Lec2-MOS Transistor Review

8/8/2019 Lec2-MOS Transistor Review

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EE141

MetricsEECS 115: Intro VLSI Design

MOS Transistor Review1

EECS 115: Intro. VLSI DesignECS 115: Intro. VLSI Design

MOS Transistor ReviewMOS Transistor Review

Fadi J. Kurdahi

EECS Dept.

UCI

[Adapted from Rabaeys Digital Integrated Circuits, Copyright 2003 Prentice Hall/Pearson]

{Adapted from Mary Jane Irwin, Penn State]


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EE141



Overview of Last Lectureverview of Last Lecture Digital integrated circuits experience exponential

growth in complexity (Moores law) and performance

Design in the deep submicron (DSM) era creates new

challenges

Devices become somewhat different

Global clocking becomes more challenging

Interconnect effects play a more significant role

Power dissipation may be the limiting factor

Our goal in this class will be to understand and design

digital integrated circuits in the deep submicron era


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Goal of this chapteroal of this chapter Present intuitive understanding of device

operation Introduction of basic device equations

Introduction of models for manualanalysis Introduction of models for SPICE

simulation Analysis of secondary and deep-sub-

micron effects Future trends


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Semiconductorsemiconductors Pure semiconductors have low and equal

concentrations ofelectrons and holes lowelectrical conductivity

Si has 4 valence electrons Phosphorous, arsenic, etc.. Have 5 electrons provide one free electron

Silicon doped w/these material becomes n-type

Dual argument applies for trivalent material(e.g. Boron, gallium) p-type


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The Diodehe Diode

n

p

p

n

B ASiO2

Al

A

B

Al

A

B

Cross-section of pn-junction in an IC process

One-dimensionalrepresentation diode symbol

Mostly occurring as parasitic element in Digital ICs

Doped

w/acceptor

impurities

(e.g. Boron).Mostly Holes

Doped

w/donor

impurities

(e.g.

Phosphorus).Mostly

Electrons


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EE141



Depletion Regionepletion Regionhole diffusion

electron diffusion

p n

hole drift

electron drift

ChargeDensity

Distance

x+

-

Electrical

xField

x

PotentialV

W2-W1

0

(a) Current flow.

(b) Charge density.

(c) Electric field.

(d) Electrostaticpotential.


7/66EE141 MetricsEECS 115: Intro VLSI Design MOS Transistor Review

7

Forward Biasorward Bias

x

p n 0

n p 0

- W 1 W 20

p

n

(W

2

)

n - r e g i o np - r e g i o n

L p

d i f f u s i o n

Typically avoided in Digital ICs

P region potential raised wrt N region

More electrons diffuse n->p, holes p->n

Current flow p->n

hole diffusionelectron diffusion

p n

hole drift

electron drift



8

Reverse Biaseverse Bias

x

pn0

np0

-W1 W20

n-regionp-region

diffusion

The Dominant Operation Mode

n region potential raised wrt p region

Less electrons diffuse n->p, holes p->n

Mostly drift Current flows p->n: very small

hole diffusionelectron diffusion

p n

hole driftelectron drift



9

Review: Diodeeview: Diode The ideal diode equation (for both forward and reverse-

bias conditions) isID = IS(e

VD

/ T 1)

where VD is the voltage applied to the junction

a forward-bias lowers the

potential barrier allowing

carriers to flow across the

diode junction a reverse-bias raises the

potential barrier and the

diode becomes nonconducting

T = kT/q = 26mV at 300K

IS is the saturation current of the diode

+

-

VD

-0.5

0.5

1.5

2.5

-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1

ID

(mA)

VD (V)

Diode Animation
http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/diode.htmlhttp://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/diode.html


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EE141 MetricsEECS 115: Intro VLSI Design MOS Transistor Review10

Diode Currentiode Current


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Models for Manual Analysisodels for Manual Analysis

VD

ID = IS(eVD/T 1)

+

VD

+

+

VDon

ID

(a) Ideal diode model (b) First-order diode model


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Junction Capacitanceunction Capacitance


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Diffusion Capacitanceiffusion Capacitance


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Secondary Effectsecondary Effects

25.0 15.0 5.0 5.0VD (V)

0.1

ID(

A)

0.1

0

0

Avalanche Breakdown


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Diode Modeliode Model

ID

RS

CD

+

-

VD


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SPICE ParametersPICE Parameters


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Review: Design Abstraction Levelseview: Design Abstraction LevelsSYSTEM

GATE

CIRCUIT

VoutVin

CIRCUIT

VoutVin

MODULE

+

DEVICE

n+

S D

n+

G


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What is a Transistor?hat is a Transistor?

VG S

V T

Ro n

S D

A Switch!

|VGS|

An MOS Transistor


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MOS Transistors -OS Transistors -Types and Symbolsypes and Symbols

D

S

G

D

S

G

G

S

D D

S

G

NMOS Enhancement NMOS

PMOS

Depletion

Enhancement

B

NMOS with

Bulk Contact


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The MOS Transistorhe MOS TransistorPolysilicon

Aluminum


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The NMOS Transistor Cross Sectionhe NMOS Transistor Cross Sectionn areas have been doped with donorions

(arsenic) of concentration ND - electrons

are the majority carriers

p areas have been doped with acceptor

ions (boron) of concentration NA - holes

are the majority carriers

Gate oxide

n+

Source Drain

p substrate

Bulk (Body)

p+ stopper

Field-Oxide

(SiO2)n+

Polysilicon

Gate

L

W


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Switch Model of NMOS Transistorwitch Model of NMOS TransistorGate

Source

(of carriers)

Drain

(of carriers)

| VGS |

| VGS | < | VT | | VGS | > | VT |

Open (off) (Gate = 0) Closed (on) (Gate = 1)

Ron


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Switch Model of PMOS Transistorwitch Model of PMOS TransistorGate

Source

(of carriers)

Drain

(of carriers)

| VGS

|

| VGS | > | VDD | VT | | | VGS | < | VDD |VT| |

Open (off) (Gate = 1) Closed (on) (Gate = 0)

Ron


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Threshold Voltage Concepthreshold Voltage ConceptS D

p substrate

B

GVGS

+

-

n+n+

depletion

regionn channel

The value of VGS where strong inversion occurs is called

the threshold voltage, VT


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The Threshold Voltagehe Threshold VoltageVT = VT0 + (|-2F + VSB| - |-2F|)

where

VT0 is the threshold voltage at VSB = 0 and is mostly a function of the

manufacturing process

Difference in work-function between gate and substrate material, oxide

thickness, Fermi voltage, charge of impurities trapped at the surface,dosage of implanted ions, etc.

VSB is the source-bulk voltage

F = -Tln(NA/ni) is the Fermi potential(T = kT/q = 26mV at 300K is thethermal voltage; NA is the acceptor ion concentration; ni 1.5x1010 cm-3 at

300K is the intrinsic carrier concentration in pure silicon)

= (2qsiNA)/Cox is the body-effect coefficient (impact of changes inVSB) (si=1.053x10

-10F/m is the permittivity of silicon; Cox = ox/tox is the gateoxide capacitance with ox=3.5x10-11F/m)


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The Threshold Voltagehe Threshold Voltage


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The Body Effecthe Body Effect

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

-2.5 -2 -1.5 -1 -0.5 0

VBS (V)

VT(

V)

q VSB is the substrate bias

voltage (normally positive for n-

channel devices with the body

tied to ground)

q A negative bias causes VT to

increase from 0.45V to 0.85V

q Can use this trick to help withpower consumption reduces

leakage currents (but slows down

the gate)

q

VSB always has to be largerthan 0.6V in an NMOS device;

otherwise the source-body diode

becomes forward biased


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Transistor in Linear Moderansistor in Linear ModeS

D

B

G

n+n+

Assuming VGS > VT

VGS VDS

ID

x

V(x)- +

The current is a linear function of both VGS and VDS


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Voltage-Current Relation: Linearoltage-Current Relation: LinearModeode

For long-channel devices (L > 0.25 micron)

When VDS VGS VTID = kn W/L [(VGS VT)VDS VDS

2/2]

where

kn = nCox = nox/tox = is the process transconductanceparameter(n is the carrier mobility (m2/Vsec))

kn = kn W/L is the gain factorof the device

For small VDS, there is a linear dependence between VDS

and ID, hence the name resistive orlinearregion


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Transistor in Saturation Moderansistor in Saturation ModeS

D

B

G

VGS VDS > VGS - VT

ID

VGS - VT- +n+ n+

Pinch-off

Assuming VGS > VT

VDS

The current remains constant (saturates).


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Voltage-Current Relation:oltage-Current Relation:Saturation Modeaturation Mode

For long channel devices

When VDS VGS VTID = kn/2 W/L [(VGS VT)

2]

since the voltage difference over the induced

channel (from the pinch-offpoint to the source)

remains fixed at VGS VT

However, the effective length of the conductive

channel is modulated by the applied VDS, so

ID = ID (1 + VDS)

where is the channel-length modulation (varies

with the inverse of the channel length)


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Long Channel I-V Plot (NMOS)ong Channel I-V Plot (NMOS)

0

1

2

3

4

5

6

0 0.5 1 1.5 2 2.5

I D( A

)

VDS (V)

X 10-4

VGS = 1.0V

VGS = 1.5V

VGS = 2.0V

VGS

= 2.5V

Linear Saturation

VDS = VGS - VT

Q u a d ra ticd e p e nd e nce

NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

cut-off


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Current-Voltage Relationsurrent-Voltage RelationsLong-Channel Deviceong-Channel Device


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Long Channel I-V Plot (NMOS)ong Channel I-V Plot (NMOS)

0

1

2

3

4

5

6

0 0.5 1 1.5 2 2.5

I D( A

)

VDS (V)

X 10-4

VGS = 1.0V

VGS = 1.5V

VGS = 2.0V

VGS

= 2.5V

Linear Saturation

VDS = VGS - VT

Q u a d ra ticd e p e nd e nce

NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

cut-off


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A model for manual analysismodel for manual analysis


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Short Channel Effectshort Channel Effects

0

10

0 1.5 3

(V/m)

n

( m/ s )

sat =105

Constant

velocity

Constant mobility(slope = )

q For an NMOS device with L of .25m, only a couple of voltsdifference between D and S are needed to reach velocity

saturation

c=

q Behavior of short channel device mainly due to

q Velocity saturation

the velocity of the

carriers saturates due

to scattering (collisions

suffered by thecarriers)

5


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Voltage-Current Relation:oltage-Current Relation:Velocity Saturationelocity Saturation

For short channel devicesLinear: When VDS VGS VT

ID = (VDS) kn W/L [(VGS VT)VDS VDS2/2]

where

(V) = 1/(1 + (V/cL)) is a measure of the degreeof velocity saturation

Saturation: When VDS = VDSAT VGS VTIDSat = (VDSAT) kn W/L [(VGS VT)VDSAT VDSAT2/2]


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Velocity Saturation Effectselocity Saturation Effects

q VDSAT < VGS VT so

the device enters

saturation before VDSreaches VGS VT and

operates more often in

saturation

For short channel devices

and large enough VGS VT

q IDSAT has a linear dependence wrt VGS so a reduced

amount of current is delivered for a given control

voltage

0

10

Short

channel

devices

VDSAT VGS-VT

VGS = VDD


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Short Channel I-V Plot (NMOS)hort Channel I-V Plot (NMOS)

0

0.5

1

1.5

2

2.5

0 0.5 1 1.5 2 2.5

I D(A)

VDS (V)

X 10-4

VGS = 1.0V

VGS = 1.5V

VGS = 2.0V

VGS = 2.5V

Line a rd e p e

nd e nce

NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

Early Velocity

Saturation

Linear Saturation


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MOS ID-VGSS Characteristicsaracter st cs

I D( A)

q Linear (short-channel)

versus quadratic (long-channel) dependence of

ID on VGS in saturation

q Velocity-saturation

causes the short-

channel device to

saturate at substantially

smaller values of VDS

resulting in a substantialdrop in current drive

(for VDS = 2.5V, W/L = 1.5)

0

1

2

3

4

5

6

0 0.5 1 1.5 2 2.5VGS (V)

long-channel

quadratic

short-channellinear

X 10-4


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Short Channel I-V Plot (PMOS)hort Channel I-V Plot (PMOS)

-1

-0.8

-0.6

-0.4

-0.2

0

0-1-2

I D(A)

VDS

(V)

X 10-4

VGS = -1.0V

VGS = -1.5V

VGS = -2.0V

VGS = -2.5V

PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V

q All polarities of all voltages and currents are reversed


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A unified modelunified modelfor manual analysisor manual analysis

S D

G

B


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Simple Model versus SPICEimple Model versus SPICE

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VDS

(V)

ID(

A)

VelocitySaturated

Linear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT


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Transistor Modelransistor Modelfor Manual Analysisor Manual Analysis


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The MOS Current-Sourcehe MOS Current-SourceModelodel

VT0(V) (V0.5) VDSAT(V) k(A/V2) (V-1)

NMOS 0.43 0.4 0.63 115 x 10-6 0.06

PMOS -0.4 -0.4 -1 -30 x 10-6 -0.1

S D

G

B

ID

ID = 0 for VGS VT 0

ID = k W/L [(VGS VT)VminVmin2/2](1+VDS)

for VGS VT 0

with Vmin = min(VGS VT, VDS, VDSAT)

and VGT = VGS - VT

q Determined by the voltages at the four terminals and

a set of five device parameters


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The Transistor Modeled as a Switchhe Transistor Modeled as a Switch

0

1

2

3

4

5

6

7

0.5 1 1.5 2 2.5

VDD (V)

Req

(O hm)

x105

S DRon

VGS VT

VDD(V) 1 1.5 2 2.5

NMOS(k) 35 19 15 13

PMOS (k) 115 55 38 31

(for VGS = VDD,

VDS = VDDVDD/2)

Modeled as a switch with

infinite off resistance and a

finite on resistance, Ron

q Resistance inversely

proportional to W/L (doubling

W halves Ron)

q For VDD>>VT+VDSAT/2, Ron

independent of VDD

q Once VDD approaches VT,

Ron increases dramatically

Ron (for W/L = 1)

For larger devices

divide Req by W/L


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MOS CapacitancesOS CapacitancesDynamic Behaviorynamic Behavior


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Dynamic Behavior of MOSynamic Behavior of MOSTransistorransistor

DS

G

B

CGDCGS

CSB CDBCGB


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The Gate Capacitancehe Gate Capacitance

tox

n+ n+

Cross section

L

Gate oxide

xd xd

L d

Polysilicongate

Top view

Gate-bulkoverlap

Source

n+

Drain

n+W


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Gate Capacitanceate CapacitanceS D

G

CGC

S D

G

CGC

S D

G

CGC

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off


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Gate Capacitanceate Capacitance

WLCox

WLCox

2

2WLCox

3

CG C

CG C S

VDS

/(VG S

-VT)

CGC D

0 1

CG C

CG C S = CG C DCGC B

WLCox

WLCox

2

VG S

Capacitance as a function of VGS(with VDS = 0)

Capacitance as a function of thedegree of saturation


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Measuring the Gate Capeasuring the Gate Cap

2 1.52 12 0.5 0

3

4

5

6

7

8

9

103 10

2 16

2

VGS (V)

VGS

Gate

Capacitance

(F)

0.5 1 1.5 22 2

I


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Diffusion Capacitanceiffusion Capacitance

B ottom

Side wall

Side wall

C hannel

SourceN D

C hannel-stop implantNA 1

SubstrateNA

W

xj

LS


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Junction Capacitanceunction Capacitance


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Linearizing the Junctioninearizing the JunctionCapacitanceapacitance

Replace non-linear capacitance bylarge-signal equivalent linear capacitance

which displaces equal chargeover voltage swing of interest


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Capacitances in 0.25apacitances in 0.25 mCMOS processMOS process


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Other (ther (Submiconubmicon ) MOSMOSTransistor Concernsransistor Concerns Velocity saturation Subthreshold conduction

Transistor is already partially conducting for voltages below VT

Threshold variations

In long-channel devices, the threshold is a function of thelength (for low VDS)

In short-channel devices, there is a drain-induced threshold

barrier lowering at the upper end of the VDS range (for low L)

Parasitic resistances resistances associated with the

source and drain contacts

Latch-up

S

G

D

RS RD


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Subthreshold Conductanceubthreshold Conductance

0 0.5 1 1.5 2 2.5

I D(A)

VGS (V)

10-12

10-2

Subthresholdexponential

region

Quadratic region

Linear region

VT

q Transition from ON to

OFF is gradual (decaysexponentially)q Current roll-off (slope

factor) is also affected by

increase in temperature

S = n (kT/q) ln (10)(typical values 60 to 100

mV/decade)

q Has repercussions in

dynamic circuits and for

power consumptionID ~ IS e(qV

GS/nkT) where n 1


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Sub-Threshold Conductionub-Threshold Conduction

0 0.5 1 1.5 2 2.510

-12

10-10

10-8

10-6

10-4

10-2

VGS

(V)

ID(

A)

VT

Linear

Exponential

Quadratic

Typical values for S:60 .. 100 mV/decade

The Slope Factor

ox

DnkT

qV

DC

CneII

GS

+= 1,~0

S is VGS for ID2/ID1 =10


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Subthresholdubthreshold ID vsvs VGSS

VDS from 0 to 0.5V

ID = IS e(qV

GS/nkT) (1 - e (qVDS/kT))(1 + VDS)

Subthresholdt res o vsvs


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ID VDSS

VGS from 0 to 0.3V

ID = IS e(qV

GS/nkT) (1 - e (qVDS/kT))(1 + VDS)


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Threshold Variationshreshold VariationsVT

L

Long-channel threshold Low VDS threshold

Threshold as a function of

the length (for low VDS)

Drain-induced barrier lowering

(for low L)

VDS

VT


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Summary of MOSFETummary of MOSFETOperating Regionsperating Regions

Strong Inversion VGS >VT

Linear (Resistive) VDS


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Parasitic Resistancesarasitic Resistances

W

LD

Drain

Draincontact

Polysilicon gate

DS

G

RS RD

VGS,eff


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