Lec 7 Instruction Pipeline Intro

7/31/2019 Lec 7 Instruction Pipeline Intro

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Instruction Pipeline: Introduction

Ajit Pal

Professor

Department of Computer Science and

EngineeringIndian Institute of Technology Kharagpur

INDIA -721302


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Ajit Pal, IIT Kharagpur

Outline

IntroductionIdeal Conditions

Implementing Instruction pipeline

CPI of a multi-cycle implementationPipeline registers

Speedup

Limits of instruction pipelining


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Introduction

The earliest use of parallelism in designingCPUs (since 1985) to enhance processingspeed was Pipelining

Computers execute billions of instructions,so instruction throughput is what matters

It is an implementation technique wherebymultiple instructions are executed in anoverlapped manner

It takes advantage of temporal parallelismthat exists among the actions needed toexecute an instruction


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Ideal Conditions

Assumptions:

Instructions can be divided intoindependent parts, each takingnearly equal time

Instructions are executed insequence one after the other in theorder in which they are written

Successive instructions are

independent of one anotherThere is no resources constraint


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Simple RISC DatapathIF ID EX MEM WB


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Pipelining of a RISC-like Processor

All ALU operations are performed on registeroperandsSeparate Instruction and data memoryOnly instructions which access memory are

load and store instructionsInstructions can be broken into the followingfive parts:

Instruction Fetch from instruction memory

Instruction decode and operand readInstruction Execution

Load/store operands (data memory)Write back results in the registers


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Instruction Fetch

IF Cycle: IR Mem [PC]; NPC PC + 4


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Instruction Decode

ID Cycle: A Regs [IR 6-10]; B Regs [IR 11-15];

Imm ((IR16)16 # # IR 16-31)


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Execute

EX Cycle: ALUoutput A + Immor ALUoutput A func B or ALUoutput A op Imm

or ALUoutput NPC + Imm; Cond (A op 0)


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Memory access

MEM Cycle: LMD Mem [ALUoutput ]or Mem [ALUoutput ] B

or If (Cond) PC ALUoutput ; Else PC NPC


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Write Back

WB Cycle: Regs [IR 16-20] ALUoutputor Regs [IR 11-15] ALUoutput

or Regs [IR 11-15] LMD


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CPI for the Multiple-Cycle Implementation

Branches and stores: 4 cycles (no WB), allother instructions: 5 cycles

If 20% of the instructions are branches orloads, CPI = 0.8*5 + 0.2*4 = 4.80

ALU operations can be allowed to completein 4 cycles (no MEM)

If 40% of the instructions are ALUoperations, CPI = 0.4*5 + 0.6*4 = 4.40

Pipelining the implementation can help toreduce the CPI


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Pipeline Registers Pipeline registersare essential part of pipelines:

There are 4 groups of pipeline registers in the 5stage pipeline.

Each group saves output from one stage and passesit as input to the next stage:

IF/ID

ID/EX EX/MEM

MEM/WB

This way, each time something is computed...

Effective address, Immediate value, Registercontent, etc.

It is saved safely in the context of the instructionthat needs it.


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Pipeline Registers

IF/ID ID/EX EX/MEM MEM/WB

inst. 1

inst. 2

inst. 3

IF


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Pipeline Registers


inst. 1

inst. 2

inst. 3

IF ID

IF


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Pipeline Registers


inst. 1

inst. 2

inst. 3

IF ID EX

IF ID

IF


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Pipeline Registers


inst. 1

inst. 2

inst. 3

IF ID EX

IF ID

IF


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Pipeline Registers


inst. 1

inst. 2

inst. 3

IF ID EX MEM

IF ID EX

IFID


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Pipeline Registers


inst. 1

inst. 2

inst. 3

IF ID EX MEM

IF ID EX

IFID


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Pipeline Registers

Typically, we will not think too much about pipelineregisters and one just assumes that values arepassed magically down stages of the pipeline


inst. 1

inst. 2

inst. 3

IF ID EX MEM WB

IF ID EX MEM

IF ID EX

. . .

. . .


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Pipeline Register Depiction

instructio

ns

IMALU

DM

IM ALU DM

IMALU

DM

IMALU

DM

Reg Reg

Reg

Reg

Reg

Reg

Reg

IF/ID

ID/EX

EX/MEM

MEM/WB

IF/ID

ID/EX

EX/ME

M

MEM/W

B

IF/ID

ID/EX

EX/MEM

M

EM/WB

IF/ID

ID/EX

EX/MEMEvery stage reads input

and writes output to

the pipeline registers


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Why is Pipelining RISC Processors Easy?

Recall the main principles of RISC:

All operands are in registers

The only operations that affect memory are loadsand stores.

Few instruction formats, fixed encoding (i.e., all

instructions are the same size) Although pipelining could conceivably be

implemented for any architecture,

It would be inefficient.

Pentium has characteristics of RISC and CISC ---CISC Instructions are internally converted toRISC-like instructions.


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Operation of Different Stages IF Cycle

IR Mem [PC]

NPC PC + 4

ID Cycle

A Regs [IR 6-10];

B Regs [IR 11-15];

Imm ((IR16)16 # # IR 16-31)

EX Cycle

ALUoutput A + Imm or

ALUoutput A func B or

ALUoutput A op Imm or

ALUoutput NPC + Imm

Cond (A op 0)

MEM Cycle

LMD Mem [ALUoutput ] or

Mem [ALUoutput ] BorIf (Cond) PC ALUoutputElse PC NPC

WB CycleRegs [IR 16-20] ALUoutputor

Regs [IR 11-15] ALUoutputorRegs [IR 11-15] LMD


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Adding Pipeline Registers


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Basic RISC Pipelining

Basic idea:

Each instruction spends 1 clock cyclein each of the 5 execution stages.

During 1 clock cycle, the pipeline canprocess (in different stages) 5 different

instructions.


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Alternative Visualization


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Speedup Assume that a multiple cycle RISC implementation has a 10 ns

clock cycle, loads take 5 clock cycles and account for 40% of

the instructions, and all other instructions take 4 clock cycles.

If pipelining the machine adds 1 ns to the clock cycle, howmuch speedup in instruction execution rate do we get frompipelining?

Average instruction execution Time (nonpipelined)= Clock cycle x Average CPI= 10 ns x (0.6 x 4 + 0.4 x 5)= 44 ns

Average instruction execution Time (pipelined)

= 10 + 1 = 11 ns Speedup = 44 / 11 = 4 The above expression assumes a pipelining CPI of 1 Should we expect this in practice? Any complications?


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Limits of Pipelining

Increasing the number of pipeline stages in a givenlogic block by a factor of k :

Generally allows increasing clock speed &throughput by a factor of almost k.

Usually less than kbecause of overheads such aslatches and balance of delay in each stage.

But, pipelining has a natural limit:

At least 1 layer of logic gates per pipeline stage!

Practical minimum is usually several gates (2-10).

Commercial designs are rapidly nearing this point.


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Optimal number of stages


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Speedup


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SummaryIntroduced the basic concepts of

Instruction pipelining

Observed that the time required toperform an individual instruction

does not decrease, but throughputincreases

Observed that the increase is

performance is not linear with thenumber of stages


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Thanks!

Lec 7 Instruction Pipeline Intro

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