LCLS Control Group LCLS-Week [email protected] Oct. 24-27, 2005 BPM Signal Processing...
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LCLS Control Group LCLS-Week Lcls- [email protected] Oct. 24-27, 2005 BPM Signal Processing T. Straumann, M. Cecere, E. Medvedko, P. Krejcik SLAC B. Lill ANL
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Transcript of LCLS Control Group LCLS-Week [email protected] Oct. 24-27, 2005 BPM Signal Processing...
LCLS Control Group
Oct. 24-27, 2005
BPM Signal Processing
T. Straumann, M. Cecere, E. Medvedko, P. Krejcik
SLAC
B. Lill
ANL
LCLS Control Group
Oct. 24-27, 2005
Overview for Stripline BPMs
Requirements/Engineering Constraints
Status
Current Frontend Design
Timeline for next 12 months
LCLS Control Group
Oct. 24-27, 2005
Objective
High precision/resolution BPM Electronics
5um resolution (R ~ 12mm)
drift < 5um/h
low bunch charge: 0.2..1nC
Stripline sensitivity: V = (a-b)/(a+b) = 2 r / R
dynamic range > 60dB + 20dB
LCLS Control Group
Oct. 24-27, 2005
Engineering Constraints
SNR expressed as position noise (LINAC Stripline; 150MHz)
dB[ r/1um ] = NF – dB[ q/1nC ] - ½ dB[ BW/1MHz ] 8dB > NF + 14dB(.2nC) – 10dB (10MHz)
noise figure including cable losses
stripline signal level based on estimation
LCLS Control Group
Oct. 24-27, 2005
Baseband vs. Mixer
Baseband• Simpler• Cheaper• Use existing cables (?)
Only marginally meets resolution requirements
Mixer• More signal at higher freq.• Proven solution• ADC performs better at IF
LO generation + distribution
New cables in LINAC needed
LCLS Control Group
Oct. 24-27, 2005
System Overview
Calibration scheme does not require extra cables
Direct digitization
LCLS Control Group
Oct. 24-27, 2005
Status
VME Digitizers + basic driver software available
Echotek
Joerger
SIS
New card ordered (13ENOB, 130MSPS, 700MHz input BW)
First frontend design + prototype (E. Medvedko)
Engineer hired (M. Cecere)
LCLS Control Group
Oct. 24-27, 2005
Frontend
f0 =150MHz (enough signal, ADC still well performing)
Low noise, 10MHz BW
Low distortion
Alias suppression
Build Prototype
Test (noise, stability, out-of band performance, linearity)
Final Design
Interface (form factor, control signals, status monitors)
Calibration
LCLS Control Group
Oct. 24-27, 2005
BPM Analog Front EndBaseband Design
BPF#1Signal from
BPM or Hybrid
BPF#2
LNA ADC
Final Amplifier
UndersamplingADC
Frequency Selection
Filter
Low Noise Amplifier
Band PassFilter
LCLS Control Group
Oct. 24-27, 2005
Baseband DesignComponent Selection Criteria
BPF#1 BPF#2LNA ADC
Freq./BW determine SNR
Low Insertion Loss
Good OOB rejection
Low NF
Low Distortion
Moderate Gain
Sharp Rolloff (Anti-
alias)
Flat Passband
High Gain*BW
Low Distortion
@ High Output Level
>= 119MSPS
High Dynamic Range
BW>= 200MHz
LCLS Control Group
Oct. 24-27, 2005
Calibration Bench Test
Measurement setup (not worse than required stability!!)
Test stability of calibration (splitters, BPM striplines)
Cross-talk issues?
Repeatability
Multiplexing (t/f)
Final design, integration
LCLS Control Group
Oct. 24-27, 2005
LCLS Cavity BPM Overview
RF BPM system current status
Planning for prototype testing
Planning for 8 LTU BPMs electrically identical to those in the undulator.
Planning for 33 undulator BPMs
LCLS Control Group
Oct. 24-27, 2005
Miteq X-Band Low Noise Receiver
Existing product line
WR 75 Waveguide Interface
Low Noise Figure (2.7 dB)
Prototype delivery date 12/10/05
Budgetary price for prototype $6500.00 (for 3 channels)
LCLS Control Group
Oct. 24-27, 2005
Prototype Receiver SpecificationParameter Specification Limit Condition
RF Frequency 11.364 GHz 20.0 Celsius
Dx, Dy, Intensity
Input Peak Power 50 watts peak No damage (limiter protection)
LO Frequency 11.424 GHz
(2856 MHz*4)
20.0 +/- 0.2 Celsius
1nC, 1mm offset, 200fs BL
LO Power Range +10 dBm Max. Provide LO for 3 down converters
IF Frequency 60 MHz Min. 20.0 +/- 0.2 Celsius
Noise Figure Dx and DY 2.7 dB Max. 20.0 +/- 0.2 Celsius
Noise Figure Intensity (reference) 4.0 dB Max. 20.0 +/- 0.2 Celsius
LO to RF Isolation 40 dB Min. 20.0 Celsius
LO to IF Isolation 45 dB Min. 20.0 Celsius
Output Power +14 dBm 1 dB compression
Conversion Gain 25 dB typical 20.0 Celsius
LCLS Control Group
Oct. 24-27, 2005
Long Lead Item Status
Receiver Prototype del. 12/10/05
Local oscillator del. 11/24/05
Waveguide del. 12/1/05
Waveguide calibration kit del. 12/9/05
CPI Vacuum windows 11/30/05
LCLS Control Group
Oct. 24-27, 2005
BPM System Test Approach
Phase I
Injector Test Stand ITSInstall single X-Band Cavity and modified off-the-shelf down converter receiver
Mount BPM on Piezo two-axis translation stage
Phase II
Bypass line test with PC gun
Install three X-Band Cavities BPMs
Bypass line test with PC gun to start June 06
LCLS Control Group
Oct. 24-27, 2005
Charge- 1 nC single-bunch
Bunch length- ~ 3 - 4 ps FWHM for ps laser
Spot size on final screen at 5.5 MeV ~ 0.75 mm rms, ps laser
Injector Test Stand ITS Beam Parameters
LCLS Control Group
Oct. 24-27, 2005
Phase I Data Acquisition Design Approach
Instrument three channel down converters with Struck SIS-3301-105 ADCs 14-bit
Single VME board will provide the data acquisition for 8 channels
Epics driver complete
Digitize horizontal, vertical position and Intensity 0 to 1 volt range
Fit Data to decaying exponential at 60 MHz
LCLS Control Group
Oct. 24-27, 2005
Phase I Testing Objectives
Test prototype Cavity BPM, down converter, and data acquisition
Generate preliminary compliance table to specification
Gain operational experience to determine if translation stage is useful, what are optimum operating parameters
LCLS Control Group
Oct. 24-27, 2005
Phase I Schedule MilestonesDesign and develop prototype Cavity BPM
Prototype non vacuum
Nov 05
Build single Cavity BPM
Dec 05
Cold Test
Dec 05
Install cavity BPM into ITS and Test
Jan 06
LCLS Control Group
Oct. 24-27, 2005
Phase II Schedule MilestonesRefine design and develop First Article Cavity BPM and support hardware
Jan 06
Build 3 Cavity BPMsMar 06
Cold TestMay 06
Install cavity BPM into APS PAR/Booster bypass line and TestJune 06
LCLS Control Group
Oct. 24-27, 2005
Phase II Testing Objectives
First Article Prototypes evaluated
Test three BPM separated by fixed TBD distance to determine single-shot
Complete test matrix
LCLS Control Group
Oct. 24-27, 2005
LTU and Undulator Planning
Receiver and LO housed in shielded enclosure below girder 20 watt power dissipation maximum
Presently BPM output on wall side
BPM output flexible waveguide section allows movement for alignment
LCLS Control Group
Oct. 24-27, 2005
BPM Mounting
BPM connects directly to the girder.
Mechanical translation stage used for alignment
BPM and Quad can be pre-aligned independently with respect to each other
LCLS Control Group
Oct. 24-27, 2005
fo= 150MHzBW = 10MHz
Lark EngineeringMS140-20-3CCInsert. Loss = 5.8dB--------------------------TTE filtersKB3T-150M-10M-50-3AInsert. loss = 4.1dB--------------------------Microwave Filter Co.3MB10-150/10-SF/SF-1Insertion loss = 3dB
SirenzaSGA-6589G = 26dBNF = 3.0dBOIP3 = 33dBm-------------------SirenzaSGA-4363G = 18dBNF = 3.1dBOIP3 = 29dBm
Sawtek854916fo= 150MHzBW = 10MHzInsert. loss = 11dB
TI OPA847GBW = 3.9GHzDistortion -105dBc
LTC2208130MSPSmax16-bit700MHz BWfsamp=119MHzReq. jitter < 350fs---------------------AD6645105MSPSmax14-bit200MHz BWfsamp=102?Req. jitter < 600fs
Alias image@ 30MHz
Baseband DesignComponents
BPF#1 BPF#2LNA ADC
NF = 2-4dB NF = 3dB
CableNF = 2-4dB
LCLS Control Group
Oct. 24-27, 2005
Input signal
-250.00
-200.00
-150.00
-100.00
-50.00
0.00
50.00
0 50 100 150 200 250 300
System Input
Coax 1
BPF 1 (150MHz)
Coax 2
LNA 1
BPF 2 (150MHz)
OpAmp 1
OpAmp 2
OpAmp 3
BPF 3 (150MHz)
Cable losses
BPF1
LNA
BPF
2
Final output
Frequency MHz
dBmBPM signal
Baseband DesignFrequency Response
LCLS Control Group
Oct. 24-27, 2005
BPMor
HybridLNA ADCRF
LO
IF
400-800MHz 43MHz
xN119MHz
MinicircuitsZFM-21 – 1000 MHzConv Loss = 5.8dB
Mixer Based BPMBlock Diagram
LCLS Control Group
Oct. 24-27, 2005
-250.00
-200.00
-150.00
-100.00
-50.00
0.00
50.00
0 100 200 300 400 500 600
System Input
Coax 1
BPF 1 (400MHz)
Coax 2
LNA 1
BPF 2 (400MHz)
Mix 1
Opamp 1
LPF 1 (40MHz)
Opamp 2
Opamp 3
Opamp 4
Comp12
Comp13
Comp14
Comp15
Comp16
Comp17
Comp18
Comp19
Comp20
Comp21
Comp22
Comp23
Comp24
Frequency MHz
dBm BPM signal
After coax
BPF1
LNA
BPF
2
mixer
Mixer Based DesignFrequency Response
LCLS Control Group
Oct. 24-27, 2005
Software Tasks
Evaluation / test software
BPM Processor
Processing algorithm
Real-time tasks: data acquisition and processing
timing
history buffers
Calibration
Integration (SLC-aware IOC, timing, feedback)
Slow controls (gain, calib, status monitors, alarms)
LCLS Control Group
Oct. 24-27, 2005
Integration; Hardware
Clock generation and distribution
Timing; triggers/gates
Calibration signal generation and distribution
Controls: gain, calib. mux
Power
Status monitors
LCLS Control Group
Oct. 24-27, 2005
Integration; Software
Timing
SLC-aware layer
Shot-to-shot feedback
High-level applications (EPICS database)
Naming
Real-time
Sysadmin; infrastructure; network
LCLS Control Group
Oct. 24-27, 2005
PDRO local oscillator
11.424 GHz
(119 MHz x 96)
Phase lock to 119 MHz ref 0 dBm +/- 3 dB
+13 dBm output power
In-Band Spurs <70 dBc
Phase noise depends on 119 MHz reference
LCLS Control Group
Oct. 24-27, 2005
Noise Estimates
Sensitivity:
-58 dBm/0.2nC/1m
Minimum bit size: 16 bits/micron@ 0.2nC
Assumes 2 gain ranges for 75 dB
Noise floor <200 nm rms
Parameter Value
Thermal noise -174 dBm/Hz
IF Bandwidth 20 MHz
Noise in-band -101 dBm
Receiver 1 dB compression
+14 dBm
Receiver gain 25 dB
Receiver noise figure 2.7 dB
LCLS Control Group
Oct. 24-27, 2005
APS Test Objectives
Develop a cavity BPM that meets system requirements and can be manufactured economically
Develop simulation model that correlates to prototype data
Transition from prototyping to production
LCLS Control Group
Oct. 24-27, 2005
Cost Savings
Reduce the dipole cavity outputs from 4 ports to 2 portsTerminate the unused ports in vacuumEliminate 2 transitions, 2 windows, waveguide, 2 magic teesProve resolution and offset performance
