LCFI POsC, July 13, LCFI Project Oversight Committee Outline CCD Clock Drive (WP3/4) External Electronics (WP4) CCD Sensors (WP2) CCD Testing (WP5) ISIS Sensors (WP2) Mechanical (WP6) LCFI POsC, July 13, CPD1 Testing o CPD1 driver ASIC Designed for large and small sensors: 40 nF at 50 MHz or 127 nF at 25 MHz One chip drives both phases with 3.3V clock swing, 21 amps/phase 0.35 m CMOS process, 3x8 mm 2 o Features Three separate modes for operation over a wide range of frequencies Designed to provide >2V pk-to-pk, up to 50MHz o Testing results Control circuitry and integrated capacitive load work well Tested to 50 MHz in test board (at right) First demonstrated operation at 50 MHz Works well, now mounted and testing in MB5.0 CPD1 50 MHz, 2nF internal load 50 MHz, 40 nF external load LCFI POsC, July 13, External Electronics Many different boards since last POsC: o CPD1 Test Board Boards completed and in use o MB5.0 Layout and production complete Several boards produced and in use o CPC-T Layout nearly complete Provides clocks, outputs and measures capacitance o BVM sequencer boards All 10 BVM2s in use; 5 more being made Plans for BVM3 coming together- significant advance o Transformer Drive Works to 45 MHz, limited by parasitic inter-winding cap Test improved designs standalone--> implement in MB5.1 o Setup copied by Oxford electron microscopy group LCFI POsC, July 13, CPC2: Next generation CCD o CPC2: second generation Column-parallel CCD Low-speed single-metal; with 100 cm 25 m and m High-speed double-metal; busline-free variant designed for 50 MHz operation 4 more wafers of each variant being produced Busline-free design a big step! CPC2-70 CPC2-40 CPC2-10 ISIS test structures Busline-free CPC2 LCFI POsC, July 13, Sensor Developments Progress with sensor production at e2v technologies: o ISIS1 with p-well complete Production complete: samples to arrive in July o CPC2 in production 4 wafers of single metal: delivery in July 4 more wafers double metal: delivery in autumn o CPC-T in production Delivery of samples beginning September Process split and number of samples rather complicated ISIS1CPC2Open phase CCD (CPC-T variant D) LCFI POsC, July 13, Bump-bonded High-speed CPC2 o Initial results Signals observed from all voltage channels Gain decrease away from chip edges Noise around e- Operated to 2 MHz; plans for >10MHz operation with MB 5.0 Noise Peak Fe-55 Peak LCFI POsC, July 13, Next Big Step: CPC2+CPR2+CPD1 o All ingredients are in place Medium-sized (CPC2-40) and small (CPC2-10) sensors mounted Intensive testing ahead in coming months Next generation CPR2A should offer improved clustering, testability, ADC performance Getting close to a prototype ladder! 104 mm Bump-bonded CPR2 Flexible cables CPC2-70 Two CPD1 driver chips LCFI POsC, July 13, New Results with CPD1 and Busline-free CPC2 o MB 5.0 Motherboard and CPD1 driver Board and chip work on first try CPD1 fast mode works with V CPD1 > 2.8V Inverter mode can deliver 1.2V clocks Slew rate control by changing number of CPD1 sections (inverter mode) Only one section needed to drive CCD o Integrated performance Good performance shown at 10 MHz CTE drops below 1.35 V; needs study Noise reduced from 200 e- (with transformer) to 75 e- CPD1 CPC2 MB5.0 LCFI POsC, July 13, New Testing Capabilities Added Liverpool: Cold testing of CPC1 Bristol: ISIS1 testing Oxford: CPC2 well capacity, capacitance testing, shot noise & integration time LCFI POsC, July 13, ISIS2 Progress o Initial work with ZMD/ZFoundry and DALSA Work started seriously earlier this year Good communication: met with company reps, many phone meetings etc. Decided to continue with both companies through design study phase o DALSA Non-overlapping poly process: our test of radiation tolerance looks good Made early ISIS designs for Prof. Etoh Initial feasibility study and layout by DALSA good ideas, good discussion Work-around for deep p+ implant, but CMOS circuitry still to be solved DALSA-Eindhoven too busy with big customer --> contacted DALSA-Waterloo o ZMD/ZFoundry Mixed 0.6m CMOS/CCD process (C7C) Initial work with design kit looked quite promising Have: buried channel implant, 2-level poly, CMOS elements, extensive experience with deep implants with controlled tails Need: to incorporate deep implant in C7C process Company sold in late March --> new owner (Xfab) not interested in new development for old process LCFI POsC, July 13, ISIS vendor possibilities --> Many companies, no perfect fit. CompanyProcessSize( m)Challenges DALSAmixed0.35CMOS elements, routing JazzCMOS0.18Need buried channel, poly Lincoln Labsmixed0.18Mixed process being developed XFAB (Zfoundry)mixed0.6Not willing to modify old processX TowerCMOS0.35Need buried channel, polyX CSEMmixed0.35Mixed process being developed? PanasonicCCD/mixed