Latest Developments from the

CCD Front End

LCWS 2005

Stanford

Joel Goldstein, RALfor the

LCFI Collaboration

Joel Goldstein, RAL LCWS 3/05 2

Outline

1. Reminder:• ILC Vertex Detector

• Column Parallel CCDs

• Conceptual Readout Scheme

2. First Generation Prototypes

3. Second Generation Prototypes

Joel Goldstein, RAL LCWS 3/05 3

The Vertex Detector

• 5 layers (15-60mm)

• ~ 0.1% X0 per layer

• 20 m 20 m pixels

• 800 million channels

• Background rates force readout – 50 s for Layer 1– 250 s for Layer 2

Joel Goldstein, RAL LCWS 3/05 4

Column Parallel CCDs

• Separate readout for each column

• Readout ASIC bump-bonded to CCD

• ASICs contain amplifiers, ADC and digital processing

N+1

Column Parallel CCDReadout time = (N+1)/Fout

Joel Goldstein, RAL LCWS 3/05 5

Ladder Readout

• Layer 1 read out 20 times per bunch train 50k z pixels

• Layers 2-5 read out 5 times per bunch train 31k z pixels

4.4 GPixels in total

Have to sparsify at front end

CPR

6250 rows x 5 readout frames = 31250 z-address range(15 bits)

1100 f-addressrange(11 bits)

L2 - L5 CCDs31 bits

+CPR

2500 rows x 20 readout frames= 50000 z-address range

(16 bits)

650 f-addressrange(10 bits)

L1 CCDs31 bits 31 bits

+-CPR

CPR31 bits

-

L2 - L5 CCDs

Joel Goldstein, RAL LCWS 3/05 6

CCDoutputstage

CCDoutputstage

Bumpbond

Bumpbond

Comp CompPixel

thresh

Pipeline 2 x 2kernel

Pipelineto

adjacentkernel logic

toadjacent

kernel logic

d/dtd/dt

to otherreadoutchannels

G

ADC

Gate

FIFO

Memory

64-column Multiplexer

CompClusterthresh

G

ADC

Gate

FIFOVerticaladdress

fromcol (n-2)

col 1 col (n-1) col n col 64

fromcol (n+1)

CCD

ReadoutChip

CCDoutputstage

CCDoutputstage

to otherreadoutchannels

ERF ERFDetector

Level

DAQ

Amplification

ADC

Filtering

Clustering

Multiplexer

Joel Goldstein, RAL LCWS 3/05 7

Front End Readout Chain

Dataformatting

De-serialiser

De-serialiser

De-serialiser

De-serialiser

De-serialiser

Data collection sequencing

Readout Control (FPGA)

L1

L2

L3

L4

L5

6.1 Mbytes (120 msec)

2.9 Mbytes (58 msec)

1.1 Mbytes (22 msec)

220 kbytes (4 msec)

220 kbytes (4 msec)

Pipeline ring busflex-circuitCPCCD

readoutchips

5 LVDS serial bitstreams(400 Mbit/s)

L5L4L3L2L1 Readout chip control

Secondarystorage

(10 Mbytes)

OpticalTx

Serialiser

Single opticalfibre (1 Gbit/s)

OpticalRx

Single opticalfibre (1 Gbit/s)

De-serialiser

Dataout

Controlin

Dataformatting

De-serialiser

De-serialiser

De-serialiser

De-serialiser

De-serialiser

Data collection sequencing

Readout Control (FPGA) DAQ Card

1.3 million hits = 20 Mbytes per bunch train

Joel Goldstein, RAL LCWS 3/05 8

First Prototype CPC/CPR

• Column parallel CCD principleproven

• Noise < 100 electrons

• Minimum clock ~1.9 V

• No sparsification in ASIC

Charge Amplifiers(inverting)

Voltage Amplifiers(non-inverting) 6 keV X-rays

Joel Goldstein, RAL LCWS 3/05 9

Next Generation ASIC

• No major changes to amplifiers or ADC

• Digital cluster finding:– 2x2 kernel

– Extended cluster read out

Expanded cluster to be read out

0000

0000

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 5 5 0

0 0 0 0

0 0 0 0 0 0 0

0 0 0 0 0 0 0

0 0 0 0 0 0 0

0 0 0 0 0 0 0

0 0 0 0 0 0 0

0 0 5 5 0 0 0

0 0 0 0 0 0 0

Cluster found

0 0 0 0 0 0 0

0 0 0 0 0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

Joel Goldstein, RAL LCWS 3/05 10

CPR-2

Output Sparsification Cluster Binary 5-bit ADC Preamp Input & Multiplexing Finding Conversion

DATA

Joel Goldstein, RAL LCWS 3/05 11

CPR-2

• IBM 0.25 m

• 6 x 9.5 mm

• Chips have arrived at RAL

• Stand alone testing starting

• Test features:

– direct analogue I/O pads

– I/O serial register between ADCs and cluster logic

Joel Goldstein, RAL LCWS 3/05 12

Summary

• First generation CPCCD/ASIC tested

• Second generation ASIC ready for testing

• Cluster finding implemented

• Sparsification at front end

– Major steps on road to ILC readout