Latch Up Prevention

EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS

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Kenneth R. Laker, University of Pennsylvania


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-> ESD PROTECTION CIRCUITS (INPUT PADS)-> ON-CHIP CLOCK GENERATION & DISTRIBUTION-> TRANSLATION BETWEEN OFF & ON-CHIP LOGIC LEVELS-> OUTPUT PADS-> ON-CHIP NOISE DUE TO PARASITIC INDUCTANCE-> LATCH-UP PHENOMENON


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ESD PROTECTION

1 MΩ

100 pF

1.5 kΩ

DUT+−V

esd

HUMAN BODY MODEL MACHINE MODEL

1 MΩ

200 pFDUT+

−Vesd

ESD TESTERS: LUMPED ELEMENT MODELC

S

CC

DUT+

-V

LS

RS C

t

I Component HBM MMC

C (pF) 100 200

RS (Ω) 1500 25

LS (µΗ) 5 2.5

CS (pF) 1 0

Ct (pF) 10 10

Simulates the touch from a charged human’s finger.

Since in MM body resistance is absent, contact with machines can be higher stress.


4

VDD

input pin

to circuits on dieV

A

-0.7 V < VA < V

DD + 0.7 V

PROTECTION NETWORK (PN)

1 - 3 kΩ

Effective protection networks can withstand up to 8 kV HBM ESD stress.


5

VDD

PNA

E

XINPUT SERIES TRANSMISSION GATE CIRCUIT

TGA

E

X

A -> EXTERNAL (OFF-CHIP) input signalE -> INTERNAL (ON-CHIP) enable signalX -> INTERNAL (ON-CHIP) output signal

X = A, when E = 0X = HIGH-IMPEDANCE STATE when E = 1

NOTE: ANY UNUSED INPUT TERMINALS SHOULD BE TIED TO V

DD OR GND USING WEAK PULL-UP OR PULL-DOWN

TRANSISTORS RATHER THAN FLOAT


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VDD

PNA XA X

INVERTING INPUT CIRCUIT

VOL

= 0.8 V

NMH

NML

VOH

= 2.0 V

TTL

Vin

= A

CMOS

VIH

VIL

Vth

Vout

= X

VOH

= VDD

Vth

VOL

= 0

Vout

= V

in

VIL V

IH2.0

Vin

= A

0.8

LEVEL SHIFTING FROM TTL TO CMOS

DESIGN FOR Vth

= 0.8 V + (2.0 V - 0.8 V)/2 = 1.4 V

X = A

NML = V

IL - V

OL

NMH = V

OH - V

IH


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Vout

= X

VOH

= VDD

Vth

VOL

= 0V

IL VIH

2.0V

in = A

0.8

PM-NM

PH-NL

PL-NH

PM-NM => nominal processingPH-NL => strong pMOS, weak nMOS process cornerPL-NH => weak pMOS, strong nMOS process corner

IN ADDITION:Strong (fast) nMOS, pMOS -> low V

Tn0, low |V

T0p|; high k

n, high k

p

Weak (slow) nMOS, pMOS -> high VTn0

, high |VT0p

|; low kn, low k

p

VARIATIONS IN LEVEL SHIFT VTC DUE TO PRCESS VARIATIONS

Worst Case Simulation Method

Models are first partitioned into their main types, that is NMOS, PMOS, R, and C. All possible combinations of these types are then run. However, in practice, in order to reduce the number of simulation runs R and C are grouped together.

For example, if a design contained NMOS and PMOS, the following sets would be run: 1. weak nmos, weak pmos, weak temp.2. weak nmos, nominal pmos, weak temp.3. weak nmos, strong pmos, weak temp.4. nominal nmos, weak pmos, nominal temp.5. nominal nmos, nominal pmos, nominal temp.6. nominal nmos, strong pmos, nominal temp.7. strong nmos, weak pmos, high temp.8. strong nmos, nominal pmos, high temp.9. strong nmos, strong pmos, high temp. A total of 9 runs.

If R and C are included, the number of runs would increase to 27. Kenneth R. Laker, University of Pennsylvania

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DIFFERENTIAL SIGNALING (LOGIC LEVELS) FOR GBPS SYSTEMS

LVPECL (low-voltage positive referenced emitter coupled logic) LVDS (low-voltage differential signals)

HSTL (highspeed transceiver logic)CML (current-mode logic)


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10OUTPUT CIRCUITS AND L(di/dt) NOISE

VDD

Z

D

CK

TRISTABLE OUTPUT CIRCUIT

Z = D for CK = 1Z = HIGH IMP for CK = 0

6 transistors

Large W/L

LARGE W/L-> Sufficent current sink, source-> Reduce delay times

Z

CK

D

CKV

DD

D

ZCK

12 transistorsLarge W/LP

N

CK D P N Z1 1 0 0 1 = D1 0 1 1 0 = D

or superbuffer

or superbuffer

or superbuffer


11LARGE W/L-> Sufficient current sink, source-> Reduce delay times

=> LARGE di/dt

L (di/dt) VOLTAGE DROP ACROSS BONDING WIRE CONNECTING PAD TO PACKAGE PIN

t

VOH

VOL

Vin

, Vout

T/2 T

t

nMOS ON

nMOS ON

pMOS ON

iC

didt

max

≥ Imaxts/ 2

= 2 Imaxts

≥ 4 CloadVDD

ts( )2

0 tst

s/2

Imax

iC(t)

t

0.1 to 10 A/ns


12

LET Cload

= 1 pF, L = 1 nH, VDD

= 3.5 V and ts = 1 ns

HIGH-END MICROPROCESSOR CHIPS WITH 32 BITS OR 64 BIT DATA BUS LINES - ALL OTPUT DRIVERS SWITCHING AT THE SAME TIME!

didt

max

≥ 4CloadVDD

ts( )2

For 32 bits switching simulataneously:

PROBLEM!


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PRECHARGES INVERTER OUTPUT “Z” TO VDD

/2 WHEN ST = 1 AND CK = 0 (JUST PRIOR TO CK -> 1)

REDUCE L(di/dt) NOISE

(dVout

/dt)max

= VDD

/2

VDD

D

ZCK

ST = 1

CK = 0, VDD

CK = 0, 0 V

VDD

/2

ALSO, STAGGER SWITCHING TIMES OF 32 OUTPUT DRIVERS BY USING BULT-IN DELAYS IN THE CLOCK DISTRIBUTION NET.

VDD

OVDD

/2IN

2ZO

2ZO

To a Z0

transmission line

B

C

A

IN

A

B

C

O VDD

/2

DIFFERENTIAL DRIVER CIRCUIT


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POS. PULSE ON FALL OF IN ONLY

NEG. PULSE ON RISE OF IN ONLY

DIFFERENTIAL SIGNAL wrt VDD

/2


15BIDRECTIONAL BUFFER CIRCUIT WITH TTL INPUT CAPABILITY

Z

E

D

E

TS

TTLDI

VDD

D

ZE

VDD

PN

DI

TTL Level Shift

Tri-state Output


16ON-CHIP CLOCK GENERATION AND DISTRIBUTION

CK

CK

RING OSCILLATOR

SIMPLE ON-CHIP CLOCK CIRCUIT

CK FREQUENCY-> PROCESS DEPENDENT-> UNSTABLE FREQUENCY

Rbias

CrystalC

1 C2

PIERCE CRYSTAL OSCILLATOR CIRCUIT

-> GOOD FREQUENCY STABILITY


17TWO-PHASE CLOCKING SCHEMES

phi1

phi2

Tc

clk phi1

phi2

CLOCKDECODER

PRIMARY CLOCKS FROM

XTAL CONTROLLED OSCILLATOR

CK1CK2CK3CK4


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CLOCK GEN

GENERAL LAYOUT OF H-TREE CLOCK DISTRIBUTION NETWORK FOR UNIFORM CLOCK DISTRIBUTION

C AD Techniques to automate the generation of optimum clock distribution networks.


19PLL CLOCKING SCHEMES

ddata

= dout-reg

+ dpad

clk

clk pad

output pad

R

C

ddata

= dclk-buf

+ dRC

+dout-reg

+ dpadclk

dclk

data out

chip

clk

clk pad

R

C

clkd

clk

data out

chipPLL

output pad

WHY USE PLL IN SYSTEM CLOCKS?

+ To syncronize the internal clock of a chip to an external clock - reduce skew.

+ To operate an internal clock at a higher rate than the external clock input.

Phase Detector Filter VCOclk

÷ n

output - clk

clk-out clk-out

clk-out clk-out

buffer

output register


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Generates an internal fclk-out = 4 × fclk synchronized to clk

clk

clk pad

output pad

R

C

chipPLL

÷ 4

clkclk-out

ddata

= dout-reg

+ dpad


21LATCHUP IN CMOS CIRCUITS

Rsub

Rwell

VDD

IE2

VB-npn

IRsub

IRwell

I

VB-pnp

IE1

I

Q1 (PNP)

Q2 (NPN)

+

−

V

V

I

0

2.0 mA

VH = 1.5 V

trigger pointIH

slope = 1/RT

VDD

VH

IHR

T

SCR EQIV CKT in Latch-up

latch-up susceptability proportional to

Rwell

n+ p+ p+n+

VDDV

out

n+p+

n-wellp-sub

Vin

NPNPNPR

sub

Rwell


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LATCH-UP CONDITION

Rsub

Rwell

VDD

IE2

VB-npn

IRsub

IRwell

I

VB-pnp

IE1

I

Q1 (PNP)

Q2 (NPN)

+

−

V

At the on-set of latch-up

V

I

0

2.0 mA

VH = 1.5 V

trigger pointIH

slope = 1/RT

VDD

VH

IHR

T

SCR EQIV CKT in Latch-up

I > IH = (V

DD - V

H)/R

T


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A. Use a latchup resistant process.Latchup Prevention LAYOUT Guidelines:

B. Use p+ guard rings connected to GND around nMOS transistors and n+quard rings connected to VDD around the pMOS transistors to reduce Rwell and Rsub and to weaken BJTs.

C. Place sub, well contacts close to the nMOS, pMOS source connections to supply rails (i.e. GND for nMOS, VDD for pMOS) to reduce Rwell and Rsub.

CONSERVATIVE RULE: One sub contact per source connection to a supply, or GND.

LESS CONSERVATIVE: One sub contact per 5-10 transistors.

D. Layout nMOS, pMOS transistors close to GND, VDD rails, respectively and maintain space between nMOS, pMOS transistors.

Reduce αnpn

, αpnp

; Reduce Rsub

, Rwell

make small

make largeLATCH-UP PREVENTION

TO PREVENT LATCH-UP: Insure Latchup Condition is Violated!

LATCHUP OCCURS IF SATISFIED-


24INVERTER AND I/O BUFFER CELL LAYOUT USING LATCH-UP GUIDELINES

(a) (b) Latchup Protection Using

p+ guard ring to GND

n+ guard ring to V

DD

(c)

n-welln-well

n-well

Latch Up Prevention

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