Better Understanding of Cmos Latch Up

7/30/2019 Better Understanding of Cmos Latch Up

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HU: A BETTER UNDERSTANDING O F CMOS LATCH-UP 63

R L - -=4sn p -S I

Fig. 1. Crosssection of a CMOS invertor. R , and R, represent heresistance associated wi th the well and the substrate, espectively.

VDD

4Fig. 2. Basic equivalent c h i t of a CM OS inverster for latch-up study.

11. A GENERAL RITERION OR LATCH-UPBefore the actual 2-D simulation is performed, theequivalentcircuit is used to derive a generalized latch-up criterion. Thislatch-up riterion which is a more general condition hanal +all >1 or Plpil >1, canbe obtained rom Fig. 2. As-suming that the p-n-p-n structure is in a low-impedance state,one finds

where al and all are the common-base dc current gain of thevertical p-n-p and lateral n-p-n transistors,espectively, and ,, isthe collector saturation current. By rearranging (l), one has

whereI,, =ICol+I,, 11 .for a nontrivial solution I ,#0, t is foundIn a low-impedance state, the term Z,,/It is negligible, and

al t all=1+elal +ellall (3a)or

PlPII =1+e lP l (P l l +1)+e I l P l l (PI+1) (3b)where

and

Equation (3) is a generalized latch-up criterion fora four-terminal device. I t expresses the relationship of as and 8sina low-impedancesteadystate. 8 represents thecontribu-tion of the resistors R, and R, in preventing the atch-up.Undernormalconditions, 8 ranges between :I and 0. 8=1means all the emitter current is bypassed through the resistor(R, or/and R, =0), and (3) can never be satisfied; thus nolatch-up can occur. On the other hand, in the case of a two-terminal p-n-p-n structure (Shockley diode) [:6] 81=8 1 =0and (3) reduces to the conventional expression for the latch-upcriterion

a1+a11 =1 ( 44

PlP l l =1. (4b)or

I t is clear that this well-known criterion is only a special caseSeveral points may be worth mentioning here. The relation-ship shown by (3) has been used to define the center junctionof a one-dimensional p-n-p-n structure gaing from reverse bias

to forward bias [7] , [8] . I t also has been suggested that, basedon a power supply constraint, an expression similar to (3) canbe used as a necessary condition or atch-up o occur [4],[9]. Furthermore, (3) was used to described the atch-upholding current [9]. However, one should understand that (3)has a much wider application than any of the previous sugges-tions; (3) is a sufficient condition for a p-n-p-n device being ina steadystate.A lthough (3) is derived from he equivalentcircuit shown in Fig. 2, the inal mathematical expression doesnot contain either R, orR,; thus the resistance values are ofno mportance. n act, (3) is valid whetherornototherresistancessuch as those associated wi th the base, col lector,or emitter of the parasitic transistors are included. Therefore,theuncertainty of determining he resistance value for acomplete wo-transistor equivalentcircuit is eliminated,andinstead a well-defined parameter 8 is used.If carrier generation in the center junction f a p-n-p-ndevicetakes place (for instance, by light or radiation), an additionalterm IGENERA TIONIZ~,which is similar to Ic,/It should beadded to he eft-hand side of (3). However, under normalFET operatingconditions, hemagnitude of the generationcurrent is not significant. Thus this term may also be ignored.

of (3).

111. DETE RM IN ATI ONF THE LATCH-UP HRESHOLDBothasand the8s are functions of current. Itwill be shownthat onceas and0sare determined as functions of current, the

latch-up threshold can be predicted. The structure shown nFig. 3 will be used for demonstration in this study. I t hasbeensuggested that the conventional way of measuring a in CMOSstructures does not give true values [101. This is because thebase current of the measured transistor is supplied by the ex-ternal base-emitter bias during the. medsurement, while inareal situation, the ase current is supplied by he complementarytransistor. The pattern of the current low within the structureis totally different between the two cases. In order to modelthecurrent flow na more realistic fashion, wodifferentstructure configurations depicted in Figs. 4 and 5 were used


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64 IEEE TRA NS/.CTIONS ON ELEC TRON DEV ICES, VOL . ED-31, NO. 1, JANUARY 1984VD D

TI T22pm

Fig. 3. A p-n-p-n structure used for the2-D simulation of latch-up.

L-- ~ i ._~21-Fig. 4. Part of the structure shown in Fig. 3 used to determinea11md

0 1. Zcl s acurrent source replacing the vertical p-n-p transistor.

Fig. 5. Part of the structure shown in Fig. 3 used to determineai nd01. 1,ll is a current source replacing the lateral n-p-n transistor.

to determine a's and 0's. In Fig. 4, current sourceIcl is usedto replace the vertical transistor so thatno atch-up can beinitiatedand hecurrent flow resembles the real situaticln.Accuratea11 and 8 1 as functions of current can thus be obtainedfrom electron and hole current components computed at ;:heterminals. Similarily, al( I) and O1(Z) are determined from 1:h.econfiguration shown in Fig. 5. The results acquired for VDL=3 V areshown n Figs. 6 and 7. If one defines the smalloattotal current at which (3) is satisfied to be the threshold vu-rent ITHRESHOLD, then in this case, ZTHKESHOLD=51yA//.mof width. I t is interesting to note that

a1 t all< t elaL ellall I[5 )al t all>1t elal t e llall 116)

is satisfied for I ,ITH RESHOLD. Since the a's will continue! todecrease after 0 saturates as current increases, (3) will besatisfied again at a current level Z (latch current) higher thanZTHRE~HOLD . For current even higher than I,, al tall < t8lal t 011a11 s always valid. This situation is il lustrated. nFig. 8 where a's and 8's are obtained from Figs. 6 and 7, a I dthe latch-up current I, is determined by a separate simulatic'n.So, (3) is satisfied at two current levels, i.e., at I ,=ZTHRESFI-OLD and[, =Z . Whereas, inequality (5) or (6) holds, elsewhae.I t can readily be shown that inequality 5) leads toZcl


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HU: A BETTER UNDERSTANDING OF CMOS LATCH-UP 65

looti

0 1 2 3 4 5 6VD 0 (volts/

Fig. 9. Predicted latch-up triggering threshold current versus the powersupply voltage. This is obtained rom the as and the 0s following(3).

Fig. 10. Equivalent circuit or atch-up riggering experiment. Besidesthe power supply VDD,an additional bias VBIAS is applied to stim-ulate n-p-n transistor.bias changes the equivalent circuit rom Fig. 2 to Fig. 10(assuming current injection through n-p-n). Under this circum-stance, the current I , becomes negative and consequently 0 isnegative too. This change in 0 value causes the (3) to besatisfied at a lower current level. Since the intrinsic 0 1 for theCMOS with epitaxial layer approach is much bigger than 01,the value and sign change in 011results i n a greater impact onthe measurement of latch-up triggering current than does 01;this means lateral triggering is easier than vertical triggering inthe experiment. Because the additional external bias (in addi-tion to the biases for the properCMOS operation) changes thelatch-up equivalent circui t, the measured triggering current isnot the intrinsic latch-up threshold for the circuit without thisadditional bias. Therefore, the triggering current measured nthis case may be considered as an extrinsic latch-up threshold,and an extrinsic atch-up threshold may vary with dif ferenttriggering methods.

IV . DYNAMIC RIGGERINGF LATCH-UPN 2-DIn a p-n-p-n structure, the switching from a high-impedanceoff state to a low- impedance on state is a transient phe-nomenon. This fast transition makes the study of this phenom-enonxtremely if ficult. Now withhe advancement innumerical analysis, transient simulation provides a feasiblewayto study this dynamic behavior. In the following a demonstra-tion of dynamic triggering of a p-n-p-n latch-up is presented.

STEADY STATE

Fig. 11. A steady-statepotentialdistributionat he high-impedanceoff state.

AFTER 16nsVDD3V

Fig. 12. An instantaneouspotentialdistri bution during the atch-uptriggering process.The FIELDAY [l11 program is used, for this simulation, andthe simulated structure is the one shown n Fig. 3. Fig. I 1shows the initial potential distribution at the highrimpedanceoffstate, where the well bias V , =Voo. Insuchplots,zero potential orrespondsohe ermi level inntrinsicsilicon at zero bias. Thus at zero bias, the potential of n-typesilicon is positive andp-type is negative. Note hat well-to-substrate junction is reversely biased. The latch-up is triggeredby forward biasing the p+-well junction. By lowering downV, to 2.2 V , the p-n-p transistor is turned onhard enough toinitiate apositive feedback rom hen-p-n transistorwhichcauses the total current toncrease. Fig. 12shows the potentialdistributionafter V, =2.2 V for 1.6 ns. EIoth the p+-welljunction and the n+-j unction re forward biased. This is due toa large number of holes injected from the emitter of the p-n-ptransistor into the col lector (the substrate) which causes thepotential of the substrate to rise, in turn forward biasing the


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66 IEEE TRANS8P,CTIONSON EL ECTR ON DEV ICES, VOL. ED -31, NO. 1, JANUARY 1984AFTER 2.6 ns

VDD 3vh

Fig. 13. An instantaneouspotentialdistributionduring he latc11-uptriggering process.AFT ER 1.1 nsv =3v

vw =3v

Fig. 14. A n instantaneouspotentialdistribution during the atck-uptriggering process.STEADY STATE

VDD = 3v/ vw i 3v

Fig. 15. The potential distributionof the latch-up on state.nmbstrate unction. Nevertheless, it is found hat becaI.s,ethe total current at this stage is still smaller than the threshcidcurrent, the positive feedback cannot sustain after V , returns

7- 1

i1I I I

I 2 3 4 5 6 7VDD ( V o l t s )

Fig. 16. Simulated ow-impedance steady-state I-V characteristics forthe structure in Fig. .to 3 V . Fig. 13 shows the state after V, is kept at 2.2 V for2.6 ns. There, the total current has ncreased to an even higherlevel. A fter totalof 3.1 ns at 2.2V , the bias at thewell terminalis returned o3 V . Because the otalcurrentat this stageexceeds ITHRESHOLD, latch-up can e triggered. Fig. 14depictsthepotentialafter Vw returns to 3 V for 1.1 ns. The inallatch-upcondition is shown n Fig. 15.There, he n-well isindistinguishable, and the entireegion is flooded with electronsand holes ~m - ~) .heotal urrent is close to1A/pmof width.V. STEADY -STATE- V CHARACTERISTICSF LATCHUPStarting from a latch-up state one can determine the steady-state I- V characteristics by either varying the voltage and com-

puting the current or varying the current and computing thevoltage. With this method, thelow-impedance steady-statel-Vcharacteristic is obtainedandplotted n Fig. 16.Note heportion of the curve for I ,


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HU: A BETTER UNDERSTANDING OF CMOS LATCH-UP- STEADY STATE

2

Fig. 17. The potential distribution at I , =lTHRESHOLD.his steady statesanunstable state.

Fi g. 18. M easured ow- impedance steady-state Z-V characteristics. Thiscurve is traced from high current to ow current. Due to the unstablenature of the lower part of the curve, further trace towardven lowercurrent is not obtained.

lorn IOopA Im A IOmA IOOmAI T ~ T A L ( ~m- )

Fig. 19. Simulated as and 0s which are determined at dif ferent cur-rent levels corresponding to the curve shown in F ig. 16. A t ll currentlevels, (3) is satisfied.low-impedance state does not correspond to the holding cur-rent. Actually, at east in principle, the minimum low-impe-dance currentwhichcorresponds o atch-up hreshold willcontinue to decrease as voltage increases unti l junction breaksdown. Thus there is no well -defined minimum current. On theother hand, there is a ocal minimum n voltage, namely theholding voltage. Below this voltage, there is no low-impedance

6 1

solution. Above thisvoltage, thereare wo low-impedancksolutions corresponding to eachvoltage; theower-currentsolution, whichhasa negative impedance, is the atch-upthreshold and the higher-current solution, which hasa positiveimpedance, is the atch-uponstate.The as and 0s cor-responding to the curve of Fig. 16 are recorded n Fig. 19.As predicted,heentire teady-state I-V curve, both hepositive-impedance part as well as the negative-impedancepart, satisfy the relationship of (3).

VI . SUMMARYThe two-transistor equivalent circui t and theirect simulationusing finite-element analysis are shown to be useful in under-standing the latch-up phenomena. It also has been shown thatall the low-impedance steady states of p-n-p-n structure satisfythe relationship state by (3). This latch-up criterion is goodfor 2-, 3-,and 4-terminal p-n-p-n devices. Even with the factthat the resistances associated wi th a real CMOS structure areof distributed nature, (3) is always valid because the mathe-maticalexpressiondoes not contain any resistance value. I tis found that besides the high-impedance off state, there are

two low-impedance steady states correspondingo every voltagegreater than the holding voltage. The state ,atlower currentlevel is the latch-up triggering threshold and the one at highercurrent level is the latch-upon state. The latch-up triggeringthreshold of a p-n-p-n structurecan be predicted if the 0s andas can be determined as functions of current. Since there isno minimum current associated with the atch-up I-V char-acteristic, thus physically, the holding voltage is a more mean-ingful term than theholding current.

ACKNOWLEDGMENTThe author would ike to acknowledge the valuable assistanceof M . Pinto, S.K ordic, and S. Laux. The author is also grate-ful to L . Terman, R. Dennard, and H. Y u for their encourage-

ment during the course of this work.REFERENCES

[I F. E. Gentry, F. W. Gutzwiller, N. Holonyak, Jr., and E. E. V onNJ : Prentice-Hall, 1964.Zastrow, Semiconductor Controlled Rectifies. Englewood Cliffs,[2] J . . Ebers, Four-terminal pnpn transistors, Proc. I RE, vol. 40,p. 1361, 1952.[3] E. L . Gregory and E. D. Shafer, L atch-up n CM OS integratedcircuits, ZEEE Trans. Nucl. Sci., vol. NS-20, p. 293, Dec. 1973.[4] D. E. Estreich, T he physics and modeling of atch-up and CM OSUniv., Tech. Rep. G-201-9, Nov. 1980.integrated ircuits,Dep.ofElectricalEngineering, Stanford[5] G. J . Hu, M . R. Pinto, and S. K ordic, Two-dimensional simula-tion of latch-up n CM OS structures, presentedat the 40theviceResearch Conf. (FortCollins, CO), paper VA -5, une 1982.[6] Sze, Physics of semiconductor Devices. New Y ork: Wiley-Inter-science, 1969.[7] J . F.Gibbons, A critiqueof he heory ofp-n-p-n devices,

[8] W. D. Raburn, A model for the parasitic SCR n bulk CM OS,ZEEE Trans. Electron Devices, vol. ED-11, p. 406, 1964.inZEDM Tech. Dig., p. 252, Dec. 1980.[9] A . Ochoa,W. Dawes, and D. Esteich, Latch,.up control in inte-gratedcircuits, ZEEE Trans. Nucl. Sci., vol.NS-26,p.5065,1979.[ l o] A . Ochoa and P. V. Dressendorfer, A discussion of the role ofdistributed effects in latch-up, ZEEE Trans, Nucl. Sci., vol. NS-28, p. 4292, 1981.[111 E. M. Butula, P. E. Cottrell, E. E. Grossman, and K . A . Salsburg,ZBMJ. Res. Develop., vol . 25, p. 218, 1981.

Better Understanding of Cmos Latch Up

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