Lab 3: VHDL Layout Generation Using First Encounter

1. First Encounter Setup gfxlab13% cd $CDSVHDL gfxlab13% mkdir fe gfxlab13% cd fe gfxlab13%cp $DSMSE/ece753.conf ece753.conf 2. Invoke First Encounter gfxlab13% encounter The window will show up like below (FE window)

Figure 1. First Encounter (FE) Window

1

3. Import the design. Invoke (FE window) > Design -> Import, this will display the Design Import window, see Figure 2. Click the "Load " button at the bottom of the window and select the configuration file “ece753.conf”. Then click OK,

Figure 2. Loading Configuration File. Figure 3 will display, with entries filled up as shown. The configuration file “ece753.conf” supply all the entries or this particular lab, Lab3. For other lab, only two entries need to be modified:

2

Verilog Files: ../xorgate/src/xor.v should be change to your verilog source filename. Top Cell: By User: xorgate should be changed to the entity name of your design.

Figure 3. Design Import file for Lab 3 4. Specifying Floorplan (FE window)>Floorplan>Specify Floorpan. A Floorplan window will pop up. Just click OK.

3

Figure 4. Floorplan Window 5. Add power and ground ring (FE Window)Floorplan -> Custom Power Planning -> Add Rings. The Add Rings window will display. Make sure the following entries are modified as follows: In Ring Configuration section

4

Top: Bottom: Left: Right: Layer: Metal3 H Metal3 H Metal2 V Metal2 V Width: 4 4 4 4 Offset: select Center in channel button. Make sure it matches the entries in Figure 5. Then Click OK. The floorplan with power ring will display, see Figure 6.

Figure 6. Floorplan with power rings 6. Route the power grid (FE Window)> Route>SRroute, use the default value. Click OK. This will display the vdd and gnd power lines, shown as two blue (metal1) horizontal lines, see Figure 7.

5

Figure 7. vdd and gnd power grids. 7. Place and Routing To place the cells, invoke (FE Window) >Place -> Place. Use the default value, click OK . To route the design, invoke (FE Window) >Route -> Nanoroute. Use the default value, click OK. Click the physical view icon (the last one of the three icons in the top right corner). This will display the complete layout of the xor gate, see Figure 8.

6

Figure 8. Xor layout. 8.Verify the Routing (FE Window)> Verify, use verifying tools to verify the design. Follow the error messages to make change of the routing. 9. Exporting the design (FE Window)> Design>Save>DEF Export the design file name as “xor.def” Exit First Encounter

7