Lab3 Cadence

8/4/2019 Lab3 Cadence

1/16

Laboratory Work in Analog LSI Circuits. Laboratory #3, Spring 2000.

J. Jacob Wikner, [email protected] 27/1 - 2000 1 (16)

An alog LSI Circu its

Laboratory Work 3

Cad e n ce Lay ou t Too l


2/16



Refresh Your Knowledge

Refresh the basic principles of CMOS layout. Design

rules, concept of using layers, etc. You can find some

chapters about this in Johns&Martin but also in Tan,

Allen&Holberg, Rabaey, etc.

Get-to-know the Layout ToolSummary: We design some building blocks using the

layout editor. For this, we need to understand the con-

cepts of the tool and the process. We run design rule

checks (DRC) to check for desing errors. The netlist is

extracted from the layout view and compared to the

one entered in the schematic view. For this we use the

layout vs. schematic tool (LVS). We find if we have

done a proper layout in terms of connectivity.

We highlight some important analog layout issues and

we use the extraction tool to investigate the parasitic

capacitances, etc.

Start the Tools

As previously, start cadence and use the same design

library as you have done throughout the labs.

Note, that there is a new cadence version (4.4.5) and

you may have to modify some of your startup scripts

and remove the calls to version 4.4.3.

First, we design a CMOS common-source amplifier.

From the first lab you should already have a schematic

view of the circuit. Modify the sizes of the transistors

in this view. The PMOS transistor should be 120 um /

1 um and the NMOS transistor 40 um / 1 um.

To simplify for the LVS tool - remove all variables in

your design.

Now, we start with the layout tool. In the library mana-

ger, click on your common source cell. Choose File >

New > Cellview and let the view name in the pop-upmenu be layout. Click OK and Cadence Virtuoso Lay-

out Tool starts.

Two windows open. One is the layer selection window

(LSW) and the other is the design entry window.


3/16



The Layer Selection Window

Obviously, from the LSW you select inwhich physical layer you want to add a

component to the design. For a metal

wire, we select for example the MET1 dg

layer for the metal layer closest to the sili-

con surface.

With the left mouse button you select the

layer, with the right button you toggle the

layer between selectable and non-selecta-

ble, and with the middle button you toggle

between visible and invisible.

Note, that we will use the dg and pn lay-

ers. The nt layer is reserved for the extrac-

ted view. In the LSW we have also two

ticks, one for Inst and one for Pin. These

can be toggled to make the instances and

pins (terminals) selectable or non-selecta-ble.

The buttons AV, NV, AS, and NS makes

All/No layers Visible/Selectable.

The Virtuoso Layout Editor

The layout editor is similar to the schematic editor interms of interface. However, there are several short-cut

keys that are different. Otherwise, there are multiple

ways (mouse, menu, quick access bar, etc.) to execute

a command. Some useful command are

Otherwise, the editor has a rather straight-forward

interface. (Dont forget the Escape button).

Short-cut OperationCtrl + r Redraw

Shift + f Displays all levels

Ctrl + f Displays only the top level

f Fits the design to the window

Right mouse

button

Hold down and draw a box to zoom

this area.

w Toggles between last few zoom areas

Shift + z Zoom out

g Toggles the gravity

F4 Toggles selectable object edges

k Ruler for distance measuring


4/16



The First Design

Now, we first add two transistors to our design. Use the

i button to add an instance. Choose from PRIMLIB

the layoutview of the cell nmos4.

Let the widths be 40 um and the length 1 um. Place the

transistor by simply clicking in the window. (Before

you place it you are also able to rotate it using the right

mouse button). Use f to see the whole design and use

Shift + f to see all layers. Identify the different layers

and use the LSW to find out how you can hide layers.

Use the k button to use the ruler to measure distan-

ces. With Shift + k you remove the rulers.Add a PMOS transistor in the same way, but with the

widths of 100 um instead. Place it at a safe distance,

say 10 um from the NMOS transistor.

By clicking any one of the objects, it is selected. With

the q button you are able to modify its properties.Using Shift and the left mouse button you can select

several objects.

The substrate or bulk connections are added by using

the o button. From the different contacts you can

choose the ND_C contact to be placed near the PMOS

transistor. The PD_C contact is to be placed near the

NMOS transistor. Modify their properties (q) and

choose for example as many number of columns

needed to make the contacts as wide as the respective

transistors. For the PMOS transistor use a contact that

is 111 columns wide and for the NMOS it could be 44

or 45. In the figure below a partial plot of the layout isshown. The NTUB layer (crossed light-brown layer)

N-diff contact

P-diff contact

PMOSNMOS

NTUB

D

G

S


5/16



indicates the N-doped area around the PMOS transis-

tor. We find that the N-diff contact is overlapping both

the N-doped area and the P-doped substrate. There-

fore, we have to increase the NTUB area so that it

covers the contact as well. This is done by first selec-

ting the NTUB dg layer in LSW with the left mouse

button. Use r to create a rectangle and cover the con-

tact. The NTUB must cover the diffusion of the con-tact with at least a 0.2 um margin. You can change the

size of the rectangle by clicking its edges. If you are

not able to do this, toggle this option with F4 and try

again. You can move a (selected) object by either pres-

sing m or keeping the left mouse button pressed.

Run the design rule checker (DRC) to check the design

for errors. Use Verify > DRC... Set the switches to be

no_FIMP no_erc. Click OK. Do you have any errors?

If you have, you find a blinking layer in your design

and messages displayed in the CIW. To get further

information on the errors, choose Verify > Markers >

Find... Tick Zoom to markers and apply. A pop-up

window explains the errors (sometimes very poor error

messages blame AMS). Fix the errors.

If you have not already noticed it, Virtuoso is a poly-

gon-based layout tool. It does not contain the electri-

cal information as the vector-based GDT (Mentor

Graphics) does. As soon as two objects of same layer

are overlapping or adjacent, they will also be interpre-

ted as connected by the netlist extractor.

Now, we connect the bulks to the sources of the trans-

istors. First click the MET1 dg layer in the LSW for

the lowest metal layer. Use p to add a path (wire).

By double-clicking the middle mouse button the pro-

perties of the path can be modified. First, the path is

only 0.4 um wide. To make the interconnect wire for

the PMOS as wide as the contact, we would need99.6 um (use the ruler k).

If you zoom to the middle of the substrate contact you

also find a small mark indicating the centrum of the

contact. Here you can start the path and let it end

somewhere on the PMOS contact.

For the NMOS transistor we would need a 39.4 um

wide wire to cover the contacts. One could use a rec-

tangle r instead to simplify some of the moves.


6/16



The outputs (drains) of the transistors can now be

interconnected. This is done in the same way with

metal 1. However, the width must not be to wide. Cen-

ter the transistors (and the contacts) and interconnect

with a wire as wide as the drain contact of the NMOS

transistor. This is all the interconnection for now.

We have to add pins (or terminals) to the design in

order to give nets names. Note that the pins do not

have the same function as terminals in GDT. Pins are

only used by the netlist extractor.

First, we will only add a pair of Metal-to-Poly contacts

on the gates of the transistors. Choose o and use the

P1_C contact. Let the number of columns be 4 and

rows 1. Put the contacts adjacent to the gate as shown

in the figure below. For the pins, choose Ctrl + p and

sym pin. Let the terminal names be AVDD AGND

Bias In Out. Tick Display Pin Name and by choo-

sing Display Pin Name Option... set the height of thetext to 0.2. Let the Pin Type be given by the layer you

are using for the specific terminal/pin. We have added

contacts on all of our nodes and therefore we can also

access them with the metal 1 layer and hence choose

MET1_T. Place the pins in the order specified by the

terminal names. Let the PMOS transistor be the bias

transistor. Be sure you put them on the metal.

Check the design for errors (Verify > DRC...). Use the

switch no_FIMP.

From this design we now want to extract the electrical

properties, hence the netlist. Use Verify > Extract...and OK. Check if you have any errors reported in the

CIW.

Go to the Library Manager and you will now for your

common source stage find a cell view called extracted

as well. Open it. Display all levels (f and Shift + f)


7/16



and you will find that the layers look slightly different.

The extractor uses layers with the extension nt (look in

the LSW). Zoom at the one of the edges of the transis-

tors and you will find that the extractor has identified a

transistor.It also identifies the terminal names, etc.

This extracted view can be compared to the schematicview. Actually, what we do is that we compare the two

netlists generated by the tools. Start the layout vs.

schematic tool. Verify > LVS... Make sure that the cor-

rect libraries, cells and views (schematic and extrac-

ted) are entered in the form. Untick all of the LVS

Options. Run. Eventually a pop-up window tells you

if the run has succeeded or failed. Either way you can

use the Monitor button in the LVS form, tick the cur-

rent process and choose Command > Show Run Log.

If the Run has failed, you may have an error like:

Global error: (common-source schematic) in library

first_test has been changed since it was last extracted.This is probably one of the most stupid errors in his-

tory of man, thanks to the cadence programmers.

However, it can be handled simply by once again

saving the specified cell view. Rerun the LVS after

that.If the Run has succeeded you will find a brief report in

the run log. It may however be insufficient and therfore

open the result file by clicking Output in the LVS

form. Now, you may find that the LVS reports that the

terminals in the respective views are not correspondingto eachother, since the names are differing. The most

important thing to check is if the number of instances,

nets, and devices is equal in both schematic and layout

view. Also check that no nets are unmatched.


8/16



To make the netlists match exactly, you have to change

the terminal names to be equal in both views. (It is

most often simpler to change in the schematic view,

then you do not have to rerun the extraction, etc.)

When you extract the netlist from the layout, you have

a number of switches to choose from. Using cap and

cap_all you will also extract the parasitic capacitances

from the layout. You can open the LVS and select to

generate the netlist for the extracted view containing

the parasitics. This netlist can with some modifica-

tions to the AMS process be used in the Spectre

simulator in Analog Artist.

Unfortunately, in this process, AMS does not support

any extraction of wire resistance, etc., only capacitan-

ces.

As you hopefully have noticed, the layout of the com-

mon-source stage is rather stupid since the transistors

are large. A wide transistor can be constructed byusing a number of smaller transistors in parallel. In the

AMS process this is supported more or less automati-

cally. Go back to the layout view and close all other

windows.

Click on the NMOS transistor and modify its proper-

ties (q). Choose Parameter. Change the MOS transis-

tor shape to interdigit (interdigitized). Let width be

40 u and the number of gates 4. Note that you can tick

Substrate contact and cadence adds the bulk connec-

tions automatically. Do the same for the PMOS. Let

the width be 100 u and the number of gates 10.

We are going to add dummy transistors at the edges of

the transistors for improved matching of the edge sub-

transistors. They should be 10 um / 1 um. This can be

done in two ways. One is to add four transistors with

these dimensions to the existing transistors. Then the

drains and sources need to be connected. The secondway is to change the size of the original transistors to

be 60 um and 6 gates for the NMOS and 120 um and

12 gates for the PMOS. AMS lets us choose to not

interconnect the gates, drains, and sources. It can be

done manually afterwards.

We choose to do it the second way, since then we have

automatically added the substrate contacts as well. Let

the drain and source of the dummies be shortconnected

with the supply (AGND for NMOS, AVDD for

PMOS). Let their gates be left unconnected.


9/16



Connect all the sources to the respective supply by

using the path command p. Only use one side of the

transistors. Double-click the middle mouse button and

a pop-up menu toggles. You can now specify the wire

width to be 0.6 um. Do the same for all drains on the

other side and interconnect them to become the output

of the common source stage. You will find that it is

more metal wire on either the supply or the outputnode. The best thing is to let less metal area be connec-

ted to the output since you reduce the parasitic capaci-

tance. If you want to modify a bend or similar on the

path, you have to point the center of the path. Then

you can move this, delete, or whatever.

Be sure that you place the wires on a correct distance

according to the design rules. (You can run the Verify

> DRC with the switches no_FIMP and no_erc to

check).

Place metal-to-poly contacts on the gates (only oneside). You may have to add a path of poly to bridge the

metal 1 supply/output wires. Interconnect the gates

with metal 1, 10 for the PMOS to become the Bias

input and 4 for the NMOS to become the signal input,

In.

Check for errors in your design.

An example of layout is shown in the figure on nextside, but the transistors can naturally also be rotated 90

degrees for a more rectangular layout.

Before you extract the design, you have to consider the

dummies. These have to be added to the schematic

view as well. Add two PMOS and two NMOS with the10 um width and 1 um length. Interconnect their drain,

source, and bulk with their respective supply.

Use a no connection pin on the gates, noConn from the

basic library. See the figure on the next side.

Note that you in the schematic entry do not have tospecify if the transistors are interdigitized, etc. This

will not effect the LVS, but it may effect the simula-

tions, since the capacitances associated with the trans-

istors are dependent on the layout style.

Extract and run the LVS as was presented previously.Check if you have any errors.

To keep the threshold voltage very stable for all sub-

transistors in the complete transistor, one could add

more substrate contacts and basically fence the com-


10/16



Input

Bias

NMOS

AGND

AVDD

Output

PMOS

dummies

dummies

substratecontacts

dummies


11/16



plete transistor in. This will make it possible to attach

the supplies from any direction, but it requires that we

move to a higher metal layer for the signal wires. It can

however be advantegous since the higher metal layers

have less resistance/square and less parasitic capaci-

tance to the substrate. However, it may have larger

fringing capacitance and also the vias from metal 1 to

2 are resistive and add parasitics. The vias are calledVIA_1 for metal 1 to 2 and VIA_2 for metal 2 to 3. All

vias may be stacked on eachother. To add this substrate

contact ring, we can either choose to place 4 contacts

and interconnect them with metal 1 paths, etc. But,

fortunately, once again AMS has made it simple for us.

In the library PRIMLIB you find the cells

NSUB_PATH and PSUB_PATH. They let you draw a

polygon which is transformed into a substrate contact

path. In the figure on the side, we show a layout

using contacts only (ND_C and PD_C).

We have now implemented a common-source consis-

ting of a PMOS and an NMOS. We have used a layout

technique (unit elements) to improve local matching of

the transistors. We have used substrate rings to guaran-

tee a stable threshold voltage and a guard of the trans-

istors. Now, we will match two transistors with

eachother, i.e., global matching.


12/16



Differential Pair

First, create a cellview in your design library. Let it becalled diff-pair (or similar) and first create the schema-

tic view. Add (i) two NMOS transistors of size

120 um / 1 um (nmos4 from PRIMLIB). Interconnect

their sources and call this node Common using an

input/output pin (p). Connect the bulks to AGND, thegates to Vpos and Vneg, and the drains to Ineg and

Ipos.

Create the symbol cellview as well. (Design > CreateCellview > From Cellview ...)

Create a layout view for the same cell. The first and

naive approach is to place two long transistors close

to eachother as we first did in the previous example.

Instead we are going to use unit elements. In this case

use 10 sub-transistors at each 12 um width. For the

complete differential pair we would need 20 sub-trans-

istors and a number of dummy transistors.

First, add a transistor (i) that is 264 um / 1 um and

interdigitized with 22 gates. Do not connect the gates,

source, and drain. Do not add the substrate contacts.

We can now apply a interdigitized structure to match

the two transistors. The outer transistors are the dum-

mies and ignore them for the moment.

Since the transistors have a common source connec-

tion it is simple to create the matched pair. Identify andintraconnect pairs of adjacent gates, see the figure on

the next side. There should be 10 pairs of gates (do not

use the dummies). Assume that you connect Vpos to a

pair, the transistor contact in-between these gates is the

Ineg output and the contacts outside are the common

source.

Every second pair of gates should then also be inter-

connected with eachother as well as the common node

and the current outputs.


13/16



A hint is to use the copy command (c). First select an

object and then copy. By double-clicking the middle

mouse button you get a pop-up menu where you can

fill in multiple copies. By clicking the right mouse but-

ton you can rotate the objects you are about to copy.

Another tip is to use the de-select commands, d and

Shift + d. This is useful when handling several

objects.

A third tip is to watch the specification on coordinates

at the top of the design window. If you select an object

and then move it, you will find the relative distance,

etc.

For the gates, add poly-to-metal contacts and intercon-

nect them with metal rather than poly. (This may

dependent on how large the distances are). Also add

metal 1 to 2 vias on top of the poly-to-metal contacts.

For the outputs (Ipos and Ineg) assign one side foreach node. (Right for Ineg in the example figure). Use

metal 1 and be prepared to add vias to change to metal

2.

For the common node access it from both sides. Note,

that it is rather narrow and you have to use two metallayers for either the output nodes or the common node.

For good matching do not cover the transistor gates

with metal Not even higher metal layers!

Continuously run the DRC to check your design.

Dummy

Vpos

Vpos

Vneg

Ineg

Ipos

Common

Common

Common

Common

Ineg


14/16



Add a substrate box around the transistors. Note that it

should be connected to the analog ground; add a sym-

bolic pin named AGND.

Interconnect all wires outside the substrate ring. Use

for example a wide metal 1 wire for the Common node

and metal 2 wires for the other nodes.

The width of the wires should be given by specifica-tions on parasitic resistance, capacitance, the size of

the currents floating through them, etc.

To illustrate the final result see the figure on the next

side. (Although the wires should perhaps be routed

somewhat differently when the differential pair is putin a context, e.g., amplifier, etc.)

Sensitive wires can also be guarded by encapsulating

them by ground wires.

Now, we have left the dummies unshorted. Connect

the gates and the drains to ground.

From the figure below we see that the transistors are

still more of a rectangular structure. To minimize the

area it is however preferred to (still depends on the

Ipos

In

eg

Via

Via

Via

Common

Vpos


15/16



context and the whole layout) make the transistor lay-

out as quadratic as possible.

Therefore, divide the transistors into two blocks and

do a common-centroid layout. This means that you

should interdigitize the transistors in two dimensions,

in both the x- and y-directions.

See Johns & Martin for more information.Note, that a common-centroid transistor pair is more

easily laid out if the number of sub-transistors is given

by a power of 2. You may therefore either divide the

transistors into 16 gates (each 7.5 um) or 8 gates (each

15 um).In the figure on the next page we show an example of a

common-centroid transistor pair. The width of each

sub-transistor is 15 um. (From the figure, try to

understand how it is understood that the transistors are

interdigitized in two dimensions).Finally, do a simple PMOS current mirror, where both

transistors are 90 um / 1 um. The mirror should be

guarded by substrate contacts. Create schematic andIneg

VnegVpos

Ipos

Common

AGND


16/16



symbol views. The circuit should be verified with

LVS.

In the next lab, we shall begin to interconnect the dif-

ferent blocks in a fully-differential operational trans-

conductor. Since it is differential, the requirements on

the matching of the transistors are high.

Common

Common

Vpos

Vneg

Ipos

Ineg AGND

Lab3 Cadence

Documents

Transcript of Lab3 Cadence