JVC Plasma troubleshooting manual

7/29/2019 JVC Plasma troubleshooting manual

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PDP Troubleshooting

PD-42WV74 PD-42WX84

GM-X50U GM-V42UGPD-42X776 PD-42V475/485

PD-42X795 PD-50X795


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The models that apply to this course are the following, PD-42WV74, PD-42WX84, GM-X50U, GM-V42UG, PD-42X776, PD-42V475/485, PD-42X795, PD-50X795.

Page 1 notes.


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Course Contents

Plasma Basics

Panel Trouble Shooting Without the CPU

Service Cautions

Power Supply And Y-Main Adjustment Info

HDMI/DVI Reset Info


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Page 3 notes.

The topics covered will be Plasma Basics (review), Panel Trouble Shooting Withoutthe CPU, Service Cautions, Trouble Shooting techniques, Power Supply and Y-Main

Adjustment Information, and HDMI/DVI reset Info.


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Plasma Basics: Pixel

Display electrodes are Horizontal and address electrodes are vertical

Voltage breakdown

Movement of electrons.

Ionization of the gas

Multiplication of electrons Plasma

Xe excitation.

UV radiation.

Phosphor excitation.

Visible light emission.


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Page 5 notes.

********Plasma: This is one of the four states of matter (The other three are solid, liquid and gas). Plasma

consists of a gas of positively charged and negatively charged particles with approximately equalconcentrations of both so that the total gas is approximately charged neutral. A plasma can be produced froma gas if enough energy is added to cause the electrically neutral atoms of the gas to split into positively and

negatively charged atoms and electrons.

One pixel; imagine a cube with phosphorus coating at the bottom and filled with Xenon gas. When we apply avoltage on the two electrodes (shown as 1) the gas ionizes. When the gas ionizes as in area 3, UV radiation

occurs. This action is similar to a CRT. If this radiation is forced to hit the phosphor (4), light emits. This is thebasic principle of one plasma cell. One red, one green, and one blue cell together forms one pixel or Plasmacell. The diagram shown illustrates light emission for a single color. Besides the green, the red and blue are

shown and they function likewise.Sequence of events:

When a voltage is applied, between the Scan and Sustain electrodes (identify) (electrode marked 1),

movement of electrons occurs (identify as area marked 3).

This causes multiplication of electrons by gas ionization: This state of gas is known as Plasma. This excitationproduces UV radiation. At this point, if we apply a voltage to the phosphor (Address electrode marked 5), it

attracts electrons causing Phosphor Excitation and therefore, Visible Light emission.

The electrodes we apply excitation voltage to are known as scan and sustain electrodes (1). To simplify, avoltage is applied to the scan and sustain electrodes (1). Then xenon gas excitation occurs. Once the

electrons are multiplied due to ionization, emission occurs. Now a voltage (5) is applied to the phosphor forattracting the electron and producing the light. This is how the light output occurs in a Plasma environment.

The brightness of the pixel is a function of timing the potentials on the scan, sustain and address electrodes.

Now that we have seen, how one cell emits light, let us see how we made a video display panel with this.


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Plasma Basic: Panel

Cells are arranged vertically to form

red, green, and blue stripes

Transparent electrodes are used to

apply voltage

Both sides are protected by glass

substrate


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Page 7 notes.

A plasma display unit is a panel that consists of many tiny cells filled with a neon xenon.

Gas as explained in the previous slide. Let us see how they are arranged to get a panel.

Same color cells are arranged in vertical row. When we look from the front, we can see stripes.

The ionization voltage is applied through the scan and sustain electrodes positioned horizontally overeach row of cells.

We already discussed that when voltage is applied between two electrodes inside a cell, ultravioletradiation occurs and now voltage corresponding to incoming video is applied to the corresponding

address line which is located perpendicular to the scan and sustain electrodes. This is calledmatrixing. This applied address voltage excites the phosphors lining in the cells and light is

produced.

Let us look how a voltage is applied to these cells.


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Plasma Basics: Electrodes

Transparent Scan and Sustain

electrodes on the front

Data electrodes on the back

Controlling the scan, and data, pulse

duration, we can control the light

output


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Page 9 notes.

This is yet another way of illustrating the arrangement. Vertical cells are shown as the vertical phosphor bars.

Horizontal electrodes are transparent electrodes and are across the screen under the front glass. They arevirtually transparent and do not affect light output.

When the scan and sustain voltage is applied, ionization occurs inside each cell, the address electrode isenergized to excite the phosphor. We all know about phosphor characteristics. Light output from phosphor

depends on two things, that is, the amount of electrons and the time of excitation.Depending on how long the phosphor is excited, the brightness changes.

Since we have a matrix of horizontal and vertical electrodes, each cell can be controlled independently.

How did this display become so attractive for video industry?One reason is the ability to produce large enough displays. Now they are up to 50 displays and larger are

possible.Another is the characteristic is the low atmosphere gas filled chamber.

There is no warm-up time.

There are no convergence or registration issues.High light output, good color saturation and high contrast ratio are other advantages.


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Plasma Basics: Overall

Pixels: Formed by two sheets of glass with

ribs

Electrodes: Three electrodes, one at the rear

and a pair at the front

Turn ON: Approximately 200 V appliedbetween address and Y (scan) electrodes

causes gas ionization and light emission

Sustain: Approximately 50 V is applied

between the Y (scan) and X (sustain)

electrode to hold the light emission

Turn OFF: Remove the sustain voltage and

reverse the address voltage.


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Page 11 notes.

Here is one more representation of the design of the plasma panel. It is a more practical and realistic view.

The plasma panel is composed of two sheets of glass with the bottom glass having series of ribs filled withcolor phosphors in a particular order.

The top glass with embedded electrodes seals upon that and helps form a pixel.

Inside the sealed pixel, is a mixture of rare gases- typically argon and neon, although sometimes xenon hasbeen used. Actually with this construction, a small electric capacitor has been created, with one electrode on

the rear (Address) and a pair on the front (Sustain and Scan). These 3 electrodes control the capacitorcharge, sustain and discharge functions intrinsic to the plasma imaging process.

The plasma imaging cycle can be broken into following steps. initially, the pixel is at its resting (Off ) state.while a voltage is applied to the addressing electrodes ( pixel ). When the applied voltage reaches a certain

level- say 200+ volts - the resistance in the pixel is overcome, and an electrical discharge is made across theelectrodes. Once this discharge occurs, the mixture of rare gases is ionized into a plasma state, which meansthe gas mixture can now conduct electricity, an intense burst of ultraviolet ( UV ) light is emitted. This burst of

UV energy stimulates the color phosphors, in turn makes them glow brightly. Once the pixel is switched On(Scan and Sustain), a much lower voltage sustains the UV emissions and keeps the phosphors glowing. This

sustain voltage is typically in the 50 volts range. Eventually, the pixel will need to be turned off to rest thephosphors. This is done by removing the sustain voltage first, then reversing the charge in the pixel through

the addressing electrodes to achieve precise and complete turn-off. At this point, the pixel is back to its restingstate.


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SF1 SF2 SF3 SF4 SF5 SF6 SF7 SF8Origi

nalIm

age

1

..

...

2

480

128T64T32T16T8T4T2T1T

1TV field (time)

scan

line

address

sustain

sub-field

Plasma Basics: The Image


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Page 13 notes.

Here we can see how each individual image is built.

Each image corresponds to 1 TV field and within thattime period there are 8 sub-fields of different duration in

order to obtain the correct brightness for each pixel.This works out to 479.52 address and 479.52 sustainsevery second with 200 volts being applied during the

address time period of the sub-field between the scanand address electrodes and 50 volts being applied

during the sustain time period of the sub field betweenthe sustain and scan electrodes. Keep in mind thatevery pixel needs to be addressed during each sub-

field.


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Y (Scan)Electrode

X (Sustain)

Electrode

Address Electrode



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Page 15 notes.

In this slide we can see that we have a XVGA or WXGA screen resolution panel. Lets say forexample that we want to light up only two pixels represented by the yellow circles.

Putting it simply, first the two pixels would be lit by the Address part of the 8 section TV Fieldprocess, this is represented by the orange arrows from the Y (Scan) Electrode and the red arrows

from the Address Electrodes (this will make the pixel glow).

In the Sustain part of the 8 section TV Field process the pixels that are now glowing are keptglowing by the Scan Electrode ( orange arrows) applying signal while the total panel X (Sustain)Main signal (white arrows) is sent out. During the Sustain period the entire panels X Electrode is

energized while only the applicable Y Electrodes are energized.

Remember that this entire process will happen about 8 times per tv field and about 480 times a

second.


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Y (Scan)Electrode

X (Sustain)Electrode

Address Electrode



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Page 17 notes.

This is the representation of a WVGA screen resolutionpanel. The same process applies but with only the

lower Address Buffer.

The exception to the WVGA = one row of AddressBuffers rule is the PD42X776, which is XVGA resolution

with only 1 row of address buffers.


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To Address (Logic)Buffers

To Y-Main(Scan)

To X-Main(Sustain)LVDS Input


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Page19 notes.

Here is the a typical pdp Logic Board. The major sections being the Front Processor and MemoryController sections along with the individual X, Y, and Address outputs. This is the board that processesthe video signal provided by any A/V input assemblies into the LVDS input connector along with the X,Y,and Address output signals that will illuminate individual pixels to the proper intensity on the pdp panel to

create each image 59.94 times a second.


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X-Main Data

X-Main (Sustain)Y-Main

(Scan)

Lower Y

Buffer

Upper Y

Buffer

VideoSMPS

SMPSVoltage

labelLogic

Main

Y-Main Data

AddressBuffer(E)

AddressBuffer(F)

AddressBuffer(G)

PowerOutputs

from SMPS

Address Buffer Data

Sustain(X)ElectrodesAddress

Electrodes

Scan(Y)Electrodes

Plasma Basics: Panel Overview


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Page 21 notes.

This is the typical layout of a pdp panel once the rearcover and any A/V input boards, mounting supports,speakers, etc are removed. It should be noted that

once you are familiar with the locations of these majorparts you will find that any other pdp panel will be

surprisingly similar in layout and function.

It should be noted that Address Buffers on differentpanels may be labeled with different letters.


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SMPS (Switching Mode Power Supply) :Supplies voltage and current to operate the complete assembly.

X-Main (Driver) Board : According to the timing provided from Logic board, switches the FETs andgenerates the driving waveform which is provided to X electrode of Panel.

Y-Main (Driver) Board : According to the timing provided from Logic board, switches the FETs andgenerates the driving waveform which is provided to Y electrode of Panel sequentially through ScanDriver IC of Scan Buffer.

Logic Main Board : Processes the image signal and generates Address, X, and Ydriving output signal.

Address Buffer Board(E,F) : Transfers the data and control signal to the Address electrodes of the PDP.

Y (Scan) Buffer(Upper,Lower) : Transfers the scan waveform to the Y electrode, which consistsof Upper Board and Lower Board assemblies.

Plasma Basics: Board Functions


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Page 23 notes.

These are the functions of the major circuit boards that operate the pdp panel.


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Service Precautions


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Page 25 notes.

The next several frames may have specifics that pertain to certain models but in general will be

applied to any pdp panel you may be servicing.


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The drive circuit operates at 350V. In-order to remove PWB

after power off, wait approximately 5 minutes for the capacitors to

discharge

On the connectors, one of the wires is a different color. This is

not always pin1. Refer to the pin ID on PWBA.

Service Precautions


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Page 27 notes.

The Power Factor Control on the Switch Mode PowerSupply has an operating voltage of 350 volts. When

powering off the unit and before removing anyconnectors, it is recommended that a five minute wait isused to allow the residual capacitor charges to drain off.

It is also important to know that not all connectorsuse the black wire to identify the connection as Pin1. ALWAYS look at the silk-screen printing on the

BOARD to identify pin 1 of any of the connectors inthis unit.


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Do not apply power with any of these connectors disconnected on a one by one basis.Operation with any of these disconnected individually could result in damage to the X

or Y Main PWBAs.

Service Precautions


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Page 29 notes.

Powering on the unit with the connectors identified heredisconnected can cause damage to the unit. While thisdamage may not occur immediately, it will after a shorttime. This caution should be observed at all times toavoid damage to the X-Main and Y-Main boards. The

damage can be caused by improper loading of thepanel and reverse voltages from the panel being

introduced to the boards.

It should be noted that if connectors providing power tothe X-main, Y-Main, and Address Buffer Boards are all

disconnected it is acceptable to apply power. Thisprocedure will be used later in the course to test the

power supply.


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Do not power on with Flexible cable (Panel X-

Drive) disconnected. This could cause Main

SMPS damage

When servicing the Receiver (Tuner) with cover open,

before applying power, disconnect the DVI modules

power connector.

Tuner

Service Precautions


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Page 31 notes.

Additionally, powering on the unit with the X-Main driveconnectors disconnected could cause damage to theVideo SMPS or the X-Main due to improper loading ofthe SMPS. When these connectors must be taken out,

remember that the flex cables themselves have locatingand squaring holes in them that hold them in place onthe X-Main board sockets. It is also possible to missthe hole, or insert incorrectly. If they are not inserted

correctly and secured, damage to the Video SMPS canoccur.

Shown in the green circle is the tuner/receiverdisassembly (refer to the service manual). The cautionhere is that you must be sure to disconnect the power

to the DVI (HDCP) module. NEVER remove the coverof the unit while it is plugged in. This will de-

authorize the DVI module and render it incapable of

passing High Definition Content Protectedinformation..


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This caution applies to the PD-42X475.

Service Precautions


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Page 33 notes.

This note of caution was taken from the service manual for the PD-42V475. Thereis no caution in the manuals for the PD-42X776S, PD-42X795S, or the PD-50X795which have DVI/HDMI connections either in the PDP section or in the external tunerbox so the caution should still apply, although a method to reset these modules may

exist. If the sensor cannot be located please disconnect the power connector from the

circuit board or module if the unit must be powered up with the rear cover removed(preferred method). Again do not remove the rear cover with the power connectedor connect the power if the above caution is not followed when working on the

PD-42V475. the DVI/HDMI will be disabled otherwise.


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When replacing Logic Main PWB, we must use

the old ROMs. These ROMs contain panel

adjustment information such as Gamma, Shading, etc.

When replacing Y-Main PWB, readjust the

potentiometers exactly as in the existing PWB.

These adjustments could affect picture quality.

Service Precautions


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Page 35 notes.

******************Very important.******************Logic main replacement and Y-Main replacement

precautions.

As stated in the slide, when replacing the Logic Mainboard, be sure to move the old EEPROMs from the

defective Logic Main board to the new board. Failure todo so may result in poor or no operation. These

EEPROMs are socketed devices and they can be easily

moved.

When replacing the Y-Main board, observe the physicalpositions of the adjustment pots on the old board and

adjust the new boards pots to the same physicalconfiguration. Leaving them unadjusted could cause

deterioration in picture performance.


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Always clean the FFC and connectors while

reassembling PWBs.

Service Precautions


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Page 37 notes.

******Because some of the signals used in digital transmission are low current and low voltage innature, any naturally occurring corrosion could affect electrical contacts. For this reason, when

servicing the product, clean the flat flexible cables and the contacts as much as possible. Do not use

abrasive materials. Gentle motion and the use of alcohol for cleaning should be sufficient.**********


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X-Main disassembly. Free the flexible connection

from the tabs before removing the flexible cable

X-Main reassembly: Confirm that the flexible

is seated and locked properly before applying

power.

Service Precautions


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Page 39 notes.

*****Do not jerk on the X-main connector duringremoval.***** It is locked with two tabs under the FPC.

While disassembling, first press the flexible wiring awayfrom you to free it from the tabs. Then gently remove

the FPC.

Conversely, while reassembling, make sure the tabsare locked in place and seated and the flex cable isproperly inserted before locking. Powering the unit

without these connectors could damage the units X-Main board or the SMPS.


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1. Remove the shield cover 2. Remove the bracket

4. Carefully raise the Video

process Assembly3. Remove the Speaker

connector

Panel troubleshooting without CPU.


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Page 41 notes.

In order to access the Y-main triggering points and the Logic Main PWBA, the JVC interface box mustbe removed. If this assembly is to be removed, remember that it is possible to return some of the

connectors to an incorrect location. To avoid problems, mark the connector bodies and their matchingconnectors with a swipe of a magic marker. That way, when you reassemble, you need only to match

up the marks. Besides the connectors, there is one ground wire that is attached to the Logic Mainboard. Remove this black wire by taking out the retaining screw, but always remember to re-

attach it on reassembly. Left un-attached, it may come in contact with voltages and damageother parts.

In the case of the PD-42WV74 and the PD-42WX84 the JVC boards are held in place by four smallscrews. Two of these screws also hold the top shield.

Remove the bracket as in step two. This bracket is held in place with small machine-type screws.These screws are fragile and if over-torqued, the heads will snap off and you will have to remove theremains and re-tap the hole. Do not over-tighten these screws when re-assembling.

Remove the connector from the audio board that leads to the units speakers at the bottom, and the twocables that go to the side speakers..

Carefully lift the JVC unit up and use the test point on the logic main for triggering the scope.

Please note that depending on the model you are working on the disassembly instructions will bedifferent, please consult the appropriate service manual for the instructions.

Logic Main Dip


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Logic Main Dip

SwitchesWhen operating with LVDS signal

connected, set the Logic-Main-PWB

DIP Switches are set to External mode (

2 and 4 are set to ON)

1 2 3 4

ON SD

In test mode (without LVDS signal, change the

DIP switch settings to Internal mode (3 ON, allother are off)

Refer to Panel troubleshooting


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Page 43 notes.

In all units, there are some boards that belong to JVCand some that belong to the original equipment

manufacturer. Shown here are the positions for the DIP

switches in both normal (external) and test (internal)operations.

The internal mode is used when the two JVC boardsare not in the assembly and connected.

Unless you are troubleshooting without the A/V Input

PWBAs (JVC boards), do not leave the switch inInternal mode. When using the internal mode, it is notpossible to use signal input. However, the plasma

display will light up to a grayish or white screen. This isan aid to determining panel defects.

When testing is completed, be sure to return the DIP

switches to their normal positions, that is with switch 2and 4 in the ON position

The PD-50X795 and GM-X50U do not have an internalmode and this function will not be available.

P l bl h i i h CPU


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On the Logic Main PWB, set DIP switches as follows

S1:-OFF, S2:-OFF, S3:-ON, S4:-OFF

This is Internal Sync mode


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Page 45 notes.

Here is the general location of the dip switches on theLogic Main Board. Some Logic Main Boards will havethe switches located in a slightly different location onthe Logic Main Board depending on the model and

board versions, others will have jumpers. For the unitswith the dip switches the settings for internal/external

sync mode are the same for all models.

The GM-X50U and PD-50X795 will not look like thisand will not have any switches or jumpers.

P l t bl h ti ith t CPU


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Internal SyncSettings

Normal Settings



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Page 47 notes.

This logic PWBA may be found in the PD-42WX84 models. It has jumpers instead of dip switches.The picture here shows the correct settings for internal sync mode and the settings for normal

(video input) mode. Remember to place the jumpers back to the normal/external/video sync modeonce the repair is completed and before the unit is re-assembled.

Panel troubleshooting without CPU


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From the CPU PWB, disconnect the power control wire connectors

CN00Q and CN00E

Pin 1 is the Orange Colored wire

Pin numbers

1. STB5V (orange)

2. GND

3. SW 5V4. GND

5. Therm Det

6. ACDET

7. PWR ON

8. Panel PWR


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Page 49 notes.

With the use of the internal sync mode, we will have toconfigure some connections to be able to power the

display unit for troubleshooting. The pin functions arecalled out at the right of the picture. To set up for the

Internal Sync mode, we will concern ourselves with pins3, 7 and 8. No video input will be required when testing

the panel with this method.

This method should be used with PD-42WV74, PD-42WX84, and GM-V42UG models.



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Short Pin 3 and Pin 8 so that the switched 5V can turn on the panel.


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Page 51 notes.

This is CN00Q with pins 3 and 8 shorted. A short piece of hook-up wire is used. Do this carefullyso as not to damage the connector. This will satisfy the connection needed to combine the

Switched 5 volts with Panel Power.



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Connect a hook up wire from the main power on pin. Grounding this

pin will turn on the power


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Page 53 notes.

A hookup wire is added to connector CN00Q Pin 7. Do not connect it anywhere at this time. Thiswire is used in a later step.



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Apply power to the AC input



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Page 55 notes.

Once the previous steps have been performed, the unitwill be able to operate independently of the umbilical

cable from the tuner box.

Notice in this and previous pictures that the JVC boardsare still in place. This is an option if you wish to

troubleshoot without removing this assembly. ACpower can be applied here, and if the JVC boards have

been completely removed, AC power can be directlyapplied to the panels SMPS with a simple two pinconnector attached to a properly polarized AC cord.

This is the step where AC power is supplied to thepanel.



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Attach the hook-up wire to a ground point to turn on the powerWhen power turns on, the SW5 will turn on the panel

Make all measurements, adjustments, etc.

Before closing, set the DIP switches to their normal positions

Pin numbers

1. STB5V

2. GND

3. SW 5V

4. GND5. Therm Det

6. ACDET

7. PWR ON

8. Panel PWR


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Page 57 notes.

Once AC power has been applied, the wire attached to

Pin 7 of CN00Q can be attached to a metal chassisground point. When the power turns on, the jumperedSwitched 5 volts to Panel Power will turn on the panel.

At this step, whatever measurements and adjustmentsto the panel can be accomplished.

When all testing has been completed, and before re-attaching the JVC boards, remember to return the DIP

switches to: 1 and 3 OFF, 2 and 4 ON. The unit will notpass signal if left in the INTERNAL SYNC mode.



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For models with the newer style (JVC) Power Supply, the cable from CN9001 of the Main RegulatorPWBA ASSY will be followed and removed at the opposite end, then 1 and 8 will jumped. AC will then

be applied.

New style PS withlarge aluminum heatsink plate.

Pin numbers

1. STB5V

2. GND

3. AC_CLOCK

4. GND

5. TEMP_DET

6. AC_DET

7. POWER

8. PANEL_POWER



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Page 59 notes.

This is the method in which to operate the panel ininternal sync mode with the PD-42V475/485, PD-X795,and PD-X776. This particular picture is of the PD-V475which has an internal tuner. The PD-42X776 will lookthe same while the PD-50X795 will be similar to the

PD-42WV74 and PD42-WX84 (as seen on page 19) butwill use the same internal mode power up procedure as

seen here.



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This assy must be loosened or removed in order to access the dip switches on the LogicMain Board, please consult the service manual for disassembly instructions.

Take care not to damage any FFCs while disassembling this section or accessingthe Logic Main Board.

Photo of PD-42V475. The

PD-42X776 will

be similar.


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Page 61 notes.

The models that have this A/V Input (JVC Boards) set up have a fewFFCs and wire assemblies that run across and underneath this assy.Care should be taken when accessing the Logic Main Board or when

removing this assy.

PDP Trouble Shooting Basic Flow Chart


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PDP Trouble Shooting Basic Flow Chart

Verify Proper Operation of Y-Main and X-Main

PWBAs

Verify Proper Power Supply Operation

Identify if problem is horizontal or vertical in

nature

Exchange Address or Y Buffer PWBAsdepending upon existing problem

Exchange PDP


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Page 63 notes.

This is a simplified flowchart of the pdp trouble shootingprocess. With respect to the chart not every step will be

required for all repairs once the technician is familiarwith the different types of problems Plasma sets

experience and will be able to skip over most of thechart and individual steps.


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Troubleshooting Summary

Logic Main, AddressBuffer, FFC, COF

Some vertical linesappear linked or are

missing

Address Open orShort

Scan Buffers, FPC

of X/Y-Main PWBA

Horizontal Lines

may be missing ormay be the same

Sustain Open or

Short

Y-Main, X-Main,Logic Main

Abnormal ImageAbnormal Display

Y-Main, X-Main,Logic Main, Cables

Operating Voltagesare good but there is

no picture

No Display

SMPSOperating Voltagesdont exist

No Voltage Output

RelatedBoard

DescriptionConditionName


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Page 65 notes.

Here is a table of the different conditions related to the boards that may be defective.Each row in the table will have a different trouble shooting technique and as can beseen from the table many of PWBAs can be attributed to nearly all of the symptoms.

No Voltage Output Troubleshooting


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AC InputCondition

NG

Check Line Filter Fuse, Replace As Required

Test at 2pinac inputconnector

OK

CheckSMPSFuses

NG

Replace SMPS and Check X/Y-Main in advance

OK

Continue


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Page 67 notes.

Here we can see that in the event that the techniciansuspects that the power supply is non operational thefirst step is to check for 120VAC at the 120VAC input

connector on the Main SMPS.If it is absent the fuse on the ac filter board should be

checked and replaced if necessary.

Once 120VAC has been established at the connectoron the Main SMPS board the fuses on the Main SMPSboard should be checked. Depending on the required

procedure the individually fuses may need to bereplaced and the operation of the Main SMPS checked.In most cases the Main SMPS will need to be replaced.

The Main SMPS should also be inspected for parts withphysically damaged parts and burn marks on the board

and heat sinks.



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Verify 120VAC InputAt SMPS AC InputConnector Typically

Found In This Location.


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Page 69 notes.

Here is the general location for the 120VAC input connector. Thisconnector is a two pin Molex type connector often times found in JVC

televisions. If a power cord can be found from an old TV it can be used topower the plasma panel with the A/V Input PWBAs completely removedand out of the way. A polarized power cord with an inline fuse should be

used.



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Check the Line FilterPWBA Fuse


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72

Page 71 notes.

This is the location of the fuse on the Main Filter PWBA. It is similaron all JVC models and is always mounted along with any A/V Input

(JVC) PWBAs.

No Voltage Output TroubleshootingContinue


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73


Check SMPSOutput

Voltages

Disconnect AC power. Nowremove X-Main, Y-Main, and

Address Buffer powerconnectors. Re-apply ACpower and recheck SMPS

Output Voltages.

NG

OK

NG

Continue to No Display Troubleshooting

Replace SMPS

OK

Continue to NoDisplay

Troubleshooting


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74

Page 73 notes.

Once it has been established that the Main SMPS doesnot have any open fuses and is not causing any fuses

to open the technician will be able to check the

individual output voltages of the Main SMPS PWBA. Ifthey are all OK the technician can go to the No DisplayTrouble Shooting section. If the output voltages are notgood the cable assy that leads to X-main, Y-main, and

Address PWBAs can be disconnected to check if any ofthese PWBAs are loading the Main SMPS PWBA.

Note: These connectors must be all bedisconnected in the power off mode otherwise

damage may occur to the pdp, X-Main, or Y-MainPWBAs. If the voltages check good the tech can

proceed to the No Display Trouble Shooting section.

If the voltages do not check good the Main SMPS must

be replaced. Adjustment is mandatory in order to avoidPWBA damage and premature pdp failure.

Power Supply Trouble Shooting


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pp y g

Verify SMPS Output Voltages

Typically Found In

These Locations

Voltage SpecificationLabel On PDP

Typical Adjustment Section From Service Manuals

If these check goodplease proceed to X-

Main and Y-MainTrouble Shooting


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76

Page 75 notes.

Here are the locations of nearly all of the voltages that

should be checked. Again this is very typical of all pdpassemblies. There are also voltage outputs like 5VDC

and 15VDC which do have adjustments and test points.These can be easily be found on the pwba itself and

are usually not found in the adjustment sections of theservice manuals.

It should be noted that each individual panel will havespecific adjustment needs which will be found on a

Voltage Specification Label on the pdp itself.



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If the SMPS outputvoltage is not correct

please check thefuses on the SMPS.

PD-42V475 Power Supply FuseLocation

Please locate and check the fuses on the

particular PS you are working on.

If fuses are NGplease replace the

SMPS board.


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Page 77 notes.

Here are the locations of the fuses on the Main SMPSof the PD-42V475. This board will normally have a flat

aluminum plate on top of the heat sinks that will need tobe removed to check fuses and possibly make anyadjustments.

The fuse locations may be in different locations fordifferent models.

It should be noted that the Main SMPS PWBAs that arefound in the PD-42V475, PD-42X776, and PD-42X795

are component level repair items. Fuses, at theminimum should be replaced when trouble shooting

these items.



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If the fuses are goodand the output voltagesare no good disconnect

the X-Main, Y-Main,and Address Buffer

Output Connectors

Y-Main, X-Main, and Address Buffer OutputLocations For PD-42WX84

Please verify the proper connectors for the model youare repairing as they may be different. DO NOTAPPLY POWER UNLESS THESE OUTPUTS AREALL DISCONNECTED. OTHERWISE ADDITIONALDAMAGE MAY OCCUR.

Once the output cablesare disconnected re-apply power andrecheck outputvoltages.

If voltages are goodproceed to X and Y-

Main DisplayTroubleshooting. Ifvoltages are no goodplease replace SMPSand do all requiredPower Supplyadjustments.


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Page 79 notes.

Here are the general locations for the connectors thatsupply power to the Y-Main, X-Main, and Address

Buffer PWBAs. These must all be disconnected with the

power disconnected to test the output of the MainSMPS in an unloaded state.

In this picture both CN8005 and CN8006 provideAddress Buffer power. One is for the upper row andone is for the lower row because this particular pdp

panel is capable of XVGA/WXGA resolution. A WVGA

panel will have only one Address Buffer power outputsince only the bottom of the panel will have Address

Buffer PWBAs.

Again the exception to this is the PD-42X776 which isXVGA with only one row of address buffers.

No Display/Abnormal Display Trouble Shooting, Y-Main


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Y-Main

Check Y-MainFuses forproper DC

voltage

OpenReplace Y-Main

OK

CheckFETS for

shorts

Short

Replace Y-Main

OK

Y-Main normal Check X-Main


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Page 81 notes.

Now that the it has been confirmed that the Main SMPS PWBA is operating properly the technician can

begin to trouble shoot the Y-Main (Scan) PWBA.

The first step is to check the fuses located on the Y-Main PWBA. If there are any open fuse pleasereplace the Y-Main PWBA.

If the fuses are good, the FETS should be checked. There are numerous FETs on each Y-Main PWBAall of which can be located by the labels printed on the boards themselves. None should show a short

when checked with a DVM. If any show a short the entire board should be replaced.

It should be mentioned that there are also many diodes on each Y-Main board which look very muchlike the FETs. These are also labeled on the circuit board and will show a short when checked.

A defection Y-Main may have random irregular spots through out the picture.

A defective Y-Buffer PWBA may damage the Y-Main PWBA.



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83

Please checkthat all fuses onthe Y-Main boardare good.

PD-42V475 Y-Main fuse locations. Pleaseverify the Y-Main fuse locations for the PDP youare working, they may be different.

Y-Main Fuses

If any fuses havefailed pleasereplace theboard.


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Page 83 notes.

This is the general location of the fuses on the Y-MainPWBA. Different plasma models have different Y-MainPWBAs so it should be determined where the fuses are

on the board the tech is currently inspecting.

If any fuses are found to be open please replace theboard.



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Check for anyshorted FETson the Y-MainPWBAs.

Y-Main FETs

Y-Main FET location for PD-42V475. Pleaseverify the Y-Main FET locations for the PDP youare working, they may be different.

Inspecttransistors/FETs forphysical damage. Ifany are damagedreplace the board.

If anyFETs/Transistorsare shorted replacethe board.


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86

Page 85 notes.

Here are the general locations of the FETs on a Y-Main

PWBA. Again different plasma models will have adifferent configuration so the location of the FETs willhave to be determined on a case by case basis.

These should all be checked for shorts and physicaldamaged. If any are shorted or damaged the board will

require replacement.

Keep in mind that many of the diodes look like FETs.Please determine which are which by reading the labels

on the PWBA.

Y-Main Measurement


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87

OUT4

GND

(Base Chassis)

Probe

(Port 2)DC Voltage Range : 50~100V SettingDC Voltage Range : 50~100V SettingDC Voltage Range : 50~100V SettingDC Voltage Range : 50~100V Setting

P 87 t


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88

Page 87 notes.

In order to measure the Y-main output, connect thescope as shown in the picture.

The signal is approximately 400V p-p. In order to avoiddamage to your test equipment, choose correct settingson the scope before connecting to the unit. To insure avalid ground, scope ground should be attached to the

metal portion of the chassis.

The wave form might not trigger. Use the triggerlocation and setup shown in the next slide.

Y-Main Measurement Trigger


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V_TOGG GND1

Probe(Port 1)

GND

DC Voltage Range : 5V under SettingDC Voltage Range : 5V under SettingDC Voltage Range : 5V under SettingDC Voltage Range : 5V under Setting

Trigger point is adjusted to Riging time

Logic Main

Page 89 notes


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90

Page 89 notes.

The trigger test point is on the logic main PWB.V_TOGG is the designation for the trigger pin. Use

scope ground as indicated. Obviously, to get to this testpoint on the Logic Main board, the JVC portion of thedisplay unit must be removed or carefully relocated.

Y-Main Waveform and blockVset

VsVsc_h

11


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91

Ypp

YDr

1

2

Panel

Ysc_l

YDCL1 2

RAMP

YDCH

12

Ypn

GND

Ysc_h

Vs

YgYer

Yset

bead

Yr

YDf

1

2

Ysc

GND bead

Vsc

R5124

1k

R5117R5118

Yf

2

Yfr

GND

RAMP

Ys

1

2

RAMP

To Panel

- 70V

Vset

Vsch

VsThis is the general

shape of the waveformfrom the Y-Main output.

Note: The waveform will varydepending on model number orboard/pdp versions.

Page 91 notes.

This is a block diagram representative of the operation of the Y-Main board.


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92

Y-Main output is a complex wave form used to drive the PDP cells.

The signal flow in the block diagram is from right to left.

DC voltages are switched on and off at different timings to generate this wave form.

Each FET is switched to add certain voltages. For example YS FET switches and raises the waveform to YS.(Refer to the waveform).

The final output with different voltage levels at periodic times are then output to the plasma cells for turningthem on and off according to the inputted video.

An example trouble shooting tip: When measuring the wave form, if you find the highest spike (Vset) is absent.This means that either Vset voltage is missing or Vset switching is not occurring. If the power supply outputs

Vset to the Y-main, replace the Y-main.

The waveforms in the handout are taken by a digital scope. Obviously, the waveform will vary widely whenusing an analog scope. With careful interpretation of a good units waveform, you should be able to determine

if another is good or bad.

Note: The level equipment used to obtain this waveform may not be available in every shop.

Note: This procedure can be used as a quick check to verify that the Y-Main is operating properly if it has beendetermined that the Main SMPS supply voltages are all good.

No Display/Abnormal Display Trouble Shooting, X-Main


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X-Main

Check X-MainFuses forproper DC

voltage

OpenReplace X-Main

OK

CheckFETS for

shorts

Short

Replace X-Main

OK

X-Main normal Check Logic Main

Page 93 notes.


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Page 93 notes.

The procedure for the X-Main (Sustain) PWBA is nearly identical to the Y-Main PWBA.

The first step is to check the fuses located on the X-Main (Sustain) PWBA. Depending on the proceduresany open fuses may need to be replaced, otherwise board should be replaced.

If the fuses are good, the FETS should be checked. There are numerous FETs on each X-Main PWBA all ofwhich can be located by the labels printed on the boards themselves. None should show a short when

checked with a DVM. If any show a short the entire board should be replaced.

It should be mentioned that there are also many diodes on each X-Main board which look very much likethe FETs. These are also labeled on the circuit board and show a short when checked.

The symptoms of a defective X-Main may appear that the previous picture does not get erased. (lag?)



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95

Please check thatall fuses are goodon the X-MainPWBA.

PD-42V475 X-Main fuse locations. Pleaseverify the X-Main fuse locations for the PDP youare working, they may be different.

X-Main Fuses

If any fuses areopen please

replace the X-Mainboard.

Page 95 notes.


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96

g

This is the general location of the fuses on the X-MainPWBA. Different plasma models have different X-MainPWBAs so it should be determined where the fuses are

on the board the tech is currently inspecting.

If any fuses are found to be open please replace theboard.


Inspect


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97

X-Main FETs

X-Main FET location for PD-42V475. Pleaseverify the X-Main FET locations for the PDP youare working, they may be different.

Inspecttransistors/FETs forphysical damage. Ifany are damagedreplace the board.

Check for anyshorted FETson the X-MainPWBAs.

If anyFETs/Transistorsare shorted replacethe board.

Page 97 notes.


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98

Here are the general locations of the FETs on a X-MainPWBA. Again, different plasma models will have a

different configuration so the location of the FETs willhave to be determined a case by case basis.

These should all be checked for shorts and physicaldamaged. If any are shorted or damaged the board will

require replacement.

Keep in mind that many of the diodes look like FETs.Please determine which are which by reading the labels

on the PWBA.

X-Main Measurement


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99

This is the X-Mainoutput waveform.

Page 99 notes.


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100

This slide is a picture of the X-Main output waves-shape. It was taken with a 400Mhz Digital Scope. Do

not expect this result with an analog scope.

This check can be used to ensure that the X-Main isoperating properly after it has been determined that the

Main SMPS out voltages are all good.

X-Main Measurement


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101

The X-Main waveform can bechecked at any pin on any of

these three connectors.

Page 101 notes.


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102

The X-Main (Sustain) wave form may be checked at any of the pins on any one of the threeconnectors. All of these pins are in parallel due to the current requirement of the scan electrode of

the pdp panel.

Address, Buffer, and Logic PWBA TroubleshootingProcedure


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1. Identify nature of the problem.

a. Vertical

b. Horizontal

c. PDP

2. If vertical or horizontal, please replace appropriateaddress, Y buffer, or possibly the Logic Main pwba and

check if problem is corrected.

3. If problem is not corrected please replace the PDP.

Page 103 notes.

O it h b d t i d th t th M i SMPS X


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104

Once it has been determined that the Main SMPS, X-Main, and Y-Main are operating properly the techniciancan usually diagnose the problem by just looking at thepicture on the plasma set. With the exception of a no

picture problem the panel will usually have a horizontal

or vertical line or block in the picture at this point.

This leaves the diagnoses in many cases to swappingout a few pwbas to determine if it is a problem with an

individual board or with the panel itself.

Since the Logic Main PWBA communicates to theAddress Buffers via a 8bit bus a failure of the LogicMain or an associated FFC would cause multiple

vertical lines through that section of the pdp or a loss ofpicture all together in that section of the pdp. This

should hold true for any Y-Main communication also.


Y Buffer PWBAs


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105

AddressPWBAs Buffer and Address PWBAs from PD-42V475. Please

note that your pdp may differ as it may include upper addresspwbas as well.

Logic Main PWBA

Page 105 notes.


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106

This a picture of the locations of the Y Buffers, AddressBuffers, and the Logic Main in a WVGA panel. Note thesingle row of Address Buffers on the lower edge of the

panel.

The PD-42X776 will also look like this although it is aXVGA panel.


Upper Address PWBAs


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107

Y BufferPWBAs

Buffer and Address PWBAs from PD-42WX84. Please note that your pdp maydiffer as it may include upper address pwbasas well.

Lower Address PWBAs

Logic Main

Page 107 notes.


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108

This a picture of the locations of the Y Buffers, AddressBuffers, and the Logic Main in a XVGA/WXGA panel.

Note the upper and lower row of Address Buffers on thelower and upper edges of the panel.

No Display/Abnormal Display Trouble Shooting, Logic Main


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109

Logic MainDoes the LED Blink?

Logic Main is normal.

Replace PDP

Replace Logic Main

NG

OK

Blinks at aregular

interval and

there is nodisplay

Does not blinkwith no display

or blinks

abnormally withabnormaldisplay.

Blinks at aregular

interval and

the displayis abnormal.

Logic Main is normal.

OK

Note: This procedure is in reference to internal syncmode only.

Page 109 notes.


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110

This is a step that could be accomplished at nearly anytime in the trouble shooting process. From the

flowchart we can see that if the led on the Logic Main PWBA is blinking at regular interval the boardmain is good. If the led does not blink or blinks abnormally then the board is defective.

Of course since this circuit board produces all the data that is used to create the picture on the screenthe all of the FFCs should be checked to verify that they are connected and not broken. This board

should also be considered a board to swap in order to verify that a problem does not exist in the

original since this board can produce problems that may appear like defects in other pwbas or thepanel itself.

Since the Logic Main PWBA communicates to the Address Buffers via a 8bit bus a failure of the LogicMain or an associated FFC would cause multiple vertical lines through that section of the pdp or a loss

of picture all together in that section of the pdp.



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111

Locationof LogicPWBA

Page 111 notes.


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112

The Logic Main PWBA can be found in this location in nearly all of the plasma models.


This LED should blink at aregular interval when the power


113/202

113

g pis on, whether the panel is in

internal or external sync mode.

Note: This Logic PWBA is from the PD-42V475, the logicboard on the pdp you have may be different.

Page 113 notes.


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114

Here is the location of the LED. Since thisis only one example of a Logic Main pwbait may be located in a different location on

different models.

Y-Main Buffer 0pen (Some horizontal lines dont exist)Y-Main Buffer Short (Some horizontal lines appear to be linked)

Y-Main Buffer Open/Short


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115

Change theappropriatebuffer and

recheck status

OK

NG

Replace the PDP

Defect was caused by the buffer

Page 115 notes.


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116

In this picture we can see that there is a thin horizontal line missing in the picture.

The things we do know immediately with out even opening the cabinet is that the Main SMPS, X-Main, Y-Main, and anything that could possible generate a part of the picture that is vertical in nature

(Address Buffers) is good.

The first step would be to replace the Y Buffer that would drive this part of the screen to determine if

that is the defective part. If that was not the problem then the pdp would be replaced.

The Y-Buffers Y Electrode connection may be temporarily disconnected to check if thatparticular buffer is causing a problem.

1. With the AC disconnected remove the suspect connection.2. Power the unit on and check the picture for any change.

3. The unit should not be left on for no more than 5 seconds in this state. Damage may occur

to good Y Buffer PWBA otherwise.


Upper Y Buffer


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117

Upper Y Buffer

Lower Y Buffer

Y Electrode

FFC

Page 117 notes.


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118

Here is another picture of the location of the upper and lower Y Buffers.


If this buffer wereto fail it would


119/202

119

to fail it wouldcreate a thickhorizontal baracross the screen.

Note: This symptom may also be caused by a defective PDP.

A thin horizontal linemay also be presentwith a failure likethis.

Page 119 notes.


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120

Here we can get an idea of what type of symptom that a failed Y Buffer will produce. Itwill always be horizontal in nature and may either be a thick bar or just a thin line.


If the picture has ablack bar like this,


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121

this Y Buffer would

be defective, and

this pwba would bereplaced.

A thin horizontal linecould also bepresent with a failurelike this.

Note: This symptom may also be caused by a defective PDP.

Page 121 notes.


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122

This picture demonstrates how to determine which Y-Buffer to replace in the event that ahorizontal line is present in the picture. One only needs to determine if the problem is in

the upper or lower portion of the screen in order to know which Y Buffer to replace.There is always the possibility that the pdp is defective in a case like this.


Example of Y


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123

Example of Y-Main buffer orPDP failure.

Page 123 notes.


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124

Here is an example of what a real horizontal type failure looks like. If it was aY Buffer it would have been the upper Y Buffer. In this case though it wasdetermined to be the pdp after a replacement upper Y Buffer did not solve

the problem.



125/202

125

Page 125 notes.


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126

This is a larger sized picture from page 56. This is either a problem with the lower Y Buffer or the pdp.


Failed


127/202

127

Failedupper andlower Y-

MainBuffers ormost likelya failed X-

main.

Page 127 notes.


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128

It was explained in the report that was submitted for thispdp that both upper and lower Y Buffers had failed in

this Plasma TV creating this type picture. (Poor antennasignal?)

Most likely a failed X-Main.

Note: picture most likely looks like this due to a poorantenna signal.

Address Buffer 0pen (Some vertical lines dont exist)Address Buffer Short (Some vertical lines appear to be linked)

Identify the failure


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129

1 line or 1block

Replace the PDP

Half ofscreen

Yes

No

Replace the Logic

Main/Applicable AddressBuffer/FFC

NG

Done

OK

YesReplace Address Buffer Done

OK

NG

Page 129 notes.


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130

With a problem that is vertical in nature the tech mustdetermine if the line is considered 1 line, 1 block, or half

the screen. In most cases an Address Buffer will bechanged first to verify that the Address Buffer is not the

problem, otherwise the pdp will need to be changed.

Since the Logic Main PWBA communicates to theAddress Buffers via a 8bit bus a failure of the Logic

Main or an associated FFC would cause multiplevertical lines through that section of the pdp or a loss of

picture all together in that section of the pdp.


This type offailure maylook like athi k ti l


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131

Note: A failure of this nature usually requires the pdp to be replaced due to a chipon film/tape carrier package vertical driver failure.

thick verticalbar or a thinvertical line.

Pleasereplace theappropriateverticaladdresspwba and

check if theproblem hasbeen solved.

Note: WVGA Panel 852x480 or PD-42X776 (XVGA, 1024 x 768)

Address

buffer pwbas.


132/202

Address Buffer 0pen (Some vertical lines dont exist)Address Buffer Short (Some vertical lines appear to be linked)This type of

failure may

look like athick verticalbar or thinline that


133/202

133Note: A failure of this nature may require the pdp to be replaced due to a chip onfilm/tape carrier package vertical driver failure.

extends halfway through

the picture.Pleasereplace theappropriateverticaladdresspwba andcheck if theproblem hasbeen solved.

Note: XVGA/WXGA 1024x768 or 1365x768

In this casethis

addresspwbawould be

changed.

Page 133 notes.


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134

This slide is the same as the previous with the exception of the higherresolution panel. The Address Buffers are not only on the bottom but

also on the top. When a problem occurs on a panel like this thevertical line will be on only the upper or lower half of the screen.


These would belocated in thisl ti d th


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135

location under thealuminum bar. If oneof these fail the pdpmust be replaced.

Page 135 notes.


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136

Here are parts that are located under the aluminum barin the red circle above. These drive the Address

Electrodes and if they fail the pdp will needreplacement. When units with the COF package havefailure with the one of these a burn mark can usually befound on the COF IC in direct relationship of where the

vertical line or bar is in the picture.

The pictures here are for reference only. If one of thesepackages fail they cannot be replaced individually so

the entire pdp must be replaced.



137/202

137

Page 137 notes.


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138

Here is an example of either a lower Address Buffer or pdp failure on a XVA/WXGAscreen (except the PD-42X776).



139/202

139

Page 139 notes.


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140

Here is an example of either an upper Address Buffer or pdp failure on a XVGA/WXGAscreen (except the PD-42X776).



141/202

141

Page 141 notes.


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142

Here is an example of either an Address Buffer or pdp failure on a WVGA screen or the PD-42X776 (XVGA).



143/202

143

Page 143 notes.


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144

This is an example of a failure on a WVGA screen withmultiple thin vertical lines. In this case it could be

multiple Address Buffers but most likely the pdp itself.

PD-42X776 (XVGA) also.


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145

Miscellaneous PDP Failures

Page 145 notes.


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146

PDP Failure Causing Picture Distortion


147/202

147

Page 147 notes.


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148

This is an example of a pdp failure causing picturedistortion.

Note: No antenna signal causing fuzzy white picture.



149/202

149

Page 149 notes.


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150

This is an example of a pdp failure causing picturedistortion.

Note: No antenna signal causing fuzzy white picture.



151/202

151

Page 151 notes.


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152

Here is an example of a pdp failure that will look likesolarization or a possible defective bit in a 8 bit digitalvideo bus. With this type of particular problem it would

be a good idea to change the Logic Main PWBA inorder to rule out a failure there.

Possibly the A/V/Tuner section also (this course did not

cover).

Possible Logic Board Or PDP Failure


153/202

153

Page 153 notes.


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154

This is a failure of either the Logic Main or the pdp. The included report did not specify either way.

PDP Vertical Failure


155/202

155

Page 155 notes.


156/202

156

This particular failure was with the pdp. It could have been one ofthe lower Address Buffers as well. XVGA/WXGA screen (except

PD-42X776).



157/202

157

Page 157 notes.


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158

Another pdp failure on a WVGA or PD-42X776 (XVGA)screen. This could also be an Address Buffer failure.

Note: Poor antenna signal causing fuzzy black andwhite picture.



159/202

159

Page 159 notes.


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160

Another type of pdp vertical failure.



161/202

161

Page 161 notes.


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162

Another single vertical line failure.

PDP Complete Failure


163/202

163

Page 163 notes.


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164

This is a pdp that has completely failed. It has nopicture despite all the circuit boards being good.

Note: The image you see on the pdp screen is thereflection of the person taking the picture.

Board and PDP Replacement


165/202

165

Information

Page 165 notes.


166/202

166

Important board and pdp replacement information. This is in addition to any previous service precautions.

Power Supply Adjustment Information


167/202

167

Power Supply Adjustment Procedure for GM-V42UG, PD-42WV74, and PD-42WX84

Page 167 notes.


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168

If the Main SMPS or the pdp are replaced on the GM-V42UG, PD-42WV74, orthe PD-42WX84 these adjustments must be done. Damage can occur to thepdp if these adjustments are not completed. Once the technician is familiarwith the approximate positions of the test points and potentiometers these

adjustments will take no more than 5 minutes.



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169

Power Supply Adjustment Procedure for PD-42V475S, PD42X776, PD-42X795

Page 169 notes.


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170

These particular models have the newer style power supply which require a slightly differentadjustment routine. The adjustment instructions contain several cautions against touching the

heat sinks and disconnecting the Y-Main, X-Main, Address Buffers, and the Logic Main PWBAspower connections prior to adjustment.



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171

Power Supply Adjustment Procedure for PD-42V475S, PD42X776, PD-42X795

Page 171 notes.


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172

There is also a method that is needed to turn the power supply on since the Logic Main PWBA is notconnected. According to Fig 2 a 3.3 to 5VDC source needs to be connected in series with a 1k ohm

resistor between pins 12 and 9 in order to turn the supply on. The dc source can be accomplished byusing three 1.5V cells in series (it is a low current circuit).

PD-42V475 Main SMPS output connectors


173/202

173

Page 173 notes.


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174

These are the pin outs for the PD-42V475 Main SMPS connectors that are the primary concern formost trouble shooting. These will also apply to the PD-42X776 and PD-42X795 models.

PD-42V475 Main SMPS output connectors


175/202

175

Page 175 notes.


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These are the pin outs for the PD-42V475 Main SMPS connectors that arethe primary concern for most trouble shooting. These will also apply to the

PD-42X776 and PD-42X795 models. The PD-42X795 will also have aconnector for the F-Buffer since it is a XVGA resolution screen and will have

an upper row of Address Buffer PWBAs.



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Power Supply Adjustment Procedure for GM-X50U

Page 177 notes.


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Here are the adjustments that need to be performed done after the Main SMPS isreplaced in the GM-X50U. Upon closer inspection of the manual it was discovered

that there is also a Sub Main SMPS that needs to be adjusted as well when it isreplaced. This applies as well to the PD-50X795 and will be covered a little later.



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Power Supply Adjustment Procedure for PD-50X795

Page 179 notes.


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These are the adjustments for the PD-50X795. The adjustments themselves areidentical to the GM-X50U and include a few more details and warnings.



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Power Supply Adjustment Procedure for PD-50X795

Page 181 notes.


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This is the continuation of the previous slide.



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DC/DC board adjustment procedure for GM-X50U and PD-X50795

Page 183 notes.


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These are the adjustments for the Sub Main SMPS which are not included in the service manual forthe GM-X50U and PD-X50795. This picture shows the locations of the potentiometers and the

connectors where the checks and adjustments will be made.



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Page 185 notes.


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Here is the Voltage Identification Label from the pdp itself, notice that the label does notidentify most of the required voltages.



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Page 187 notes.

These are the instructions which explain where thevoltages should be checked


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voltages should be checked.

For these adjustments it is recommended that to usethe suggested grounds for the adjustments.



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Page 189 notes.


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This is the continuation.

Y-Main and Logic Main Board Replacement Information


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Note: This information applies to all plasma models.

Page 191 notes.

This TT was issued for the models seen above butpertains to all plasma models. Also see page 15.


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pe ta s to a p as a ode s so see page 5

If ROMs are defective from old Logic Main PWBA allapplicable adjustments will need to be performed.



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Page 193 notes.

This picture displays the location of the ROMs that need to be swapped from the old


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p p y ppboard to the new board when replacing the Logic Main PWBA. This particular board

is from a PD-42WX84 model. Also see page 15.



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Page 195 notes.

This picture displays the location of the ROMs thatneed to be swapped from the old board to the newboard when replacing the Logic Main PWBA. This


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boa d e ep ac g t e og c a sparticular board is from a PD-42V475 model. Also see

page 15.



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Page 197 notes.

As noted previously when replacing a Y-Main circuitboard the potentiometers on the new board should

adjusted to the same physical position of the


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adjusted to the same physical position of thepotentiometers on the old board. Also see page 15.

Resetting DVI/HMDI Modules

1. Separate modules, HDMI or DVI. See TT-04100701-T(R) on ISEE.

2. Early version of combined HDMI/DVI module. Place unit into SelfDiagnostic Mode and transmit 03-6C with service jig/remote.

3. Improved version of HDMI/DVI module. Place unit into Self DiagnosticMode and then turn the power off.


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Page 199 notes.

If the unit happens to be powered up and the proper

precautions have not been taken for the DVI/HMDImodule these are the methods in which to bring the

module back to proper operating condition.


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Most modules encountered will be the type thatnumbers 1 and 3 will remedy. The number 2 type was

very limited in production but may be encountered.

PD-42WV74 Board Compatibility


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Page 201 notes.

The numbers over the circuit boards in the picture correspond to the item numbers in the chartbelow. The JVC input filter, signal, and audio boards have been removed to show the panel

board locations.

The three types of displays are listed across the top of the replacement chart. QLE0023-001and 002 are the COF type. The 003 is TCP type. The part numbers and interchangeability

are listed here.


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As an example, item number 1, the SMPS board, replacement from older to newer versionsonly is allowed. Item number 2 has full interchangeability from old to new and visa versa. For

the items marked NG, there is no interchangeability.

These boards available on individual order are CORE units. If a board is replaced, the newboard will come with return instructions and paperwork, and a return label. Return the defective

unit promptly. This will avoid problems with your parts account and credit status. The sameapplies is you have the need to replace the plasma display panel.

This will also apply to the GM-V42UG.

JVC Plasma troubleshooting manual

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