Junctionless Nanowire Field Effect Transistors

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Transcript of Junctionless Nanowire Field Effect Transistors

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    Welcome to the world of

    JUNCTIONLESS NANOWIRE FETs!

    1

    Isabelle FERAIN

    Tyndall National Institute

    University College Cork

    SQWIRE

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    Dimensions scaling

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    Voltage scaling

    Dynamic power dissipation in present CMOS

    circuits at frequency, f, supply voltage, VDD and

    load capacitance Cload can be described by:

    Any reduction of power consumption thus requires

    to reduce supply voltage

    Vdd scaling is

    set by the threshold voltage of transistors

    dependent on the inverse sub-threshold slope

    (kT/q)

    limited by short-channel effects

    Enhanced coupling between gate and channel

    3

    cycle

    2

    ddloaddynamic fVCP

    10-5

    10-4

    10-3

    10-2

    10-1

    100

    101

    102

    103

    0 0.5 1 1.5

    Dra

    in c

    urr

    en

    t (

    A/

    m)

    Gate voltage (V)

    Gate length = 70nm

    W=25nm

    Vds=0.9V

    Vds=0.05V

    Courtesy:

    Prof. Gerard Ghibaudo (IMEP)

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    Enhanced Electrostatic Control

    Gate

    Source Drain

    Buried oxide

    Back gate (substrate)

    Source

    Drain

    Gate

    ID

    Buried oxide

    Tri-Gate with 800C 600Torr 5min H2Anneal

    Fins are 45x78nm, Nice corner rounding by H2 anneal

    20 nm

    Polysilicon Gate

    Silicon

    Fin

    Buried Oxide

    Gate

    Source Drain

    BOX

    Gat

    e

    Gat

    e 1 Gate

    2 Gates

    3 Gates

    Gate-all-Around

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    Does it look too good to be true?

    Improved Lg scalability

    Almost ideal sub-threshold slope (60mV/dec) at RT

    Low drain-to-source current (IOFF)

    Drive current ION

    crystal orientation dependence

    High nano-wire pitch density

    Source/Drain resistance Rsd SEG / Layout optimization needed

    Critical Dimensions

    Gate length

    Gate oxide thickness

    Junction Depth

    Critical Dimensions

    Nano-wire width

    Junction abruptness

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    DEVICE STRUCTURE

    Junctionless nanowire transistors

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    Device Structure (1/2)

    J.-P. Colinge et al., Nanowire transistors without junctions, Nature Nanotechnology, Vol. 5, No. 3, pp. 225-229, 2010.

    Hooray!! No need for source &

    drain engineering anymore!

    10-5

    10-4

    10-3

    10-2

    10-1

    100

    101

    102

    103

    0 0.5 1 1.5D

    rain

    cu

    rre

    nt

    (A

    /m

    )Gate voltage (V)

    Gate length = 20nm

    W=25nm

    Vds=0.9V

    Vds=0.05V

    DIBL

    10-5

    10-4

    10-3

    10-2

    10-1

    100

    101

    102

    103

    0 0.5 1 1.5D

    rain

    cu

    rre

    nt

    (A

    /m

    )Gate voltage (V)

    Gate length = 20nm

    W=25nm

    Vds=0.9V

    Vds=0.05V

    DIBL

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    BOX

    Source

    Drain

    Gate

    Silicon

    Nanowire

    Gate

    Oxide

    Device structure (2/2)

    The cross-section of the

    channel must be small enough

    so that the gate can deplete

    the heavily doped channel

    entirely (OFF state)

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    CONDUCTION MECHANISM

    Junctionless nanowire transistors

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    Conduction mechanism (1/4)

    Electrostatic pinch-off: The cross section is small enough for the channel region to be depleted

    (VD=50mV, Nd>5e18/cm3)

    Below VTH Slightly above VTH

    Higher VG Depletion is gone

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    Conduction mechanism (2/4)

    -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0

    10-16

    10-14

    10-12

    10-10

    10-8

    10-6

    10-4

    DIBL S/S

    VDS

    =1.0V

    Dra

    in C

    urr

    ent

    (A)

    Gate Voltage (V)

    5x5_Lgate

    =10nm, tox

    =2nm

    Junction-less : 48 mV 66.2 mV/dec

    Inversion-mode : 153 mV 83.8 mV/dec

    VDS

    =50mV

    11

    VD=50mV VD=200mV

    VD=400mV

    VD=600mV

    Channel pinch-off

    VG > VTH

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    a b c

    d e f

    Be

    low

    Th

    resh

    old

    Ab

    ove

    Th

    resh

    old

    Inversion

    Mode

    Accumulation

    ModeJunctionless

    BOX BOXBOX

    BOX BOX BOX

    Conduction mechanism (3/4)

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    n=4x1019 cm-3

    Ninv>1x1020 cm-3

    N+PN+

    Inversion

    Mode

    N+N+N+

    Junctionless

    ND=1x1019cm-3

    Conduction mechanism (4/4)

    Channel in Multigate FETs @ VG= VG =1V

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    MOBILITY

    Junctionless nanowire transistors

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    me=250 cm2/Vs

    me=70 cm2/Vs

    Electric field ~ 0MV/cm

    (flatband)

    me=50 cm2/Vs me=10-30 cm

    2/Vs

    N+PN+

    Inversion Mode

    N+N+N+ Junctionless

    ND=1x1019cm-3

    Electron Mobility (1/2)

    VG= VG =1V

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    Lg and EOT scaling increased Eeff in the channel decreases

    Without strain technology the channel mobility in IM/AM FETs would be = or lower

    than in heavily doped Si

    Electron Mobility (2/2)

    Thompson S.E. et al., A 90-nm logic technology featuring strained-silicon, IEEE Transactions on Electron Devices, vol.51, 11

    (2004) 1790-1797.

    Jacoboni, C. et al., A review of some charge transport properties of silicon, Solid State Electron. 20, issue 2(1977) 77-89.

    J.P.-Colinge et al., Reduced electric field in junctionless transistors, Applied Physics Letters 96 (2010) 073510.

    1e15 1e16 1e17 1e18 1e19 1e20

    JL

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    PROCESS INDUCED-VARIABILITY

    Junctionless nanowire transistors

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    A

    B

    C

    Process induced-Variability (1/3)

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    Process induced-Variability (2/3)

    * Comparing SOI and bulk FinFETs: Performance,

    manufacturing variability, and cost, in ElectroIQ

    -0.7

    -0.6-0.5

    -0.5

    -0.4

    -0.4

    -0.3

    -0.3

    -0.2

    -0.2

    -0.1

    -0.1

    -0.1

    0

    0

    0

    0.1

    0.1

    0.1

    0.2

    0.2

    0.2

    0.2

    0.3

    0.3

    0.3

    0.3

    0.4

    0.4

    0.4

    0.4

    0.5

    0.5

    0.5

    0.50.6

    0.6

    0.6

    0.7

    Silicon Width (nm)

    Sili

    co

    n th

    ickn

    ess(n

    m)

    THRESHOLD VOLTAGE (V) for ND

    =1e19, Tox=2nm

    10 15 20 25 30 35 405

    6

    7

    8

    9

    10

    11

    12

    13

    14

    15

    width

    height

    A. Kranti. Junctionless nanowire transistor (JNT):

    Properties and design guidelines.

    In: Proceedings of ESSDERC 2010, pp.357-360.

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    Process induced-Variability (3/3)

    Doping

    concentration [cm-3]

    Statistical number of

    doping atoms in the channel

    1e15 0.002

    1e18 2

    1e19 20

    Source

    Drain

    Gate

    Silicon

    Nanowire

    Gate

    Oxide

    TSi=10nm

    WSi=10nm

    Lg=20nm

    Junctionless

    Inversion mode

    Lg=10 nm; Tsi=Wsi=3nm Tox=1nm Nchannel= 1e20cm

    -3 (JNT) or 0 (IM) NSD=1e20cm

    -3

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    Conclusion

    Naturally CMOS-toolset compatible

    Switching properties:

    SS=80mV/dec and DIBL=40 mV/V for JNT with Lg=25nm, W=25nm, TSOI=10nm,

    Vd=0.9V (experimentally demonstrated by CEA-LETI within FP7-funded project

    SQWIRE)

    Scalability:

    SS for p-channel JNT (Lg=3nm) is 80 mV/dec

    Manufacturability:

    JNT suppress the difficulty of fabricating ultra-shallow junctions

    SOI thickness control is critical

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    Acknowledgements

    Colleagues:

    Prof. JP Colinge, N. Dehdashti Akhavan, P. Razavi, S. Das, R. Yu (Ultimate

    Silicon Devices Group);

    N. Petkov, M. Schmidt (Advanced Microscopy Facility Group);

    L. Ansari, G. Fagas, J. Greer (Electronics Theory Group)

    Prof. G. Ghibaudo (INPG)

    Tyndalls Central Fabrication Facility

    22

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    Annex 1

    At High Gate Bias:

    The saturation current-blocking

    region is in the drain,

    not in the channel region.

    23

    Gate

    Source Drain

    Depleted

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    Annex 2

    Lo

    g (

    I D)

    VGS

    VFB

    VTH

    Lo

    g (

    I D)

    VGS

    VFB

    VTH

    Lo

    g (

    I D)

    VGS

    VFB

    VTH

    Deple

    tion

    Deple

    tion

    Deple

    tion

    Inversion

    Accumulation

    Partial

    Depletion

    a b c

    Inversion

    Mode

    ON: Main Current in

    Surface Inversion

    Channels

    OFF: Surface

    Subthreshold Current

    Accumulation

    Mode

    ON: Small body

    current & Surface

    Accumulation Channels

    OFF: Body

    subthreshold current

    Junctionless

    Mode

    ON: Large body

    current

    OFF: Body

    subthreshold current