Thin EBL defined HSQ spacers for vertical nanowire transistors
“ High Electron Mobility InAs Nanowire Field-Effect Transistors ”
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“ “High Electron Mobility InAs Nanowire Field- Effect Transistors ” ” Shadi A. Dayeh, David P. R. Aplin, Xiaotian Zhou, Paul K. L. Yu,Edward T. Yu, and Deli Wang Small 3 (2): 326-332, 2007 Presented by Zachery Jacobson April 9, 2007
description
“ High Electron Mobility InAs Nanowire Field-Effect Transistors ”. Shadi A. Dayeh, David P. R. Aplin, Xiaotian Zhou, Paul K. L. Yu,Edward T. Yu, and Deli Wang Small 3 (2): 326-332, 2007. Presented by Zachery Jacobson April 9, 2007. Outline. InAs Nanowire Fabrication - PowerPoint PPT Presentation
Transcript of “ High Electron Mobility InAs Nanowire Field-Effect Transistors ”
““High Electron Mobility InAs Nanowire Field-Effect
Transistors””Shadi A. Dayeh, David P. R. Aplin, Xiaotian Zhou, Paul
K. L. Yu,Edward T. Yu, and Deli Wang
Small 3 (2): 326-332, 2007
Presented by Zachery JacobsonApril 9, 2007
OutlineOutline
InAs Nanowire FabricationInAs Nanowire Fabrication Fabrication without Au catalystsFabrication without Au catalysts
Back-gated device fabricationBack-gated device fabrication ResultsResults
Top-gated device fabricationTop-gated device fabrication ResultsResults
ConclusionsConclusions
InAs Nanowire FabricationInAs Nanowire FabricationInAs nanowires are fabricated InAs nanowires are fabricated using MOCVD, with AsH3 and using MOCVD, with AsH3 and TMIn precursorsTMIn precursors
Time = 15 minutesTime = 15 minutes Temperature = 350Temperature = 350°°CC V:III ratio = 25V:III ratio = 25 Au colloid diameter = 40 nmAu colloid diameter = 40 nm Nanowire diameter = 30-75 nmNanowire diameter = 30-75 nm Nanowire length = 20-30 umNanowire length = 20-30 um
Resulting nanowires are single-Resulting nanowires are single-crystal Wurzitecrystal Wurzite
Growth axis = [110]Growth axis = [110]
SEM
20 um
TEM
50 nm
HRTEM
5 nm
Au catalyst-less InAs Nanowire GrowthAu catalyst-less InAs Nanowire Growth
B. Mandl, et al, Nano Letters 6 (8): 1817-1821, 2006
Au forms deep level traps in Si, limiting Au forms deep level traps in Si, limiting the use of nanowires grown with Au the use of nanowires grown with Au catalysts in hybrid Nanowire/bulk Si catalysts in hybrid Nanowire/bulk Si systemssystemsUsing LP-MOCVD, InAs nanowires were Using LP-MOCVD, InAs nanowires were grown on SiOgrown on SiOx x (x(x≈1) ≈1) No tapering or narrowing of the No tapering or narrowing of the nanowires was foundnanowires was foundThe length of the nanowires is a function The length of the nanowires is a function of the growth temperature, and is fairly of the growth temperature, and is fairly shortshortE-beam lithography can also be used to E-beam lithography can also be used to pattern “islands” of pattern “islands” of SiOSiOxx, that define , that define where nanowires will growwhere nanowires will growSi and InP(111)B substrates were used, Si and InP(111)B substrates were used, although best results were found with although best results were found with InP(111)B substratesInP(111)B substrates
Back-gated Device FabricationBack-gated Device Fabrication
InAs nanowires were InAs nanowires were sonicated from a growth sonicated from a growth substrate in ethanol and substrate in ethanol and transferred to a 600 nm transferred to a 600 nm SiOSiO22/n+ Si substrate/n+ Si substrateE-beam lithography was used E-beam lithography was used to pattern 15 nm Ti/85 nm Al to pattern 15 nm Ti/85 nm Al contacts for the source and contacts for the source and draindrain
Back-Gate ResultsBack-Gate Results
uFE=2740 cm2V-1 s-1
Transconductance was Transconductance was found to be 2 uSfound to be 2 uSThis is found to be This is found to be comparable to a free comparable to a free electron gas on the electron gas on the nanowires surfacenanowires surface Due to surface states on Due to surface states on
SiOSiO22 substrate and S/D substrate and S/D gate coupling due to global gate coupling due to global back gateback gate
VDS = 0.5 V
Top-gated Device FabricationTop-gated Device Fabrication
Same steps as back-Same steps as back-gated device followedgated device followedGate was defined using Gate was defined using e-beam lithography e-beam lithography using 100 nm sputtered using 100 nm sputtered SiO2 and 100 nm of Au SiO2 and 100 nm of Au gate electrodegate electrodeSource drain separations Source drain separations varied from 0.5um to varied from 0.5um to 4um4um
Top-Gate ResultsTop-Gate ResultsAnalysis was comprehensiveAnalysis was comprehensiveContact resistance was Contact resistance was calculated to be 1-10 kcalculated to be 1-10 kΩΩ, and , and 1 k1 kΩΩ was used to show worst- was used to show worst-case mobilitycase mobility2-D device simulators were 2-D device simulators were used to calculate gate used to calculate gate capacitancecapacitance
ConclusionsConclusions
InAs nanowires can be easily fabricated using InAs nanowires can be easily fabricated using MOCVD technology with or without metal MOCVD technology with or without metal catalyst particlescatalyst particlesThis paper presents a detailed procedure for This paper presents a detailed procedure for collecting mobility values while accounting for collecting mobility values while accounting for contact and series resistance, as well as contact and series resistance, as well as parasitic capacitancesparasitic capacitancesInAs nanowires were found to have great InAs nanowires were found to have great potential as n-type NW FETspotential as n-type NW FETs
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