7118 | J. Mater. Chem. C, 2015, 3, 7118--7127 This journal is©The Royal Society of Chemistry 2015

Cite this: J.Mater. Chem. C, 2015,

3, 7118

Low operating voltage and low bias stress intop-contact SnCl2Pc/CuPc heterostructure-basedbilayer ambipolar organic field-effect transistors†

Sk. Md. Obaidullaa and P. K. Giri*ab

Herein, a symmetrical Ag top contact-bottom gate (TC-BG) bilayer ambipolar organic field-effect transistor

based on the heterojunction of vacuum-deposited small molecules, tin(IV) phthalocyanine dichloride

(SnCl2Pc) (n-channel) and copper phthalocyanine (CuPc) (p-channel), has been demonstrated. A hydroxyl-

free poly(methyl methacrylate) (PMMA) with aluminum oxide (Al2O3) bilayer dielectric exhibits low operating

voltage (B10 V) and low bias stress (relaxation time t B 105 s) for both n-channel and p-channel cases.

The optimized SnCl2Pc/CuPc heterostructure exhibits balanced carrier mobility and both types of charge

carriers, electrons and holes, are facilitated by the same low work function Ag contact, depending on the

bias conditions, from the TC-BG architecture. The Ag contact also exhibits Ohmic injection of charge

carriers with low contact resistance in the n-channel region under an optimal heterostructure configuration.

The contact resistance for electron and hole-injection is strongly dependent on the thickness of the SnCl2Pc

and CuPc layers, respectively. The bias stress stability is modeled using a stretched exponential fitting. Our

results demonstrate that the ambipolar device characteristics and performance can be controlled by

adjusting the thickness of the molecular layer, which is highly desirable. Such simple heterostructure

engineering with utilization of organic molecular semiconductors can truly enable the development of

promising low-cost and flexible organic electronics for extensive applications.

1. Introduction

Ambipolar organic field-effect transistors (OFETs) have attractedenormous attention due to their unique operation, which allowsboth electrons and holes to be injected and transported in thesame devices, i.e., devices can operate in unipolar mode as well asin an ambipolar mode.1–4 These devices find active applicationsin organic complementary logic circuits, double carrier deviceslike light emitting field-effect transistors for organic active matrixdisplays, organic photovoltaic cells (OPVs), sensors, radio fre-quency identification components, e-papers, and inverters.5–9

High-performance inverters are the building blocks of the inte-grated circuits (ICs). Complementary metal-oxide–semiconductor(CMOS) technology is desirable for the preparation of ICs becauseit provides a straightforward circuit design, good noise margins,low power consumption, and robust operation. Organic CMOStechnology requires the use of p- and n-type transistors on thesame substrate.10,11 In addition, both holes and electrons can

transport within the same device (depending upon the biasconditions) and the recombination of opposite charge carrierswithin the transistor channel can result in light emission, namelya light emitting field-effect transistor, which has a potential to beat heart of the next generation of light emitting devices.12–14 Forthese, it needs to inject efficient balanced chage carriers (bothtypes, electons and holes) in the channel of the device. To achievethis goal, several groups have followed different approaches:(i) ambipolar OTFTs featuring symmetric or asymmetric sourceand drain electrodes for single or double channel organic semi-conductors,15–17 (ii) bilayer heterojunction structures consist-ing of electron- and hole-transporting organic layers,18–20 and(iii) blending two organic semiconductors with different chargecarriers.21–23 They all have particular characteristics and advan-tages as well as challenges to overcome.

In a single semiconductor, the main difficulty to achieveambipolar transistor operation is the injection of holes andelectrons into a single semiconductor from the same electrode.This electrode needs to have a work function that allows theinjection of holes in the highest occupied molecular orbital(HOMO) of the semiconductor, and the injection of electrons inthe lowest unoccupied molecular orbital (LUMO). Consequently,this will result in an injection barrier of at least half of the bandgap energy for one of the carriers (either electrons or holes,

a Department of Physics, Indian Institute of Technology Guwahati,

Guwahati-781039, Indiab Centre for Nanotechnology, Indian Institute of Technology Guwahati,

Guwahati-781039, India. E-mail: giri@iitg.ernet.in

† Electronic supplementary information (ESI) available. See DOI: 10.1039/c5tc01130b

Received 21st April 2015,Accepted 8th June 2015

DOI: 10.1039/c5tc01130b

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as most of the standard semiconductors have a band gap ofB2–3 eV). To overcome the problem of injection due to thisbarrier, in double-carrier devices, such as light emitting diodesand photovoltaic cells, two dissimilar, i.e. high- and low-work-function metal electrodes are used to enable the injection orcollection of holes and electrons.15 Unfortunately, this approachmakes the circuit fabrication complex and potentially expensive.Alternatively, a single low-cost electrode material can be used incombination with two different semiconductors, where one hasits HOMO level and the other its LUMO level aligned with themetal work function. Recently, Long et al. reported a mixedcontact interlayer of transition-metal oxides that control theefficient charge injection in ambipolar diketopyrrolopyrrole-thieno[3,2-b]thiophene copolymer (DPPT-TT) organic transistorswith using low-cost molybdenum (Mo)-source/drain electrodes.24

To reduce the contact effect one can introduce a self-assembledmonolayer (SAM) to lessen the injection barrier, and it results inan efficient injection of electrons and holes.25,26 Another impor-tant challenge is the trapping of one or both types of carriersin the defects/impurities, especially electrons are likely to betrapped by impurities at certain chemical moieties at thesemiconductor–dielectric interfaces and/or semiconductor sur-faces. We have found that the particular choice of hydroxyl-freelow-cost PMMA buffer polymer dielectric layers (as compared tofluorinated polymer dielectric layers, CYTOP) and low workfunction Ag electrodes can exhibit superior performances interms of low gate-bias stress and efficient injection.27 Takahashiet al. reported rubrene single crystal ambipolar OFETS with Agpaste electrodes to inject charge carriers and PMMA buffer layersto terminate the interfacial electron traps.17 Most of the ambipolarcharacteristics reported in the literature are based on bottomcontact SiO2 gate dielectrics and heavily doped Si wafers servingas gate electrodes. Such a rigid substrate requirement limits theflexibility of the composed circuits. Further, SiO2 layers maycontain a high density of hydroxyl groups known as electrontraps, which significantly suppress the n-type device character-istics. Therefore, the majority of the OFETs have reported p-typetransistors with high work function Au-electrodes that serve ashole injection layers and these devices are highly gate-bias stresssensible (i.e., drain–source current IDS decays substantially underbiased conditions for a prolonged time). Low bias stress devicesare highly desirable for future commercial applications.

Among all organic semiconductors, vacuum-deposited smallmolecules exhibit certain advantages over polymeric thin films interms of morphology, as demonstrated in this study, a solutionprocessed field-effect transistor (FET) is of interest because of itspotential contributions to low-cost fabrication of circuits throughmanufacturing roll-to-roll processes using conventional coatingand printing techniques. Recently, Cheng et al. reported balancedcarrier mobilities in 2-(4-n-octylphenyl) benzo[d,d0]-thieno[3,2-b:4,5-b0]-dithiophene (OP-BTDT)-based fused-thiophene deriva-tive with small-molecule, fullerene (C60), bulk heterojunctionambipolar transistors.22 Further, due to the molecular weightdistribution (polydispersity), regio- and stereo-irregularities, andend-group contaminations of polymeric materials, the perfor-mance of polymer-based OTFTs could exhibit relatively large

batch-to-batch variations. The lack of ambipolar transport inbinary blends of polymers for most of the compositions is dueto the fact that controlling the thin film morphology is a crucialfactor for obtaining continuous paths for both types of chargecarriers. Further, a limited number of polymer blends are avail-able due to the lack of high performing solution processablen-type polymers. On the other hand, small molecule materials areeasier to synthesize and high chemical purity can be achievedusing techniques such as vacuum sublimation. Therefore, dueto less impurities, they can be considered as intrinsic semi-conductors and can greatly improve the reproducibility offabricated devices as compared to that of polymeric materials.Small molecules can be easily purified using various methods,such as chromatography, sublimation, and recrystallization,while polymers can only be purified by recrystallization.

Therefore, bilayer heterojunction structures appear to besome of the very promising approaches for device fabrication,as they are readily deposited on the same substrate withoutbreaking the vacuum. Unfortunately, the carrier mobility inthese devices rarely exceeds the order of 10�3 cm2 V�1 s�1

because of poor control over molecular packing. In general,organic-based large electronic circuits may need 41800 tran-sistors and as the number of transistors per circuit increases,there is an increasing need for circuits characterized by lowpower dissipation, high noise margin, and greater operationstability.6 So, the high operating voltage and environmentalstability of ambipolar OFETs are still major challenges for theircommercial applications.

To reduce the operating voltage, herein, we used anodizedAl2O3, modified with PMMA, as a buffer gate dielectric layerinstead of the commonly used SiO2 layer. The optimized SnCl2Pc/CuPc heterostructure ambipolar OFETs with operating voltagesdown to 10 V and carrier mobilities of 1.8 � 10�4 cm2 V�1 s�1

and 2.1 � 10�4 cm2 V�1 s�1 for holes and electrons, respectively,are demonstrated here. The heterojunction OFETs consisting ofp-type CuPc and n-type SnCl2Pc have been chosen for the followingreasons: (i) they possess almost identical molecular shapes, andvery similar crystal packing structures and grain sizes under thesame deposition conditions, so it may be convenient to produceheterojunctions with nearly perfect crystalline interface, (ii) thefield-effect mobility (mFE) of carriers in these two materials is verysimilar at a level of 10�1 cm2 V�1 s�1 in the unipolar case.28,29 So, itmay be easier to achieve the balanced ambipolar characteristics byengineering small molecules. Several groups reported that lowband gap organic semiconductors, especially small molecule-based semiconductors are promising candidates for ambipolarOFETs.18,30,31 Most studies reported on ambipolar OFETs focus onthe hole and electron field-effect mobilities (mh and me, respec-tively), while the issues of the bias stress (drain current (IDS)instability with a prolonged operation time) and contact resistance(RC) effects have been rarely addressed, except for in a few reports,especially for bilayer heterostructure ambipolar OFETs. As thegate-bias stress and RC effects can be critical factors to limit thepractical applications of ambipolar OFETs, it is essential toinvestigate the contact resistance as well as gate-bias stress effectsfor both holes and electrons in organic bilayer structures.19,32,33

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2. Result and discussions

In bilayer heterostructures, depending on the device configurationand the materials used, charge accumulation and transport ofelectrons and holes can occur in different layers. However, at leastone of the two accumulation zones are formed at the interface andtherefore charge transport depends on the quality of this inter-face. Consequently, an accurate control of the growth conditionsof the evaporated film is necessary. The top contact-bottom gate(TC-BG) ambipolar bilayer device structure with silver (Ag) assource/drain (S/D) electrodes and the chemical structures ofsmall band-gap molecules tin(IV) phthalocyanine (SnCl2Pc) andcopper phthalocyanine (CuPc) are shown in Fig. 1(a). In general,top contact OFETs exhibit the lowest contact resistance, at leasttwo orders of magnitude lower, because of the increased metal–semiconductor contact area in this configuration.34 The detailsof the fabrication procedure for the device are provided in theExperimental section. CuPc was deposited as the first activelayer on the top of the insulator PMMA/Al2O3 and SnCl2Pc wasdeposited as the second active layer on the top of CuPc layer.The bilayer dielectric PMMA/Al2O3 enables a low voltage opera-tion. PMMA as a polymer dielectric is chosen because no chemicalgroups (–OH) are present at its surface that may act as electrontraps, and shows a very low bias stress effect, low contactresistance and is of low cost compared to other hydroxyl-freeflouro polymers, like CYTOP.27,35 The same device structure isreported to show a low bias stress (time constant B 105 s) and alow operating voltage (10 V). Herein, we used Ag electrodes astop-contact source/drain (S/D) electrodes, instead of the usualgold electrodes, which facilitate the electron injection due totheir low work function. In addition, the top contact-bottomgate (TC-BG)-OFET behaves as an inverted-staggered transistorand is affected by the current crowding effect, in which thecontact resistance, Rc is lower than the channel sheet resistanceRch.36 A schematic energy level diagram of the SnCl2Pc andCuPc – heterostructures with a symmetric Ag-contact is shownin Fig. 1(b) (under zero bias condition). The lowest unoccupiedmolecular orbital (LUMO) level of SnCl2Pc is at 4.0 eV,37 whichhas a very small difference compared with the Fermi energylevel (EF) of silver (Ag) (work function FE 4.3 eV), and it results

in an Ohmic electron injection (i.e., the output drain–sourcecurrent initially increases and is finally saturated) into theLUMO level of the SnCl2Pc layer. It is known that a good Ohmiccontact can be achieved when the work function of metalclosely matches with the LUMO or HOMO energy level of thesemiconductor. On the other hand, the difference between theHOMO level of CuPc and the Fermi energy of Ag is quite large(E0.9 eV). When the gate bias is applied, band bending occursat the metal/semiconductor interface and reduces the energybarriers and allows tunneling of charge carriers from theelectrode to the semiconductor. Note that we did not find anyambipolar signature for CuPc/SnCl2Pc (top/bottom) bilayerheterostructures for the CuPc (60 nm)/SnCl2Pc (12 nm) device,though it may be possible to obtain an ambipolar behaviorfor thinner layer combinations. Therefore, the SnCl2Pc/CuPc(top/bottom) heterostructure pair is found to be an excellentchoice for obtaining ambipolar characteristics.

The performance of electronic devices depends cruciallyon the depletion width, film thickness, and in particular thespatial location of trap states, either at the organic/organic ororganic/dielectric interface. In addition, an energy land scapeat the organic/organic interface is complicated due to severalelectrostatic phenomena, such as charge transfer, dipole genera-tion and/or dipole orientation, and doping, which are dependenton features, such as molecular structures (orientations), crystal-linity, inter-diffusion, and domain sizes. Therefore, it is necessaryto track the evolution of device characteristics with the filmthickness.30,38

In order to investigate the crystalline quality of the SnCl2Pc/CuPc heterostructure, we carried out X-ray diffraction (XRD)analysis using Cu-Ka radiation (l = 1.54056 Å). The XRD patternof the SnCl2Pc thin film with a thickness of 60 nm grown on theCuPc bottom layer with different thicknesses (4, 12 and 16 nm)is shown in Fig. S1 (ESI†). The SnCl2Pc layer without the CuPclayer shows XRD peaks at 2y = 10.481 and 12.181 correspondingto the (010) and (100) crystalline planes, respectively, of SnCl2Pc.Upon the introduction of the CuPc bottom layer, the intensity ofthe XRD peaks related to SnCl2Pc decreases and a new peakappears at 2y = 6.841 for the 12 nm and 16 nm CuPc films. Thepeak at 2y = 6.841 results from the (200) lattice planes of CuPc,

Fig. 1 (a) Schematic of the top-contact (Ag) bottom-gate (Al) device configuration employed in this study, with chemical structures of the small moleculesSnCl2Pc and CuPc. (b) A schematic of the energy band diagram of SnCl2Pc/CuPc heterostructures with Ag electrodes without any external bias.

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where the inter-stacking distance is d E 12.9 Å. It implies that thetrace of the herring-bone pattern is parallel to the substrate.18

The presence of distinct peaks in the XRD pattern of the SnCl2Pcfilm implies the formation of the crystalline film and inter-molecular p–p stacking parallel to the substrate. This featureimplies that the crystalline quality of thin films is appropriate toexpect good transport of charge carriers in the OFET geometry.29

We used atomic force microscopy (AFM) to study the surfacefeatures of the as-deposited films that influence the ambipolarbehavior of the fabricated transistors, and to investigate whetherthe CuPc to SnCl2Pc thickness variation have any influence onthe phase-separated network. Fig. 2(a–d) show the AFM imagesin tapping mode of the SnCl2Pc thin film (60 nm) grown over theCuPc layer with different thicknesses (0, 4, 12 and 16 nm) at asubstrate temperature 60 1C. It is noticeable that the root-mean-square roughness (Rq) of the SnCl2Pc thin film becomes higherat a higher thickness of CuPc (Rq E 1.7 to 2.2 nm). The thicknessof the CuPc film is controlled by building up of separate singlelayers. At a very low thickness deposited at 60 1C, voids mayappear in the filmbecause all grains are not fully connected witheach other, and they provide the location upon which the secondlayer can grow. Thus, the SnCl2Pc/CuPc heterojunction interfaceis expected to be smooth with the ultra-thin CuPc layer, but itmay become little rougher at a higher CuPc thickness.

A typical unipolar OFET based on vacuum-depositedSnCl2Pc exhibited a carrier mobility of 0.01 cm2 V�1 s�1, asreported in the previous work.27 The bilayer heterostructureambipolar OFET device charateristics are shown in Fig. 3(a)–(f),and in Fig. 4(a)–(c) with optimal 60 nm thick SnCl2Pc and x nm(x = 4, 12, and 16 nm) thick CuPc bilayer heterostructures.

Fig. 3(a), (d) and 4(a) shows the output characteristics (IDS–VDS),Fig. 3(b, c) and (e, f) are the transfer characteristics in p-channeland n-channel regions for CuPc-thicknesses of 4 nm and 12 nm,respectively. The bilayer heterostructure OFETs show V-shape trans-fer characteristics typical of ambipolar transistors of n-channel andp-channel ambipolar OFETs under low vacuum (B10�3 mbar)and under dark conditions with electron and hole mobilitiesof 5 � 10�4 and 3 � 10�4 cm2 V�1 s�1 for the n-channel andp-channel, repectively. In the case of thick CuPc with the corre-sponding rough heterojunction interface, the hole-current domi-nates IDS and while the electron-dominant IDS is supressed. Thedevice parameters are summarized in Table 1, VTh,e, and VTh,h arethreshold voltages of the top n-channel and bottom p-channel,respectively. A noticeable hysteresis in the output characteristicsof the p-channel regime may be due to hole scattering and/ortrapping at the CuPc/PMMA interface (as the thin CuPc layer mayhave formed interconnected grains, not fully covered on thedielectric surface). As the gowth of heterostructures was sequen-tial and performed under vacuum conditions, the measurementof the surface roughness of only the CuPc layer was not possible.The mechanism of charge carrier transport in the present hetero-structure (SnCl2Pc/CuPc) transistor is schematically illustrated inFig. 5(a) and (b) for n-channel and p-channel cases, respectively.With VDS 4 0 and VGS 4 0, electron conduction takes place fromthe source to the drain mainly through the SnCl2Pc layer due tothe particular positions of the Fermi and LUMO levels, asexplained in Fig. 1(b). Similarly, under VDS o 0 and VGS o 0,the hole conduction takes place through the CuPc layer only. Inthis way, an ambipolar characteristic is obtained in the herero-structure device.

Note that at a higher thickness of CuPc, me is reducedmarginally (see Fig. 6(a)), which may be due to the enhancedelectron scattering and/or electron trapping owing to theincreased roughness of the heterojunction at the SnCl2Pc/CuPcinterface. It is evident that the ambipolar OFETs can work wellwith the CuPc layer as thin as 4 nm and gives almost balancedelectron and hole mobilities (B2 � 10�4 cm2 V�1 s�1), which isan interesting feature and it is crucial for applications incircuits and light emitting OFETs. The value of mh and me

is B10�4 cm2 V�1 s�1, which is comparable to the literaturereports on other CuPc based ambipolar devices.18,30 A numberof devices (4–7) were tested for obtaining the device parameters.Fig. S2 (ESI†) shows the distribution of mobilities for the repre-sentative devices with different CuPc thicknesses (4, 12 and16 nm) for p-channel (left panel) and n-channel (right panel)cases. The average m and its standard deviation for each case arementioned in the inset. Note that the commonly reported mobilityfor unipolar devices is comparatively higher (B10�2 cm2 V�1 s�1)than that of the ambipolar devices. It has been generally attri-buted to low conductivity of evaporated CuPc and SnCl2Pc,whuch exhibit disorder of dipole at the heterojunction interface.31

At low values of VGS, the bilayer heterojunction ambipolar tran-sistors exhibited a diode-like (super-linear) behavior, which isfrequently observed for typical ambipolar transistors due to thepresence of both charge carriers (electrons and holes) in the activechannel of the device. We attribute this behaviour to the highly

Fig. 2 Tapping-mode AFM images (1 mm � 1 mm) of a 60 nm-thickSnCl2Pc layer grown on the CuPc bottom layer with different thicknesses:(a) 0 nm, (b) 4 nm, (c) 12 nm, and (d) 16 nm. The measured RMS roughness(Rq) of the SnCl2Pc surface is indicated in each case.

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negative threshold voltage VTh,h for p-channel operation and/orthe positive threshold voltage for n-channel operation. Therelatively high threshold voltages imply electron and holetrapping at the interface between the p- and n-channel materi-als in the phase separated network (see Table 1).

Table 1 shows that the threshold voltages, VTh,e and VTh,h,shift oppositely towards negative and positive sides, respec-tively, when the roughness of the heterojunction is higher.A possible mechanism of the shift in VTh,e and VTh,h may be dueto charge transfer to some extent (electrons from the HOMO

level of CuPc to the LUMO level of SnCl2Pc) at the SnCl2Pc/CuPcinterface, which could be facilitated at the rough interface dueto an increased interfacial area.19 For a higher thickness of theCuPc layer, both the electron and the hole threshold voltagesshift oppositely to more negative and positive values, respec-tively. In the n-channel device, the threshold voltage showsa small shift of DVTh,e E 0.87 V when the CuPc thickness ischanged from 4 to 16 nm, and consequently the p-channelthreshold shows a larger shift of DVTh,h E 3.43 V to more positivevoltages (VTh,h down from�6.84 to�3.41 V). Thus, the shift of the

Fig. 3 (a) Typical output characteristics (IDS–VDS) and (b) and (c) transfer characteristics (IDS–VGS) (for p-channel and n-channel, respectively) of theheterostructure ambipolar OFET for a CuPc thickness of 4 nm. (d) Output characteristics (IDS–VDS) and (e) and (f) transfer characteristics (IDS–VGS) (forp-channel and n-channel, respectively) of the heterostructure ambipolar OFET for a CuPc thickness of 12 nm. Note that the thickness of the top SnCl2Pclayer was kept constant (60 nm) for both cases.

Fig. 4 (a) Typical output characteristics (IDS–VDS) and (b) and (c) transfer characteristics (IDS–VGS) (for p-channel and n-channel, respectively) of theheterostructure ambipolar OFET for a CuPc thickness of 16 nm, while the thickness of the top SnCl2Pc layer is 60 nm.

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threshold voltage in the n-channel is much smaller comparedto that observed in the p-channel device. This may occur due tothe larger contact area of Ag with the CuPc film with a highthickness. At a higher thickness of the CuPc layer, the diffusionof the noble metal Ag is high in the organic semiconductor. Thediffused Ag impurity can create deep trap centers in SnCl2Pc/CuPclayers, which may affect the long term stability of the device. Notethat most of the deep trap states are located directly under themetal contact layer. However, some trap states may extend to theunderneath of the semiconductor layer.36,39

To further investigate the degree of charge trapping, weextracted the density of traps for CuPc (4 nm), Ntr = CiDVTh/q,where, Ci is the capacitance per unit area, DVTh is the shift ofthe threshold voltage. The trap densities derived from thetrans-conductance curves are 6.31 � 1011 cm�2 and 9.69 �1010 cm�2 at |VDS| = �4 V in the p-channel and n-channel,respectively. It has been proposed that deep traps are usuallyresponsible for the shift of the threshold voltage and its densityis higher at the CuPc/PMMA interface than at the SnCl2Pc/CuPcinterface. The deep trap states may be generated at both metal/organic interfaces in the contact region due to the diffusion of

Ag atoms.39 To further confirm the modulated charge injection,we analyzed the contact resistance. Fig. 6b shows the channelwidth (W)-normalized contact resistance (Rc) as a function ofthe CuPc thickness, in the n-channel regime (for electrons) aswell as the p-channel regime (for holes) of the OFETs. In then-channel regime, the normalized contact resistance of 1.60 �109 O cm for SnCl2Pc (60 nm)/CuPc (4 nm) is the smallest whencompared with larger thickness CuPc layer cases. Here, Rc isextracted using the Y-function method (YFM) for individualSnCl2Pc/CuPc OFETs (channel width/channel length (W/L) of780 mm/30 mm) using the following equation,40

Rc ¼VDS

IDS� 1

Gm VGS � VThð Þ; (1)

where Gm = (W/L)m0Ci, is the trans conductance parameter. Thisis in contrast to the transfer line method (TLM) used toestimate the contact resistance of the amorphous silicon tran-sistors, where one can obtain only an average Rc from the setof different channel lengths of transistors. This leads to thescattering of data in the plot, as Rc varies from transistor totransistor. Again, this method cannot be used if the contactresistance is nonlinear (i.e. departs from Ohms law), as it isapplicable in the linear regime. The YFM offers a straight-forward way to obtain the Rc in a single transistor, and thereby itaccesses the evolution of charge injection induced by differentcombinations of heterostructures with the same channel length, L.In devices with different thickness combinations, the RcW(Rc,e) forelectron injection systematically increases from 1.6 � 109 O cm to115 � 109 O cm, while the RcW(Rc,h) for hole injection does notchange significantly. This is due to the importance of diffusion atthe contact. As the thickness of CuPc increases, diffusion is nolonger sufficient to drive the current through the bulk of thesemiconductorbecause for a given number of charges induced bythe gate voltage, a sizeable concentration gradient can only bemaintained over a finite distance and this results in the increase inthe contact resistance, Rc,e for electron conduction. Furthermore,the VGS dependence of the normalized Rc shown in Fig. 6(c and d)supports the above analysis. It is noticeable that the contactresistance Rc of holes is one order of magnitude higher than thatof electrons for the SnCl2Pc/CuPc heterostructure reflecting a finiteSchottky barrier at the Ag/CuPc interface. It is clear that Rc

decreases with the increase in the VGS for both hole and electroninjection, and it is due to the fact that a higher VGS induces moreaccumulated charges, which will increase the conductivity of thecontact region and follow the current crowding model.41

Table 1 TC/BG OFET (Ag-contact) electrical parameters for the SnCl2Pc/CuPc heterostructures with different CuPc thicknesses grown at a substratetemperature of 60 1C

SnCl2Pc-thicknessa

[nm]CuPc-thicknessb

[nm]

n-channel OFET p-channel OFET

me

[cm2 V�1 s�1] VTh,e [V]Rc,e[�109 O cm]

mh

[cm2 V�1 s�1] VTh,h [V]Rc,h[�109 O cm]

60 4 1.8 � 10�4 2.53 1.60 2.1 � 10�4 �6.84 7.1912 2.4 � 10�4 4.22 15.6 1.2 � 10�3 �2.88 9.7816 1.4 � 10�4 3.40 115.15 4.2 � 10�4 �3.41 10.70

a Active layer (n-channel). b Active layer (p-channel).

Fig. 5 Schematic of the conduction process in the TC-BG SnCl2Pc/CuPcheterostructure transistor for (a) n-channel, (b) p-channel operationsunder different bias conditions. The flow of electrons and holes is indi-cated with arrows in respective cases.

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In staggered TC-BG OFETs (where the contact and theaccumulation layer are formed at opposite sides of the semi-conducting layer), the gate-voltage dependent Rc has beenobserved to mainly arise from current crowding. At a smallgate bias, the bulk semiconductor between the contacts and thechannel would be highly resistive if the injected charges arelimited, and the injection is confined in a small contact areaclose to the channel. At a higher gate bias, charges accumulatein the channel and also spread far from the channel interfaceand thus increase the bulk conductivity at contacts. Moreover,charge injection extends to a larger contact area, as the injec-tion current gets more and more crowded and consequently Rc

decreases. It has also been found that in staggered devices,Rc does not change significantly. Thus, the optimized SnCl2Pc/CuPc heterostructures result in the gate-voltage independent Rc

and signifies Ohmic contacts.Besides the static device characteristics, the dynamic device

characteristics are correlated significantly to the SnCl2Pc/CuPcheterojunction. Fig. 7(a) shows the bias stress results at positiveVGS and VDS (VGS = VDS = 8 V) in the ambipolar OFETs, i.e., theoperational instability of the electron-dominant drain–sourcecurrent, IDS(t), normalized by IDS(0), where IDS(0) is the initialmaximum source–drain current established right after thetransistor is on (in n-channel and p-channel regimes) for SnCl2Pc

(60 nm)/CuPc(4 nm). In SnCl2Pc/CuPc bilayer heterojunctionOFETs, the bias stress effect under dark conditions is very small;the current decreases by only 5–7% after a continuous bias-stressing for 1 h at VGS = VDS = 8 V in the n-channel regime(Fig. 7(a)) and shows a similar small decay (o10%, see Fig. 7(b))in the p-channel regime (VGS = VDS = �8 V). It is noticeable thatinitially (t o 50 s) IDS increases to some extent and then decays ina longer time for both n-channel and p-channel devices. It isbelieved to be caused by dipoles that can be oriented at thePMMA/Al2O3 interface or at Al2O3 bulk.42 Although the SnCl2Pc-based unipolar OFETs show good bias stress stability, the biasstress effect for electron-dominant IDS in the ambipolar OFETs isgenerally significant.

The bias stress-induced decay of the drain–source current,IDS, in OFETs can be described by a stretched-exponential time(t) dependent formula applicable to a wide variety of disorderedsystems and can be written as (when field effect mobility, mFE, isalmost constant),43,44

IDS tð Þ ¼ IDS 0ð Þ exp � t

t

� �b� �; (2)

where b is the stretching parameter (temperature dependent) relatedto the barrier energy height for charge trapping (0 o br 1), t is therelaxation time, and IDS(0) is the initial maximum drain–source

Fig. 6 (a) Electron (me), and hole-mobility (mh) in SnCl2Pc/CuPc bilayer heterostructure OFETs using Ag electrodes as a function of the thickness of theCuPc bottom layer with a fixed thickness (60 nm) of the SnCl2Pc top layer. (b) Contact resistance in the n-channel (Rc,e) and p-channel regions (Rc,h) ofthe corresponding devices prepared using the Y-function method. (c) and (d) Gate bias dependence of the channel width normalized contact resistancefor the TC-BG devices based on SnCl2Pc (60 nm)/CuPc (x nm, x = 4, 12 and 16) in n-channel and p-channel regions, respectively.

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current measured at the beginning of stressing. Althoughthis model was originally developed to describe the bias-stress effect in amorphous silicon transistors considering thetime-dependent evolution of trap states due to hydrogen migra-tion, we employ a similar formalism to describe a dispersivetrapping process in OFETs. A stretched exponential function(eqn (2)) provides a perfect fit to the data in both n-channel andp-channel systems. Fig. 6(a and b), shows the data points(symbols) as well as fitted lines using eqn (2). The values of tat room temperature, extracted from the fitting are 4.28 � 105 sand 1.58 � 105 s in n-channel and p-channel devices, respec-tively. The corresponding exponent values are b = 0.57 and 0.67,respectively. The large t values imply a long-term stability of

the device, which is very much desirable for practical applica-tions. Considering that the interfacial chemistry at the hetero-junction remains identical, the bias stress effect is primarilyattributed to structural defects at the SnCl2Pc/CuPc interface,which may generate deep traps for electrons in the n-channel. Ithas been proposed that the time-dependent charge trapping indeep traps is responsible for the bias stress effect in OFETs andthus, charge traps at organic heterojunction can be the sourceof the small bias-stress instability in the n-channel device.45

As for the bias stress effect in the p-channel device shown inFig. 7(b), it has less dependence on the SnCl2Pc/CuPc hetero-interfacebecause the p-channel is close to the CuPc/PMMAdielectric interface rather than the SnCl2Pc/CuPc heterointerface.Therefore, both the organic/dielectric and organic/organic inter-faces influence the bias stress effect in bilayer ambipolar OFETs.1,45

To study the influence of the gate bias on the cyclic biasstress behavior, we measured the drain–source current, IDS ofbilayer ambipolar OFET applying a gate-source voltage VDS = 6 Vwhile changing VGS = 6 V in the ‘‘ON’’ state (for 180 s) and VGS =0 V in the ‘‘OFF’’ state (for 180 s). It is plotted as a function oftime in Fig. 7(c). During the ‘‘OFF’’ state, the drain currentslowly decreases with time and in the ‘‘ON’’ state it sharplyraises to its maximum value. It is noticeable from Fig. 7(c) thatnegligible decay of the maximum drain current (‘‘ON’’ state)occurs after repeated ‘‘ON’’ and ‘‘OFF’’ states during 3600 s ofoperation at room temperature under low vacuum. The timeconstant for decay of current during the ‘‘OFF’’ state is B333 s.We acquired the transconductance curves before and after cyclicbias stress of 1 h for both channels and they show no shift of thethreshold voltage (Fig. S3, in ESI†) after the bias stress. Thus, thedevices are very stable under low vacuum conditions.

3. Conclusion

In conclusion, we have demonstrated an ambipolar OFETbased on the heterojunction of low band gap SnCl2Pc and CuPcsmall molecules that exhibit ambipolar conduction dependingon the applied gate bias, either an accumulation layer of holes(negative gate bias) is formed in the CuPc layer or an accumula-tion layer of electrons (positive gate bias) is formed in theSnCl2Pc layer of the heterostructure device. The change inoperation mode was attributed to the appropriate choice ofthe organic/organic heterojunction and the contact electrodemetal work function. The change in the layer thickness resultedin evolution of the field-effect mobility values and an optimizedthickness SnCl2Pc/CuPc heterostructure yielded a balancedcarrier mobility (B10�4 cm2 V�1 s�1). The bias stress effectand contact behavior in the bilayer ambipolar OFETs have beeninvestigated. For the top SnCl2Pc n-channel, a smooth andcontinuous organic heterojunction enabled not only high biasstress stability (t B 105 s) but also optimal contact resistance(RC) for efficient carrier injection. For the bottom CuPc p-channel,the hole injection may be realized by the Ag penetration intoSnCl2Pc to form a local direct contact with CuPc, and the biasstress stability is dependent on the CuPc/dielectric interface

Fig. 7 (a) and (b) Normalized drain–source current decay IDS(t)/IDS(0) as afunction of time in the n-channel (SnCl2Pc = 60 nm) at the electronaccumulation state and IDS(t)/IDS(0) in the p-channel (CuPc = 4 nm) at thehole accumulation state. (c) Cyclic stability with the ‘‘ON’’ and ‘‘OFF’’ cyclesup to 3600 s for the TC-BG heterostructure ambipolar OFET device basedon SnCl2Pc (60 nm)/CuPc (4 nm).

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rather than on the organic heterojunction. Using low workfunction Ag as a top contact and a hydroxyl-free PMMA gatedielectric, the electron injection is greatly enhanced, leading toan improvement of both the electron and hole currents in thesaturation region. We believe that the present results are signifi-cant to develop further understanding of the carrier transportationprocess in organic–organic (p–n) heterojunction, and will be help-ful to develop the fabrication of stable ambipolar OFETs, which aresuperior candidates for organic complementary circuits, organiclight emitting field-effect transistors and organic lasers.

4. Experimental sectionMaterials

Tin(IV) phthalocyanine dichloride (SnCl2Pc) (C32H16Cl2N8Sn)and copper phthalocyanine (CuPc) (C32H16CuN8), which servedas organic semiconductors in all devices were purchased fromAlfa Aesar, UK. Poly(methyl methacrylate) (Alfa Aesar, PMMA,Mw B 550 000 kg mol�1, 25 mg ml�1 in anisole) was used as apolymer gate dielectric. A silver (Ag) wire (Alfa Aesar, 97%) wasused for evaporation of source/drain (S/D) contacts. All materialswere used as received without any further purification.

Heterostructure device fabrication

To form the control gate, about 150 nm thick layer of aluminum(Al) (Alfa Aesar, 99.9% pure) was vacuum deposited at a rate of30 Å s�1 on to clean glass substrates. The Al layer was anodizedby immersing in citric acid solution prepared using ultra-pure(18.2 MO cm) de-ionized water as a solvent, 1 mM L�1. Aconstant current density of 0.3 mA cm�2 was maintained untilthe voltage reached 10 V, and the voltage was then maintainedat 10 V until the current density dropped to 0.015 mA cm�2. Thethickness of the Al2O3 was estimated to be 13 nm, given theanodization ratio (cAl E 1.3 nm V�1).27 A thin buffer layer ofPMMA was coated at 5000 rpm for 60 s to deposit a very thinand uniform layer on the Al2O3 surface and annealed at 80 1Cfor 30 min under low vacuum to remove residual solvents. Themorphological analysis was carried out using an AFM (Agilent-5500) in the tapping mode. Fig. S4(a) (ESI†) shows the AFMimage of PMMA deposited on the Al2O3/Al/glass substrate.PMMA can provide a high-quality hydroxyl free interface tothe organic semiconductor with a high dielectric breakdownstrength (B1 mV cm�1). The optimized thickness of PMMAlayer was 100 nm, as measured using a surface profilometer(Veeco Dektak-150). The root-mean-square (RMS) roughness(Rq) of PMMA was 0.231 nm, as measured using AFM, whichwas much lower than the thickness of the anodized Al2O3 layer(E5 nm). A 60 nm-thick SnCl2Pc film was deposited on theCuPc layer (with different thicknesses) on to the PMMA/Al2O3

dielectrics under identical conditions at a rate 0.8 Å s�1 usingthermal evaporation at a base pressure of B10�6 mbar. Thesubstrate temperature was kept at 60 1C during all depositions.Finally, using a thermal vacuum deposition chamber, a 450 nmsilver (Ag) top electrode drain/source (S/D) was deposited andpatterned through a shadow mask on the substrate to complete

the device structure, where the device channel length (L)and channel width (W) were determined to be 30 mm and780 mm, respectively. The surface morphology of the organicthin films was characterized under ambient conditions by AFMin tapping mode.

Device characterization

We fabricated SnCl2Pc top-contact OFETs on the PMMA/Al2O3

substrate. The capacitance density Ci (nF cm�2) was measuredfrom a metal–insulator–metal structure of a parallel plate capacitorwith different contact areas. The buffer layer PMMA on Al2O3 gavea capacitance density Ci of B 31 nF cm�2. The leakage currentdensity, J (A cm�2) through the gate dielectrics was very small(B10�7 A cm�2) [see Fig. S4(b), ESI†]. The electrical characteristicsincluding the voltage–current relationship and capacitancewere measured using a Keithley 4200-SCS system at room tem-perature in a probe station (Lake shore, USA) under low vacuum(B10�3 mbar). The field-effect mobility (mFE) was calculated in thesaturation regime using the equation, |IDS| = (WCi/2L)me(VGS� VTh,e)

2

and |IDS| = (WCi/2L)mh[VDS� (VGS� VTh,e)]2 for electron and holetransport, respectively where W is the channel width (780 mm)and L is the channel length (30 mm), Ci is the capacitance ofPMMA/Al2O3 gate dielectrics (B31 nF cm�2).

Acknowledgements

We thank Dr Mujeeb Ullah, Centre for Organic Photonics &Electronics, University of Queensland, for providing valuablesuggestions on the anodization process. We also thank Prof.P. K. Iyer for extending the experimental facilities to carry outpart of this work.

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