Javier Pardo Garcia 2014/6/12 Master’s Thesis in...

FACULTY OF ENGINEERING AND SUSTAINABLE DEVELOPMENT .

Measurement and circuit modeling of advanced interconnect reliability

Javier Pardo Garcia

2014/6/12

Master’s Thesis in Electronics

Master’s Program in Electronics/Telecommunications

Examiner: Jose Chilo

Supervisor: Francky Catthoor and Kristof Croes

Javier Pardo Garcia Measurement and circuit modeling of advanced interconnect reliability

i

Preface

I must thank Dr. Francky Catthoor, Dr. Kristof Croes, Dr.Yunlong Li and all the team of

Reliability and Modeling (REMO) at imec. They really give me a lot of help and instructions

for completing this Master´s thesis. On the other hand I want to thank the University for

Gävle for giving me the opportunity to do my studies and the possibility to perform the thesis

abroad.

I also thank my family and my father. Sadly, he passed away 2 years and 3 months ago but he

would have been really proud of me.


ii

Abstract

This MSc-Thesis is focused on the development and calibration of a model for Time Dependent

Dielectric Breakdown (TDDB) of low-k dielectrics that are necessary in future deeply scaled

technologies. The workflow of this project is divided in two parts, the experimental part and the

modeling part.

The experimental part involves a series of measurements in the Constant Voltage Stress (CVS)

regime, carried out at “Automated Measurements in Imec (ANSIMEC) Central lab for electrical tests”,

in Leuven Belgium. A special hardware setup has also been built for this. The context of this work, in

terms of the equipment that has been used, the testing structures, the software environment, the

experimental conditions and the evaluated results, is described in this part.

In the modeling part, the collected data are analyzed and evaluated and then a methodology has been

proposed and implemented for calibrating two state-of-the-art TDDB models for both the parametric

effects (or leakage current over time) and hard-breakdown (or Time to Failure) of interconnects’

dielectrics.


iii

Table of contents

Contents

Preface ...................................................................................................................................................... i

Abstract ................................................................................................................................................... ii

Table of contents .................................................................................................................................... iii

1 Introduction .......................................................................................................................................... 1

1.1 Aims and objectives ...................................................................................................................... 2

1.2 Why ............................................................................................................................................... 3

1.3 Outline ...........................................................................................................................................3

2 Theory...............................................................................................................................................4

2.1Low-k ............................................................................................................................................. 4

2.2 Back end of line (BEOL)............................................................................................................... 4

2.3 Time dependent dielectric breakdown(TDDB)..............................................................................5

2.3.1 Inter-metal dielectric leakage......................................................................................................5

2.3.2 Break-down..................................................................................................................................5

2.4 Copper diffusion.............................................................................................................................6

2.5 Moisture absorption and Porosity influence...................................................................................7

3 Hardware and Software ........................................................................................................................ 8

3.1 Thesis Process ............................................................................................................................... 9

3.2 SD30 Mask Characteristics...........................................................................................................10

3.2.1 Twin Peaks Mask Characteristics .............................................................................................10

3.2.2 Curve Fitting tool ......................................................................................................................10

3.3 DC Measurements.........................................................................................................................11

3.4 AC Measutements.........................................................................................................................12

4 Process and Results ....................................................................................................................... 13

5 Conclusions ................................................................................................................................... 26

References ............................................................................................................................................. 27

Appendix A .......................................................................................................................................... A1


iv

Appendix B ........................................................................................................................................... B1

Appendix C ........................................................................................................................................... C1


1

1 Introduction

The advanced process technology for IC fabrication is in continuous progress to further scaling. The

dimensions of both devices and wires progressively shrinks. In order to achieve this, the technology

becomes more and more complex and additional materials and technological steps have to be

introduced in order to enable the proper electrical behavior in a sufficiently reliable way. Here we

focus on the wires, where especially the resistance R and the capacitance C are the main parameters.

They directly impact both the delay (inversely proportional to the RC product) and the energy

(proportional to the C). Traditionally, the metal wires have been prone to a wear-out mechanism where

metal atoms are moving due to the presence of strong currents: electro-migration. This leads in the end

to voids in the metal and an increase of the R value.

In more recent technology nodes, an additional reliability problem has started to occur. In order to

keep the C sufficiently low, the traditional metal wires need to be surrounded by a dielectric layer. In

order to keep the C low, a so-called low-k material needs to be used for this. Relative to the shrinking

wire dimension, this dielectric layer is becoming more and more important. As a result also its

weaknesses in terms of the degradation over the life time of the wire usage are becoming more

dominant. The reliability of this dielectrum is indeed limited, especially when higher voltages or

higher temperatures are present over long time periods. As a result of this, a mechanism called Time-

dependent-dielectric breakdown (TDDB) is present which initially degrades the C value of the wire,

increasing both the energy and the delay. When the stress continues, the TDDB leads to the full

breakdown of the dielectrum, meaning that a continuous leakage current flows from the metal into the

bulk of the silicon device. That leakage current degrades both the energy and the delay and hence

strongly impacts the electrical behavior of the affected wire. Hence, these TDDB issues form a threat

to further scaling of the interconnect in these advanced technology nodes. So the introduction of these

low-k materials introduces more and more risks for TDDB, resulting in a potentially reduced time-to-

failure and excessive leakage current. These effects have to be carefully studied to understand their

mechanism and to characterize their impact. This Master’s Thesis is focused on measurements and

modeling the expected breakdown and degradation of future CU/low-k interconnect and dielectrics in

an advanced 14 nm technology node. Up to now a large number of studies have been performed on

static DC stress but they aren’t fully calibrated for the newest technology nodes and they are not

covering dynamic workload-dependent breakdown effects [5-8].

In the conventional method of measurement for TDDB, the variation in leakage current is measured

under stressed structures with high voltage, constant (DC) and high temperature, until the moment the

breakdown of the dielectric starts to happen. In order to have results within a reasonable time the

TDDB has to be accelerated so high voltage/temperature conditions are necessary during the


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measurement. To analyze the global and especially workload-dependent TDDB impact, we will trace

the degradation of the dielectric in a pair of neighboring parallel wires by applying a varying voltage

workload under different temperature conditions, and we will monitor the resulting leakage current

behavior until a final hard breakdown occurs.

1.1 Aims and objectives

The aim of this Master’s Thesis is to develop a model of TDDB of deeply scaled interconnects and the

corresponding leakage mechanism under realistic working conditions. The essential objective of this

thesis work is collecting data to be used for the calibration of that model with accurate data from test

chips measurements of a future 14 nm technology node. Test structures for this have been processed

at IMEC.

Another objective is to research TDDB under workload-dependent AC stress, again simulating

realistic working conditions. From these results designers can arrive at conclusions to improve the

reliability of interconnects by mitigation techniques including ways to improve the future design of

such circuits.

1.2 Why

The real aim of the measurements is to provide insight in the underlying TDDB reliability mechanisms

and to calibrate the models. And the models are needed to be able to predict what happens in situations

that are different from the measurement conditions, in particular (much) lower voltages, and especially

workload input stimuli shapes (sequences of 0 and 1 bits in a bit stream applied as input to and adder

e.g.). We cannot exhaustively measure those because we have to wait too long for low voltages to be

applied, and the nr of possible different 0-1 bit streams is simply too large also. So it is not practically

doable without a parameterized model.

The model allows us insight in how TDDB affects the circuit (e.g. a microprocessor) under specific

conditions. Potentially it can also enable steering a run-time control engine that tries to mitigate the

negative TDDB impact. That mitigation approach and the corresponding control engine are being

developed in an ongoing PhD thesis at this moment and we hope to be able to prevent that the wires


3

are degrading as much as they would do with the current approaches which ignore the workload-

dependent effects.

1.3 Outline

The following chapters explain the theory, process, results and conclusions. The theory chapter 2

includes all the theory concepts to understand the thesis and the workflow of the thesis. In the chapter

3 a description is included of the hardware and software used, and also of the measurement techniques

used during this thesis.

The process and result chapter 4 includes the measurements of the thesis and the modeling

methodology used to achieve firm conclusions.

The last chapter of the thesis discusses the overall results and it provides a conclusion.


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2 Theory

The theory chapter explains the methodology applied and principal concepts during the process of this

thesis. This chapter provides a basic understanding of concepts, process, hardware and software used.

2.1Low-k dielectrics

The low-k material is extensively used for Cu/low-k interconnect to reduce the dielectric constant by

adding porosity. But the reliability worry of the dielectric breakdown of Cu/low-k interconnect is

more significant when “k” is reduced, because of the low intrinsic breakdown threshold and the higher

fields due to the much smaller interconnect size and spacing. Hence we can say that it is an important

problem and we need a thorough understanding of the breakdown behavior. The main reason for the

dielectric breakdown is the Cu ion drift at dietetic low-k.[1]

2.2 Back end of line (BEOL)

Back-end-of-line is added in the second stage of the Integrated Circuit fabrication process. Metal

interconnect is deposited at several layers (typically 8 or more) to provide a connection between the

front-end-of-line devices such as resistors, transistors and capacitors. The Back End Of Line process

normally starts when the first metal layer is deposited on the wafer. Back end of line incorporates

several metal levels (can be more than a dozen), inter-layer via’s, bonding sites and dielectrics.[2]

Figure(1): typical BEOL metal wire and via stack with intermediate dielectric material


5

2.3 Time dependent dielectric breakdown(TDDB)

The TDDB mechanism is divided in two stages: the inter-metal dielectrics leakage which occurs

during the build-up phase and the hard break-down which is the main mechanism during the run-away

phase. A description of both stages is provided below.

2.3.1 Inter-metal dielectrics leakage

In Cu damascene structures there is an electrical transport among two neighboring lines when these

are under electrical stress. This phenomenon produces a stressed behavior in the metal-insulator-metal

capacitor stack. The temporary conduction leads to a leakage current that will increase the power

consumption and that will heat up the chip which further increases the current flow. [4]

2.3.2 Break-down

During this final process stage, the dielectric break-down threshold is met when electric fields applied

to the device and the electric field collected by charge injection exceeds the break-down in some weak

points of the dielectric. An example of break-down is shown in the Figure (2).

Typical factors that can decrease the TDDB-related lifetime are moisture absorption, low-k material

estate degradation with the porosity gain, and copper contamination of the low-k dielectric [3].

Figure(2): (a) Breakdown area , (b) SEM image of dielectric Breakdown


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2.4 Copper diffusion

The TDDB could be reduced radically with the presence of Cu in the dielectric material. The trend

from the Figure (3) shows a curve that decreases when the copper contamination concentration

increases. The degradation of TDDB is caused by big diffusion and Chemical-Mechanical Polishing

surface diffusion respectively, for copper structures with and without metal barriers [10].

Figure(3): TDDB plotted as a function of Cu concentration

When the barrier is deficient the dielectric could go to a pseudo breakdown instead of a hard

breakdown. [11]


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2.5 Moisture absorption and Porosity influence

Another TDDB factor for low-k is moisture absorption. In that case, the breakdown resistance is

reduced leading to a leakage increase. Research in moisture absorption with leakage current

measurements on an integrated metal leads to enhanced conductivity.

The porosity can strongly influence the TDDB lifetime, the breakdown threshold decreases when the

porosity of the material increases. [11]


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3 Hardware and Software

3.1 Thesis proceedings

The Figure (3) describes the process of this thesis. It is divided in two main parts: an experimental

measurement activity and a modeling part.

Figure(3): Thesis Workflow

The experimental part involves a series of measurements in the Constant Voltage Stress (CVS)

regime, carried out at “Automated Measurements in Imec (ANSIMEC) Central lab for electrical tests”,

in Leuven Belgium. A special hardware setup has also been built for this. The context of this work, in

terms of the equipment that has been used, the testing structures, the software environment, the

experimental conditions and the evaluated results, is described in this part.

In the modeling part, the collected data are analyzed and evaluated and then a methodology has been

proposed and implemented for calibrating two state-of-the-art TDDB models for both the parametric

effects (or leakage current over time) and hard-breakdown (or Time to Failure) of interconnects’

dielectrics.

Experimental• Hardware used in the lab for measurements

• Mask-set Characteristics

• Software used for modeling

Modeling • Matlab Curve fitting toolbox

Conclusion • Results


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3.2 SD30 Mask characteristics

The 300mm wafer “SD30” has been provided by IMEC. This wafer is adequate to TDDB test given

the selected lengths of each pair of parallel wires, the distance between the wires and the varying

shapes.

The SD30 mask set includes 4 masks. Two masks for METPASS and two other for PASS, for

passivation. In the first mask METAL1A and METAL1B are used for the first and second exposure

respectively.

The groups of structures on SD30 are:

Single pattering: both of them for long single lines

EM structures

CD Lines

Double pattering:

MF: Meander-Forks Structures

MF_CMP: long Meander- Fork (1x1 mm2)

PL2P: 2 parallel lines

FROKS: Fork-fork structure

The structures that are used in this thesis are parallel lines because we want to measure under what

voltage and time duration conditions the low-k dielectric between these lines will break down, both in

terms of parametric breakdown (leakage current increases) and hard breakdown (the dielectrum fully

collapses and a short is created between the metal lines).

The figure 4 below shows us the four dies Q1, Q2, Q3, Q4, all of these dies are present in each chip on

the wafer.


10

Figure(4): SD30 Floor plan

3.2.1 Twin- Peaks Masks Characteristics

Twinpeaks is a full CMOS platform maskset for 14nm technology node. It includes both FEOL

devices and BEOL test structures. In this maskset, we have a dedicated BEOL test structure group for

high frequency AC TDDB test, integrated in the M1 and passivation stack modules. This

documentation is highly confidential by imec given it is still in the early research stage. I cannot

include process details, material names, etc.

3.2.2 Curve Fitting tool

Matlab software with the inclusion of the Curve Fitting Toolbox is the suitable tool for the experiment

due the fitting capabilities. The regression analysis and statistical analysis present in that toolbox are

suitable for the purpose of this work. After some tests with the toolbox, it has become clear that the

rational function of a 5rd degree polynomial as a numerator and a 3rd degree polynomial as

denominator fits in a good way the data curve using the Levenburg-Marquardt LMA algorithm. LMA

is a common algorithm for solving problems of nonlinear least squares fitting, and it matches very

well to our approach.

𝑓(𝑡) =C5t5 + C4t4 + C3t3 + C2t2 + C1t + C0

Q3t3 + Q2t2 + Q1t + Q0

Equation (1) :Rational function to fit the TDDB data


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3.3 DC Measurements

The aim of this thesis is to develop a model for approximating hard breakdown voltage and TDDB

parameters of the dielectric degradation in scaled interconnects. Previous works on dielectric

breakdown are using physics as the “E” model [ ln (𝑡)∞𝐸] where E is the electric field applied and t is

the lifetime.

The E model experiments in previous studies indicate good results for earlier technology nodes, so it is

reused here. But we have to tune it to the future scaled interconnect. The proposed method to analyze

the experimental data, is using a well fit-able equation as input for the Curve Fitting tool of Matlab.

3.4 AC Measurements

Up to now the TDDB studies are focused on static DC Voltage stress. The intention of this work is to

advance this state-of-the-art, by studying a methodology for the study of TDDB under a dynamic

workload with a set of pulses. In order to have a good insight in reliability analysis the methodology

used will allow the waveforms to be arbitrary, to lead to a fully work-load dependent model.

The diagram Set-up for AC measurements is shown below, where we can appreciate the use of

different devices as Oscilloscope, AC waveform generator, Bias Tee and DC Source.

Figure(5) : Diagram AC Set-up


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The bias tee chosen for the Set-up implementation is ZFBT-6GW+ which has a frequency range of 0.1

Mhz to 6000 Mhz, high isolation and low insertion.

The left bias is playing a role as offset of the AC waveform, whereas the right one serves as the

ground of the DC component. Given the goal of tracking the changes in DC, the direct output before

the second bias Tee is mandatory. The scope samples the signals that are previously amplified by the

amplifier.


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4 Process and Results

4.1 Measurements

To measure the TTDD first of all we have to find the breakdown voltage value/threshold in order to

know the suitable voltage of the stress. The voltage higher than the hard breakdown voltage threshold

will be refused because the structures would fail immediately. Therefore to observe the degradation of

the structures evolving over time, the last measurement point has to be the hard breakdown point.

Structure tested:

The series of tests has been conducted with the test structures mentioned below sweeping over a

voltage range of 0-40 Volts at 100° C temperature.

Structure and stressing conditions

Standard

parallel lines

30nm width

25nm spacing

30nm spacing

35nm spacing

40nm spacing

1µm

100µm

171 samples

1 for die

0-40V

100° C

Table(1): test structures for I-V

The setup used to measure it is of type I/V using the tool Cascade S300 probe station HP4142B Pico-

amp Meter and the wafer ALI 123578/2.

The experiments show however that for the spacing of 25nm and 30nm the results are not stable for

firm conclusions. So for these spacing’s, the results will not be provided because the defects rates are

too high in the fabrication process. Moreover, for the lengths less than 10µm the short-circuited

behaviors present very abrupt I-V curve behavior which is not usable for our modeling purpose.

Hence, we have focused mainly on 35nm, 40nm spacing and 100µm length because these will allow

us to obtain firm conclusions.


14

Below are shown the curves of 35nm spacing 1µm length, 40nm spacing 1µm length, 35nm spacing

100µm length and 40nm spacing 100µm length.

Figure(6): I-V curve of 35nm S- 1µm L with 0-40V tamping voltage at 100° C

It can be clearly observed that the breakdown voltage is related with the interference length of the

interconnections lines and the spacing between them. In the way that the length of the lines increases

proportionally with the voltage of the point at which the dielectric is decreased and vice versa.


1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 10 20 30 40 50

Cu

rre

nt

(A)

Bias (V)

35nm spacing- 1µm length

4,-1

5,-1

6,-1

7,-1

3,-2

4,-2

5,-2

6,-2

7,-2

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 10 20 30 40 50

Cu

rre

nt

(A)

Bias (V)

40nm spacing-1µm lentgh

3,-1

4,-1

5,-1

6,-1

3,-2

4,-2

5,-2

6,-2

7,-2


15


However the breakdown voltage increases proportionally with the spacing increase between the lines

and vice versa. The process variations make the position of the curve change due to the nominal

behavior of the structures along the wafer not being the same.


1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 10 20 30 40 50

Cu

rre

nt

(A)

Bias (V)

35nm spacing -100µm length

4,0

5,0

3,-1

4,-1

5,-1

6,-1

7,-1

2,-2

3,-2

5,-2

6,-2

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 10 20 30 40 50

Cu

rre

nt

(A)

Bias (V)

40nm spacing-100µm length

4,0

5,0

3,-1

4,-1

5,-1

6,-1

7,-1

2,-2

3,-2

4,-2


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The set up for the “Current Versus Time under CVS” experiments is similar as the previous I-V

measurements. Once the breakdown voltage threshold has been identified, based on the definition of

it, the first set of measurements in CVS regime has been initiated.

For this stage we have focused on 40nm spacing and 1000µm length structures increasing the voltage

from 10.5V until 14V and with 100° C temperature. The TDDB results of 100µm length and 1000µm

would be quite similar given that they lie quite close to each other. If we want to measure TDDB for

the 100µm length within the same die, we should use another structure.

Structure and stressing conditions

Standard

parallel lines

30nm width

40nm spacing

1000 µm

28 samples

10.5V-14V

100° C

Table(2): Set of measurements

The time limits are shown in the table below, ranging for measurement conditions between 10.5V and

14V at the same temperature. The time limit is significantly decreasing when the voltage is increasing.

But this also means that under 10.5V the measurements are becoming too long for the available time

on the test equipment:

Test 10.5V 100° C 11V 100° C 12V 100° C 13V 100° C 14V 100° C

Time limit 3000s

0.8h

165.642s

2.76m

293.8s

4.89m

20.61s

0.3435m

10.67s

0.17m

Table(3): Set time limits


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The pattern chosen for TDDB is shown below where we have used the same sub dies “Q4” from

different dies in order to achieve the measurement of each test-structure in different areas of the wafer.

This kind of pattern has been selected, given that going too close to the wafer boundary could

introduce some uncertain values in the measurement, which can lead us to false conclusions.

Table (4) : Example measurement pattern

The figures below represent the resulting TDDB measurements. As you can appreciate, the axes are in

log scale to get better plotting and better understanding of the results. The results are accurate and very

good taking into consideration that the leakage current is inside the measurement range of the probe

station and we do observe significant noise in the results.

We can observe that the voltage stress are consistent in the figures. The resultingTDDB behavior is as

expected due to the availability of sufficiently accurate data.

Regarding to the Figure (7) we can see that the lower the voltage, in the degradation evolution the

current flow is going down. For that reason we can appreciate that in the Figure (10) the curves start


18

going down slowly initially and that continues until they will enter the hard breakdown region,

because the degradation in lower voltages is accelerated.

Figure10) : Measure curves of 40nm-S, 1000um-L under 10.5V stress at 100°C

It can be clearly seen that some of the curves do not end properly because the equipment determines

that for example the die ”7,-7” in the Figure (7) and the die 1,-19 in Figure (8) respectively are already

broken at this point. And then the measurement ends.

Figure(11) : Measure curves of 40nm-S, 1000um-L under 11V stress at 100°C

1.00E-12

1.00E-10

1.00E-08

1.00E-06

1.00E-04

1 10 100 1000 10000

Cu

rre

nt

(A)

Time (s)

10.5V-100°C

4,-2

7,-7

7,-8

4,-11

4,-13

8,-16

1,-18

5,-20

1.00E-12

1.00E-10

1.00E-08

1.00E-06

1.00E-04

1 10 100 1000 10000

Cu

rre

nt

(A)

Time (s)

11V-100°C

5,-2

2,-3

5,-6

4,-8

6,-10

0,-14

2,-17

1,-19


19


It can also be verified that the higher the voltage the lower the degradation and the time life is shorter

than with the lower voltages, because higher internal fields are present between the 2 parallel wires of

the test structure.


Increasing the voltage further up to 14 V in Figure (14), it can be observed that the amount of dies that

resist the voltage decreases considerably.

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1 10 100 1000 10000

Cu

rre

nt

(A)

Time (s)

12V-100°C

3,-7

1,-8

4,-9

0,-11

5,-12

3,-15

0,-16

5,-16

5,-19

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1 10 100 1000 10000

Cu

rre

nt

(A)

Time (s)

13V-100°C

5,-3

3,-5

1,-7

3,-9

0,-11

2,-13

2,-15

3,-18

4,-22


20


4.2 DC Model development

Intro

The best way that a model can be derived is by mathematical expression of the laws of physics

underlying the process involved but these laws are not always well-understood. So we can instead also

use a more experimental curve fitting approach. The present thesis is focused on this later approach, and

aims to model an approximation of the parametric effects and breakdown of TDDB, through curve fitting

of a function to the measure data.

Methodology

The used Curve fitting method can be used to optimize some dependent variables. The most common

approach for the optimization is using the least squares method where using this method will provide

us the date optimized as close as possible to the desired data set. The least squares method minimizes

the sum of the squares of the errors made in the result of every single equation.

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1 10

Cu

rre

nt

(A)

Time (s)

14V-100°C

5,-2

2,-3

5,-6

4,-8

6,-10

0,-14

2,-17

1,-19


21

Parametric Model

The main objective of this part is the extraction of a model that can characterize the leakage behavior

of interconnect structures. Therefore, the first step will be to exclude the data from the hard BD region

for all the samples.

Followed steps:

a) Find the function to fit the date for the experiment

b) Fitting the function defining the curve for every experiment

c) Find the average curve amongst different data set of every experiment.

The suggested method involves every set of parameters which has been applied, namely Voltage

stress, the interface Length of the lines and Temperature (V,L,T). The equation is a polynomial where

n is the degree and cx the coefficient of each term.

𝑓(𝑡) = 𝑐𝑛 + 𝑡𝑛 + 𝑐𝑛−1 ∗ 𝑡𝑛−1 + ⋯ 𝑐1 ∗ 𝑡1 + 𝑐0

𝐶𝑥 = 𝑓(𝑉, 𝐿, 𝑇)

In this way the values of the coefficients can be calculated given that the main goal is to express each

coefficient as a function of the parameters that we want to fit.

Function definition and fitting

Matlab software with the inclusion of the Curve Fitting Toolbox is the suitable tool for the experiment

due the fitting capabilities. The regression analysis and statistical analysis present in that toolbox are

suitable for the purpose of this work. After of some test with the toolbox the proper rational function

of 5rd degree polynomial as a numerator and 3rd degree polynomial as denominator fit in a good way

the data curve using the Levenburg-Marquardt LMA algorithm. LMA is a common algorithm for

solving problems of nonlinear lest squares and it fits very well to our approach.

𝑓(𝑡) =C5t5 + C4t4 + C3t3 + C2t2 + C1t + C0

Q3t3 + Q2t2 + Q1t + Q0

Equation (2) :Rational function to fit the TDDB data

Different fitting examples are presented below, the graphs are expressed in logarithmic scale for both

axes as this is better for later comparisons.


22

Figure (15): Figure of rational function (Red line) in actual values (blue dots) of 1000µm Length (40nm S)

structure under 10.5V stressing 100° C( x:time in seconds -y: current*109 )

On the Y axis, the leakage current is normalized by 109 (y=y*109) due to the fact that the fitting

algorithm performs better in this value range. The R- square is about 1 which indicates us that it is an

excellent fitting.


structure under 11V stressing 100° C( x:time in seconds -y: current*109)


23


structure under 12V stressing 100° C( x:time in seconds -y: current*109 )

The figure (17) and (18) present results at higher voltages which are important to add because they

represent the results for longer life times in the accelerated testing procedure. Figure (17) also presents

a small bump around x=50, when compared with the figure (16) and (18). This is probably due to a

small problem in the measurements at that point. The curve fitting procedure is then partly confused

by this and enters a small ”bump” in the curve fitted through the measured points. But this error is

relatively small so we have left it like this.


structure under 13 V stressing 100° C( x:time in seconds -y: current*109 )


24

In the figure (19) the highest voltage (14V) is reported. Here, the R-square factor is similar to the one

of figure (17). Measurements at even higher voltages would negatively affect the dielectric between

the 2 parallel wires in the test structure because the field will become too large. So that has been left

out of our measurement plan..


structure under 14V stressing 100° C( x:time in seconds -y: current*109 )

4.3 Average fitting

The experimental result consists of the measurement of 28 samples in different wafer dies. Then for

each sample we have 28 different curves fitted for each experiment. The next step is to obtain the

average curve (out of 28) that will be representative for each experiment. The method proposed is to

calculate the 𝑒𝑎𝑣𝑔(ln (𝑖)) function of every coefficient (out of 28 curves) to define each curve.

The average fitting from the voltages with 1000 µm length structure at 100° C is presented below. As

shown in the example of Figure (20), we can predict with quite good accuracy the current as a function

of time inside the range of the measured parameters.


25

Figure (20): Average fitting of the different fittings (x: time in seconds -y: current*109)

1E-10

1E-09

1E-08

0.0000001

0.000001

0.00001

0.1 1 10 100 1000 10000

Cu

rren

t (*

109)

Time "s"

Average Fitting

10.5 11V 12 13V 14V


26

5 Discussion and Conclusions

The reliability margin of interconnect has been pushed by the fast increase of technology scaling. The

low-k dielectrics in combination with copper (Cu) interconnects is the main trend to address the

problems in growing bandwidth requirement and increased wire delays in deeply scaled technology

nodes. Nevertheless, interconnect systems based on Cu/low-k are currently not well unprotected to soft

or hard breakdown due to the manufacturing process. The time-dependent dielectric breakdown (TDDB)

mechanism is one of the major issues which has to be addressed for dealing with this [9].

The current thesis researches the degradation and the failure in deeply interconnects, as a result of

TDDB. An approximated TDDB model has been proposed. This model describes Time to Failure under

the applied voltage field, temperature and the length between lines. This model has been provided by

the Central Lab for electric test of IMEC. The model has been derived and calibrated from experimental

data 32nm half-pitch test structure.

Such parameterized work largely existed already for DC input stimuli but the proposal in this thesis can

be a ground for further research in the AC direction, as explained further. This current model has two

different aspects with respect to TDDB.

a) It can be used as an indicator to help the engineer in future physics model. This model is created

from experimental data

b) It is calibrated with 32nm half-pitch interconnects (SiOCH low-k). It is experimental data from

test structures processed in a recent technology node at IMEC.

Another important contribution of this work is the proposal of a method for AC TDDB measurements

(High Frequency, cycle pulses). Nowadays the current studies are focused in DC measurements which

means that almost no studies deal with low voltage periodic pulses. Nevertheless, to have an

understanding of the behavior of the high frequency and the cycle pulses in terms of the TDDB impact

can help to improve the workload-dependent reliability characterization and mitigation for the future

interconnects.


27

References

[1] Shou-Chung Lee, A.S Oates and Know-Ming Chang,”Fundamental understanding of porous

low-k dielectric breakdown,” Anual International Reliability, p-p 481-485, Montreal, 2009.

[2] Karen A. Reinhardt and Werner Kern,“Handbook of Silicon Wafer Cleaning

Technology,” (2nd ed.), William Andrew, p-p 202, ISBN 978-0-8155-1554-8, 2008.

[3] Y.Li, ”Low-k dielectric reliability in copper interconnects,” Ph.D, dissertation. KULeuven,

Belgium, 2007.

[4] V Adamec and J H Calderwood,”Electrical conduction and polarisation phenomena in

polymeric dielectrics at low field,” Journal of Physics D: Applied Physics vol.11, p-p 517-525,

2005.

[5] F. Chen, P. Mc Laughlin, J. Gambino, E. Wu, J. Demarest, T. Sullivan and M. Shinosky in

”Proceeding of 45th Annual IEEE Reliability,” Physics Symposium, p-p 382-389, 15-19 April,

2007.

[6] J. Noguchi, N. Miura, M. Kubo, T. Tamaru, H. Yamaguchi, N. Hamada, K. Makabe, R.

Tsuneda, and K. Takeda, “Cu-ion-migration phenomena and its influence on TDDB lifetime in

Cu metallization” in Proceedings of IRPS, p-p 287–292, 2003.

[7] N.Suzumara, S. Yamamoto, D. Kodama, K. Makabe, J.Komori, E.Murakami, S. Maegawa, and

K.Kubota in ”Proceeding of 44th Annual IEEE Reliability,” Physics Symposium, p-p 484-489,

26-30 March, 2006.

[8] G. Haase, E. T. Ogawa, and J. W. Mc Pherson in ”Processing of 43th Annual IEEE Reliability

Physics Symposium,” p-p 466-473, 17-21, April, 2005.

[9] M. Bashir and L. Milor, ”Towards a Chip Level Reliavility Simulator for Copper/Low-k

Backend Processes,” Georgia Institure of Technology, 2010.

[10] J.Noguchi, N.Ohashi, J.Yasuda, T. Jimbo, H. Yamaguchi, N. Owada, R. Tsenuda and K.

Takeda, ”Cu –ion-migration phenomena and its influence on TDDB lifetime in Cu

metalization,” in Proceedings of IRPS, p-p 287-292, 2003.

[11] R. Tsu, J. W.McPherson, and W. R. McKee, ”Leakage and breakdown reliability issues

associated with low-k dielectrics in a dual damascene Cu process,” in Proceedings of IRPS, p-

p 348-353, 2000.

http://en.wikipedia.org/wiki/International_Standard_Book_Number

http://en.wikipedia.org/wiki/Special:BookSources/978-0-8155-1554-8


A1

Appendix A

TCPIP Connection of Tektronix TDS6124C

1- Settings on the scope:

a. Control Panel / Network Connections / Local Area Connection, right-click, select

‘Properties’

b. Scroll down to TCPIP properties, click ‘Properties’ button

c. Select ‘Use the following IP address’: IP address 192.168.0.1, subnet mask

255.255.255.0

d. Start / All Programs / TEKVISA / VXI-11 Server Control

i. An icon appears in the system tray

ii. Right-click, server properties: location = 192.168.0.1

iii. Right-click, Start VXI-11 Server

e. (not sure if this is really needed) Open TekVISA resource manager configuration,

under ‘Preferences’, check the ‘search for LAN instruments’ box. To search locations,

add 192.168.0.1

2- Settings on the client PC:

a. Make sure TekVISA is installed.

b. Assign a static IP address to the interface (e.g. 192.168.0.2),subnet mask

255.255.255.0

c. Open the OpenChoice Instrument Manager, Update the instrument list. The scope

should appear as “TCPIP::192.168.0.1::INSTR”

d. Open the OpenChoice Talker Listener, select the “TCPIP::192.168.0.1::INSTR” from

the Instruments list and e.g. query the *IDN? Command.

e. E.g. in c#: add a reference to

C:\Windows\assembly\GAC_32\TekVISANet\1.1.1.0__7f19bb2a5a9ae6e8\TekVISA

Net.dll

f. Example c# code:

TekVISANet.VISA TVA = new TekVISANet.VISA(); TVA.Open(VISAResourceName);

TVA.Write("*IDN?"); status = TVA.Read(out response);

3- Appendices:

a. Tektronix FAQ2718, b. http://www1.tek.com/forum/viewtopic.php?f=5&t=5284

http://www1.tek.com/forum/viewtopic.php?f=5&t=5284


A2

4- TEKTRONIX FAQ 2718

a. Starting up the Oscilloscope, minimize the TekScope Windows Application to view

the Window Desktop.

b. If the VXI-11 Server Icon is not displayed in the Windows Desktop tool bar (lower

right-hand corner) then launch the VXI-11 Server application from Windows Start,

All Programs, TekVISA, and VXI-11 Server Control.

c. The VXI-11 Server Icon will then be displayed in the Window Desktop tool bar.

d. If the VXI-11 Server application is not started a red circle will be displayed over the

Icon.

e. To start the VXI-11 Server right mouse click on the VXI-11 Icon, and in the VXI-11

Server Control window select ‘Start VXI-11 Server’. The red circle will disappear.

VXI-11 Server Control may be setup to automatically start at power-up by selecting

Server Properties, ‘Start Server Automatically at system power-up’.

f. This completes the Oscilloscope VXI-11 Server initialization for an Ethernet remote

control connection.

g. Next, you’ll need to install, and configure a VXI-11 Client on the network PC

controller. You may down load TekVISA at:

http://www2.tek.com/cmswpt/swfinder.lotr?va=1 or, National Instruments NI-VISA

at: http://www.ni.com/support/visa/.

Both VISA (VXI-11 Client) applications are compatible with the VXI-11

Oscilloscopes.

http://www2.tek.com/cmswpt/swfinder.lotr?va=1

http://www.ni.com/support/visa/


A3

6- TEKTRONIX Forum C# Example: using TekVISANet.dll using System;

using System.Collections.Generic;

using System.Linq;

using System.Text;

namespace ConsoleApplication6

{

class Program

{

static void Main(string[] args)

{

System.Collections.ArrayList instrlist;

int j;

float ymult, yzero, yoff, xincr, timepoint;

string response;

bool status;

TekVISANet.VISA TVA = new TekVISANet.VISA();

// Print list of VISA resources

TVA.FindResources("?*", out instrlist);

Console.WriteLine("Visa Resources");

for (j = 0; j < instrlist.Count; j++)

{

Console.WriteLine(j.ToString() + " : " + instrlist[j]);

}

Console.WriteLine("\n");

// Connect to a known instrument and print its IDN

TVA.Open("USB0::0x0699::0x0425::CQ010017::INSTR");

TVA.Write("*IDN?");

status = TVA.Read(out response);

if (status)

{

Console.WriteLine(response);

}

// Get curve data for channel 1, and scale to volts.

byte[] rawwave;

float[] wave;

TVA.Write("DATA:SOU CH1");

TVA.Write("DATA:WIDTH 1");

TVA.Write("DATA:ENC RPB");

TVA.Query("WFMPRE:YMULT?", out response);

ymult = float.Parse(response);

TVA.Query("WFMPRE:YZERO?", out response);

yzero = float.Parse(response);

TVA.Query("WFMPRE:YOFF?", out response);

yoff = float.Parse(response);

TVA.Query("WFMPRE:XINCR?", out response);

xincr = float.Parse(response);

TVA.Write("CURVE?");

TVA.ReadBinary(out rawwave);

Console.WriteLine("Number of Points " + rawwave.Count());

Console.WriteLine(rawwave[0].ToString());

Console.WriteLine(rawwave[1].ToString());

wave = new float[rawwave.Count()];

for (j = 0; j < rawwave.Count(); j++)

{

http://www1.tek.com/forum/viewtopic.php?f=5&t=5284&start=0&st=0&sk=t&sd=a


A4

wave[j] = (rawwave[j] - yoff) * ymult + yzero;

}

//print the first 100 scaled waveform values to the screen

for (j=0; j < 100; j++)

{

Console.Write(wave[j].ToString() + ",");

}

//write waveform to a csv file

System.IO.StreamWriter file = new System.IO.StreamWriter("test.csv");

file.WriteLine("V,S");

for (j = 0; j < wave.Count(); j++)

{

timepoint = j * xincr;

file.WriteLine(wave[j].ToString() + "," + timepoint.ToString());

}

file.Close();

Console.WriteLine("\nPress Enter to exit");

Console.ReadLine();

TVA.Close();

}

}

}


B1

Appendix B

In this appendix are enclosed the Breakdown voltage pictures.

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 5 10 15 20

Cu

rre

nt

(A)

Bias (V)

CAP-PL_Q1-.03_.025_10000-AG4

3,0

6,0

3,-3

6,-3

3,-6

6,-6

0,-9

3,-9

6,-9

9,-9

0,-12

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 5 10 15 20

Cu

rre

nt

(A)

Bias (V)

CAP-PL_Q1-.03_.025_100-AD4

3,0

6,0

3,-3

6,-3

3,-6

6,-6

0,-9

3,-9

6,-9

9,-9


B2

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 5 10 15 20

Cu

rre

nt

(A)

Bias (V)

CAP-PL_Q1-.03_.03_10000-AG6

3,0

6,0

3,-3

6,-3

3,-6

6,-6

0,-9

3,-9

6,-9

9,-9

0,-12

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 5 10 15 20

Cu

rre

nt

(A)

Bias (V)

CAP-PL_Q1-.03_.03_100-AD6

3,0

6,0

3,-3

6,-3

3,-6

6,-6

0,-9

3,-9

6,-9

9,-9

0,-12


B3

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 5 10 15 20

Cu

rre

nt

(A)

Bias (V)

CAP-PL_Q1-.03_.03_1-AG16

3,0

6,0

3,-3

6,-3

3,-6

6,-6

0,-9

3,-9

6,-9

9,-9

0,-12

3,-12

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 5 10 15 20

Cu

rre

nt

(A)

Bias (V)

CAP-PL_Q1-.03_.035_10000-AG8

3,0

6,0

3,-3

6,-3

3,-6

6,-6

0,-9

3,-9

6,-9

9,-9

0,-12


B4

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 10 20 30 40 50

Cu

rre

nt

(A)

Bias (V)

CAP-PL_Q1-.03_.04_10000-AG10

3,0

6,0

3,-3

6,-3

3,-6

6,-6

0,-9

3,-9

6,-9

9,-9

0,-12

3,-12


C1

Appendix C

IScope.cs

using System;


using System.Text;

namespace WaferStepping

{

interface IScope

{

string IDN { get; }

bool Initialize();

bool Close();

void SetupChannel(int channel_nbr);

string FetchChannelData(int channel_nbr, out Double YScaleFactor, out Int16 YScaleOffset, out string

TimeStamp);

}

}

TDS6124C.cs

using System;


using System.Text;

using TekVISANet;

namespace WaferStepping

{

class TDS6124C:IScope

{

private bool detectsuccess;

private TekVISANet.VISA TVA = new TekVISANet.VISA();

private string response;

private bool status;

#region IScope Members

public string IDN

{

get

{

status = TVA.Write("*IDN?");



C2

return response;

}

}

public bool Initialize()

{

try

{

return true;

}

catch (Exception ex)

{

detectsuccess = false;

throw new Exception("Problem Initializing TDS6124C. Reason: " + ex.Message);

}

}

public bool Close()

{

try

{

TVA.Close();

return true;

}


{

throw new Exception("Problem closing connection with TDS6124C. Reason: " + ex.Message);

}

}

public void SetupChannel(int channel_nbr)

{

string response;

status = TVA.Write("DAT:SOUR CH" + Convert.ToString(channel_nbr));

status = TVA.Write("DAT:ENC RIB");

status = TVA.Write("WFMO:BYT_N 2");

status = TVA.Write("DAT:STAR 1");

status = TVA.Write("WFMO:NR_P?");

status = TVA.Read(out response); //--> nbpts

status = TVA.Write("DAT:STOP " + response);

}

public string FetchChannelData(int channel_nbr, out double YScaleFactor, out Int16 YScaleOffset, out string

TimeStamp)

{

Int16[] data;

string header, response;

byte[] output;

string csvdata;

status = TVA.Write("DAT:SOUR CH" + Convert.ToString(channel_nbr));

status = TVA.Write("HOR:FAST:TIMES:FRA:CH1? 1");


csvdata = "TimeStamp:," + response + "\r";

TimeStamp = response;


C3

status = TVA.Write("HOR:MAI:SAMPLER?");


csvdata += "Sample rate:," + response + ",Hz\r";

status = TVA.Write("CURV?");

status = TVA.ReadBinary(out output);

data = ConvertByteToInt16(output);

status = TVA.Write("WFMO:YMU?");

status = TVA.Read(out response); //--> Y axis scale factor in V/bitlevel

csvdata += "YScaleFactor:," + response + ",V/LSB\r";

try

{

YScaleFactor = Convert.ToDouble(response);

}

catch (System.FormatException e)

{

YScaleFactor = 1.0;

}

status = TVA.Write("WFMO:YOF?");

status = TVA.Read(out response); //--> Y axis offset in bit levels

csvdata += "YScaleOffset:," + response + "\r";

try

{

YScaleOffset = (Int16)Convert.ToDouble(response);

}

catch (System.FormatException e)

{

YScaleOffset = 0;

}

for (int i = 0; i < data.Length; i++)

{

csvdata += data[i].ToString() + "\r";

}

return csvdata;

}

#endregion

//function to convert binary data back to int16

public static Int16[] ConvertByteToInt16(byte[] array)

{

Int16[] int16Arr = new Int16[array.Length / 2];

for (int i = 0; i < int16Arr.Length; i++)

{

if (BitConverter.IsLittleEndian)

{

Array.Reverse(array, i * 2, 2);

}

int16Arr[i] = BitConverter.ToInt16(array, i * 2);

}

return int16Arr;

}

//function to convert binary data back to floats

public static float[] ConvertByteToFloat(byte[] array)

{

float[] floatArr = new float[array.Length / 4];


C4

for (int i = 0; i < floatArr.Length; i++)

{


{


}

floatArr[i] = BitConverter.ToSingle(array, i * 4);

}

return floatArr;

}

//function to convert binary data back to double

public static double[] ConvertByteToDouble(byte[] array)

{

double[] doubleArr = new double[array.Length / 8];

for (int i = 0; i < doubleArr.Length; i++)

{


{


}

doubleArr[i] = BitConverter.ToDouble(array, i * 8);

}

return doubleArr;

}

//Various constructors

public TDS6124C(string VISAResourceName, bool identify)

{

try

{

status = TVA.Open(VISAResourceName);

if (identify)

{

status = TVA.Write("*IDN?");


if (response.Contains("TEKTRONIX,TDS6124C"))

{

detectsuccess = true;

}

else

{

detectsuccess = false;

}

}

else

{

detectsuccess = true;

}

}


{

throw new Exception("Error while Initializing TDS6124C. Reason: " + ex.Message);

}

}


C5

}

}

Javier Pardo Garcia 2014/6/12 Master’s Thesis in...

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