ISPD 2001 - Resources, Verification W. Grobman Mask Making Design CD

ISPD 2001 - Resources, VerificationW. Grobman Mask Making

• Design CD << Wavelength• Variants of RET Pervasively Increasing• Design Size Is Explosive• GDS is an Inadequate PD Data Format

Consequently:• Mask Data Prep Resources Are a Big Cost Adder• PD to Si Equivalence Verification is A Major Issue• Mask Manufacturability Drives Cost/Cycle Time Issues

RETICLE ENHANCEMENT TECHNOLOGY IN THE SUBWAVELENGTH ERA

IMPLICATIONS FOR DESIGN TO SILICON


Tile

Behavioral & Logic Synthesis

Formal & Func. Verification

DFT, DFM, DFD, DFR

Noise, Power, Delay Extraction

Layout , Parasitics

Floorplanning , Place&RouteLibrary Creation

Mask Data

Reticle Mfg

Litho Process

Si Process

Si IC

Reticle

MaskPrep

OPC

Phase ShiftMethodology

Phase ShiftComplientRules

A (GDSII)

B (Post-RET GDSII)

Subwavelength RET: An Increasingly Important Post Tapeout Flow


RET Mini-Review


IndustryRoadmap

MotorolaRoadmap

Motorola Digital & RF Systems Roadmaps for Gate Length Extend Below Native Stepper Resolution

Motorola Digital & RF Systems Roadmaps for Gate Length Extend Below Native Stepper Resolution

Stepper Wavelength

Chart Courtesy of Numerical Technologies, Inc.


Summary - Reticle Enhancement Technology

Optical Proximity Correction (OPC)Add shapes to design data (GDS II)Corrects for litho optics & process

Rule based OPC - one mode fits all

Model-based OPC - customized to shape neighborhood

Phase-Shift“Strong” PSM - Phase mask + binary (“cut”) mask Used for gate printing CD, sheet rho, control

“Weak” PSM - Via clear areas include attenuator

TilingRule based tiling - Doesn’t guarantee global planarityModel-based tiling - POR for future reticles


No OPC

No OPC

With OPC

With OPC

MASKMASK WAFERWAFER

OPTICAL PROXIMITY CORRECTION IMPROVES PRINTING(ADDS SHAPES TO MASK)

OPTICAL PROXIMITY CORRECTION IMPROVES PRINTING(ADDS SHAPES TO MASK)

Photo downloaded from MicroUnity (now ASML MaskTools) web site


Rule-Based OPC

Fig.1A

Fig.1B


Phase-Shifting• Uses phase-modulation at the

mask level to further the resolution capabilities of optical lithography

• Benefits:– Smaller feature sizes

– Improved yield (process latitude)

– Dramatically extended useful life of current equipment

– Performance Boost

– Chip Area/Cost Advantage for Embedded Systems

Mask

180 o phase-shifter

0.11m

Printed using a ~0.18 m nominal process


Routing polyChrome Etch(phase plate)

180 Phase Etch(phase plate) Gate

Phase Shift - Simple Idea, Complex EDA Challenge

BinaryMaskClearArea

Legend: Grey= Opaque

Color= Clear


Rule-Based Tiling

+

• Done with Boolean operations• Only density of the template is variable• Not adequate for arbitrary design


Model-Based Tiling • Different amount of tiles at different locations• Uses Linear Programming and in-house software


Untiled reticle (768A)(unmanufacturable)

Conventional

Rule-Based Tiling (702A)(9% uniformity improvement)

Model-Based Tiling (152A)(80% uniformity improvement)

Model-Based Tiling - Large Manuafacturability Enhancement

193 nm ASML Stepper N.A. = 0.85!!!


Design Release Data Prep Resources• Computation Time• CPU Time• Storage Requirements

PD to Si Equivalence Verification• Design Changes AFTER DRC/LVS/Timing/Power

Mask Manufacturability

• Mask Fabrication Cycle Time & Cost

RET is Increasingly Driving New Issues


RET Methods Pervasively Expand as Technology Nodes Evolve“Prototypical” Scenario

Rule-based OPC

Model-based OPC

Scattering Bars

AA-PSM

Weak PSM

Rule-based Tiling

Optimization-driven MB Tiling

0.25 um 0.18 um 0.13 um 0.10 um 0.07 um

248 nm

248/193 nm

193 nm

Number Of Layers Increases / Generation


Rule-based OPC

Model-based OPC

Scattering Bars

AA-PSM

Weak PSM

Rule-based Tiling

Optimization-driven MB Tiling

0.25 um 0.18 um 0.13 um 0.10 um 0.07 um

Main Drivers of RET Issues

Data File Size, Computation Time, Mask Mfgbility

Design Constraints, Mask Mfgbility, Mfg Complexity

Computation Time, File Size, Timing/Power Reverification

248 nm

248/193 nm

193 nm


Mask Data Prep Resources Driven by RET

1

10

100

1000

1997 1998 1999 2000 2001

Year

Res

ou

rces

Data Size/Layer

# RET Layers

# CPU's

Hours

Gate Mask Production (Days)

RET RESOURCES BLOAT(1997=1)

# Layers

# CPU’s

MaskProduction(Days)

Hours/designData Size/Level

1000

100

10

1

1997 1998 1999 2000 2001(Est.)


Mask / Si Dimensions (Source: ITRS)

10

100

1000

1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014

Year

Dim

ensi

on

(n

m)

50

200

MPU Lpoly (nm)

Mask Min. Image

Mask OPC Feature


Mask Metrology Dimensions for RET ImplementationAre Significantly Smaller than Predicted by ITRS Roadmaps

10

100

1000

1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014

Year

Dim

ensi

on

(n

m)

MPU Lpoly (nm)

Mask Min. Image

Mask OPC Feature

50

200

ITRSMaskMin. FeatureAssumption

RET-DrivenMaskMin. Feature


• Reticle Delivery Cycle- Model-Driven Mask Inspection

• PD to Si Integrity- Model Si AND Mask Process- Use to Drive Si vs. PD Virtual Validation

• Intelligent OPC- ID Critical Design Features- Apply MB-OPC With Discrimination

• Use Parallel Processing- Recapture Hierarchy For Compaction and Functional Validation (e.g. Timing)

• Retain Design Data in PD Representation- GDS Replacement Open Standard

Solutions

RETICLE INSPECTION ISSUES Defectivity is the most serious problem affecting reticle delivery More acute with the introduction of OPC OPC features do not resolve as drawn in the design on reticle When inspected, OPC results in vast numbers of false defect detections Worst case (currently typical), the mask cannot be inspected at all Standard practice:

De-sense reticle inspection tool so partially resolved OPC shapes do not cause errors De-sensing for OPC also de-senses the tool to legitimate defects

Original Data with SerifsReticle Image on Inspection Tool

Overlay of sample design data (red), OPC data (yellow), and reticle image

on inspection tool (white)

From Kling, Lucas Motorola Patent

OPC RETICLE INSPECTION INNOVATIONS

Create a data set separate from the design to mimic shrinkage and rounding of OPC structures on reticle

The only change from written data is that OPC structures are altered for inspectability

The altered data set is presented to the inspection tool Essentially we are inspecting to an image that depicts the reticle as it is

expected to appear after exposure transformations and chemical processing

Original data with serifs Data with inspection shapesDatabase image with inspection

shapes on inspection toolReticle image on inspection tool

From Kling, Lucas Motorola Patent


No OPC

No OPC

With OPC

With OPC

PDPD

RET Must Incorporate Virtual Stepper ANDVirtual Maskwriter

RET Must Incorporate Virtual Stepper ANDVirtual Maskwriter

WAFERWAFERMASKMASK

WithMask-Model

Based OPC

WithMask-Model

Based OPC


Courtesy: Numerical Technologies, Inc.

Si ~ Layout - Separate Mask and Wafer Process ModelsImprove Manufacturability / Flexibility

Layout to SiCommon Today

Improve Mask InspectionFix Linearity Bias (Small vs. large feature) (Esp. bad at metal: xtalk, intralevel shorts… )Fix E-beam writer artifacts

MASK processmodel

= This Paper’s Suggested strategy


Tile

Behavioral & Logic Synthesis

Formal & Func. Verification

DFT, DFM, DFD, DFR

Noise, Power, Delay Extraction

Layout , Parasitics

Floorplanning , Place&RouteLibrary Creation

Mask Data

Reticle Mfg

Litho Process

Si Process

Si IC

Reticle

MaskPrep

OPC

Phase ShiftMethodology

Phase ShiftComplientRules

MODELS

A (GDSII)

B (Post-RET GDSII)

Model-Driven (MD) RET- MD Data Processing- MD Verification

Wafer Image SimulationLayout with OPC

OPC Verification Printed Wafer

Identify Critical Design FeaturesApply OPC With Discrimination & Verify Si=PD

Courtesy: Numerical Technologies

Proper Models -> Local Design Integrity


Critical -Requires MBOPC

Simply MustAvoid Pullback

44 Vertices

Intelligent MB-OPC is DesirableAdd Vertices Only for Manufacturability

e.g. Apply OPC With Discrimination

20 Vertices

Today

Better


Partitioning for Parallel Processing

Use Hierarchy (Library Cells) AND/OR Flatten and use explicit proximity effect range

(Global Wire / Custom)

Calculate OPC In Here

Keep Solution in Here


PROCESSING THROUGHPUT AND COST

Today’s Model Cluster

N-Way ProcessorShared MemoryFull-chipHours -> Days / Run~ $500K SystemNot Easily ScaleableConventional License Model

N Linux NodesDistributed MemoryLoose Multithreading (Optical / EM Effects are Short Range Compared to Compute Cell Size)Hours / Run~ N X $2000 SystemSimple to Scale

R E T

--> Need New License Model


Storage / Data Transmission “Explosion”It’s Desirable to Compress Data Post RET

MB-OPC Breaks Hierarchy

Recapture Hierarchy by One or Both of:

1. Hierarchical Data Incorporated in Design Shapes

• GDS Is an Interchange Format• Need Representation which Couples Physical with Other Design Attributes• Examples: SI2 Open Library API, Cadence Genesis

2. Use Pattern Extraction Heuristics to Identify Arrays of Shapes

• Can be Computationally Very Efficient - O(N) CPU time where N is the Number of Shapes • Available Now - Here’s a Quick Demo


Example: Pattern Extraction Heuristic to Regain Hierarchy Start With Flat Data File of Sequential Records,

Sort to Get Contiguous Records Of Same Shape, Different x,y Positions opcode1 x y Shape Attributes

opcode1 x y Shape Attributes

opcode1 x y Shape Attributes

Opcode-k x y Shape Attributes

x y Shape Attributes





Sort1 Sort2

.

.

.

.

Opcode-k

Opcode-k

Opcode-k

Opcode-L

Opcode-L


Example: Pattern Extraction Heuristic to Regain Hierarchy

2000 Random Points + 9 X 7 Array



After 1 Pass of Heuristic



After Second Pass of Heuristic


Post-Parallel Processing Compaction and Verification

• Pattern Recognition Heuristics Can Be Very Effective for Compaction

• This is Important for Efficient Data Delivery to Mask Shop

BUT

• Timing, Power, … Checking for Tiled Design Requires An Even Better Connection of PD Data to Design

• Global Nets May Need Timing Verification after Tiling

• Consequently, RET Could Drive Industry to More Quickly Adopt a New Standard Useful for PD Re-Timing After RET


Open Library API (OLA) - SI2


Rule-based OPCc:PSM

HierarchicalPD

HierarchicalPD

Si vs PD(mask and litho

models)

Workstation

•Smart MB-OPC•Tiling

Data Compaction

Mask Data Mask Inspect Data

Example RET Design Flow Scenario

Partitioned Flat PD for Parallel Computation(OLA-like PD Data Representation)

Flatten &Partition

ParallelProcessors

Timing/Power Verify

Create Mask Inspect Data


• RET Requires Models of New Types - Closer to Fabrication

• Accurate PD -> Mask -> Si Models•Drive Design Reverification•Drive Mask Inspect Data for Mask Cycle Reduction

• Parallel Computation Can Shrink Compute Resources

• Recapture of Hierarchy Shrinks Data Size

• Recapture of Design Structure Drives Global Timing Verification

Robust, Implementable RET Design Requires New Paradigms

ISPD 2001 - Resources, Verification W. Grobman Mask Making Design CD

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