Impact of RET on Physical Design ISPD 2001 April 2, 2001

Impact of RET on Physical Design

ISPD 2001April 2, 2001

F.M. Schellenberg, Ph.D.Calibre RET Group

Luigi Capodieci, Ph.D.ASML MaskTools

F.M. Schellenberg / ISPD 2001 / April 2, 20012

Agenda Agenda Resolution Enhancement Technology (RET)

– Lithography Basics– RET: OAI, OPC, PSM, and all that

Insertion in Process Flows Impact on Physical Design

– OAI– OPC– PSM

Importance of a “Target” layer Conclusions


Lithography Basics

All IC layers are formed by Lithography

The light interacts with a reticle (aka mask) and the lens to form a reduced image in photoresist

Illumination

Mask

Lens

Wafer

4

100

UV Laser


Lithography Basics

• High spatial frequencies (dense lines) scatter at larger angles.

• The lens acts as a low-pass filter for high spatial frequencies


Lithography Basics

Fine pitches diffract at higher angles The lens acts recollects light onto the wafer The lens acts like a low pass filter “DC” light passes directly through the lens

– No contrast– No image– Wasted light


The light interacting with the mask is a wave Any wave has certain fundamental properties

– Wavelength ()– Direction– Amplitude– Phase

RET is wavefront engineering to enhance lithographyby controlling these properties

Lithography Basics

-4

-3

-2

-1

0

1

2

3

4

-20 0 20 40 60 80 100

B

Amplitude

Direction

Phase


Wavefront Engineering: Direction

-4

-3

-2

-1

0

1

2

3

4

-20 0 20 40 60 80 100

B

Amplitude

Direction

Phase



Regular Illumination: Uniform disc Off-Axis Illumination: e.g. Annular

lensLensLens



Many off-axis designs

– Annular

– Quadrupole / Quasar

– Dipole

See your local stepper/scanner supplier+

or


Wavefront Engineering: Amplitude

-4

-3

-2

-1

0

1

2

3

4

-20 0 20 40 60 80 100

B

Amplitude

Direction

Phase


Wavefront Engineering: OPC

Optical and Process Correction (OPC)for Amplitude Control

Modifies layout to compensate for process distortions– Add light where needed– Subtract light where not wanted– Add non-electrical structures to layout to

control diffraction of light


Wavefront Engineering: OPC

Mask layout Wafer result


Wavefront Engineering: Phase

-4

-3

-2

-1

0

1

2

3

4

-20 0 20 40 60 80 100

B

Amplitude

Direction

Phase


Wavefront Engineering: PSM

Phase Shifting Masks (PSM)

Etch topography into mask– Creates interference fringes on the wafer– Interference fringes can be extremely small

Make mask material phase shifting– “Attenuated” PSM



NAL

25.0

For conventional steppers:248 nm, NA=0.63

L 98 nm

Mask



Interference effects boost contrast

Phase Masks can make extremely small gates

Phase Masks can double resolution– 2X finer pitches

0° 180°

90 nm

SEM image courtesy of IMEC


So What?

RET not done in isolation

Selection of RET technique carries an impact on design rules / layout restrictions


Insertion points of RET

OAI: – Inserted into Lithography Stepper

OPC– Typically inserted at Physical Verification

Verification modified to include process simulation

PSM– Modify P&R rules to allow finer pitches– Insert at P&R , Physical Verification, or Mask

Data Preparation


Impact on Physical Design

OAI

OPC

PSM


Impact on Physical Design: OAI

Off axis amplifies certain pitches at the expense of the others.

Concept of “Forbidden” pitches

100 150 200 250 300 350 400

QuadrupoleConventional

Half Pitch (nm)Half Pitch (nm)

Depth of Focus (a.u.)

Graph reference: Noguchi, M. et al. “Subhalf Micron Lithography System with Phase Shifting Effect”, in Optical/Laser Microlithography V, Proc. SPIE Vol. 1674 (1992), 92-104.

Quadrupole Illumination



Graph reference: Socha et al. “Forbidden Pitches for 130 nm lithography and below”, in Optical Microlithography XIII, Proc. SPIE Vol. 4000 (2000), 1140-1155.

0

0.5

1

1.5

200 400 600 800 1000 1200 1400

Without SRAF

AcceptableUnacceptable

Depth of Focus (m)

Pitch (nm)

130 nm lines, printed at different pitches

Quasar illuminationNA=0.7

Iso

late

d

De

nseQuasar

Illumination



45° lines vanish

110 nm linesQuasar illumination NA=0.7

Isolated Dense

QuasarIllumination



Quasar / Quadrupole Illumination – Amplifies dense 0°, 90 ° lines– Destroys ±45° lines

Dipole Illumination– Horizontal Dipole prints only Vertical Lines– Vertical Dipole prints only Horizontal lines– Must decompose layout for 2 exposures

Vertical mask, horizontal mask



OAI

OPC

PSM


Impact on Physical Design: OPC

OPC changes layout dramatically

OPC does not change design



Designed Layout

Final Layout

Mask

Wafer



Original Designed Layout Layout with OPCGraphics courtesy of IBM



SEM image courtesy of IBM



Graphics & SEM image courtesy of IBM Simulation based check



OPC provides an automatic layout fix to achieve the target layer on the wafer

With simulation based checking, design rules can be more aggressive

Physical Verification becomes process-aware – Expands to add OPC – Verifies the results with process simulation



OAI

OPC

PSM


Impact on Physical Design: PSM

PSM allows true resolution enhancement– Thin gates 90 nm wide in 180 nm process– Pitch doubling

Line size / pitch defined in – Libraries– Routing algorithms

Drives insertion to P&R

90 nm

SEM image courtesy of IMEC



Maskmaking concerns for PSM– Phase etch effects: linewidth imbalance – No inspection technique– No repair technique– Desire to minimize final phase area

Drives phase assignment to the last possible moment



Best compromise:– Phase compliant Libraries, design rules

Phase assignment done at Verification– Allows PSM with OPC to be verified together– Verification includes mask manufacturing

rules (e.g. imbalance).


All RET make major changes to the layout

The “design” remains unchanged

Main consequence of RET:– Divorce between Design and Layout




“Target” Layer


“Target” Layer

All RET packages have one common assumption:

– The layout presented is the desired structure for the wafer

In practice, this is NOT true.


“Target” Layer

Design Rules have evolved to “make things work”

These include compensations for physical phenomena (pre OPC)

The phenomena ebb and flow with process; The rule remains as long as things work With OPC, things may no longer work

– The rules need to be reexamined


Example: Historical rule on line extension

OPC software assumes the layout is the target, and adds OPC to the old OPC extension

“Target” Layer

Truly desired on wafer Layout according to design rule

OPC on the OPC


“Target” Layer: SRAM Example


“Target” Layer: Example of Embedded OPC LI Design

Hand Applied OPC:A = 240nmB = 255nmC = 270nm

Bit Cell

Slide courtesy of LSI Logic


“Target” Layer: Poly Layer De-OPC Rule Deck

Generic De-OPC Rule

// input layers are uppercaseLAYER NISLAND_LAYOUT 2 //nisland -original inputLAYER PISLAND_LAYOUT 3 //pisland -original inputLAYER POLY_LAYOUT 4 //poly -original inputLAYER CONTACT 5 35

island = Or NISLAND_LAYOUT PISLAND_LAYOUT islandCE = Coincident Edge island endcap1 islandCEa = Length islandCE > 0.15 gate = And POLY_LAYOUT island gate1 = Size gate By -0.08 gate2 = Size gate1 By 0.08 endcap1 = Not POLY_LAYOUT gate2 endcap2 = Not Enclose endcap1 CONTACT endcap2a = Area endcap2 < 0.15 endcap3 = With Edge endcap2a islandCE == 1 endcap4 = With Edge endcap3 islandCEa realEndCap = vertex endcap4 > 4

'endcap_flag_fix' { poly = Not POLY_LAYOUT realEndCap islandCEb = Coincident Inside Edge poly island Expand Edge islandCEb Outside By 0.15 }

OPC Free Cell



“Target” Layer Plan: De-OPC on Bit Cells

Memory

I/O

Analog

Mixed Signal

Etc.

Cell Libraries

De-OPC

MemoryAnalog

I/O

Mixed Signal

Tape Out

De-OPC

De-OPC

De-OPC

De-OPC

OPC FreeCell Libraries

Memory

I/O

Analog

Mixed Signal

Etc.

Compiler “Target” Layout

DRC/LVS

Process-based OPC



“Target” Layer Conclusion

Design rules are riddled with historical OPC DON’T DO THAT! With systematic OPC now part of the flow,

it will do the heavy lifting Consciously clean up libraries and design

rules to create the actual “target” layout If this is not done,

mysterious failures will continue


Conclusions

Selection of RET is mandatory for future progress down Moore’s Law– It’s not going away

RET style has an impact on layout– Design and layout become very different

Design to a “Target” layer– Produce a layout that shows what is really desired

– Allow RET to do its job


Acknowledgements

Emile Sahouria, Olivier Toublan Mentor Graphics

Bob Socha, ASML Lars Liebmann, IBM George Bailey, LSI Logic Kurt Ronse, IMEC


Thank you for your attention.


www.mentor.com

Impact of RET on Physical Design ISPD 2001 April 2, 2001

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