ISIS and SPiDeR Zhige ZHANG STFC Rutherford Appleton Laboratory.
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Transcript of ISIS and SPiDeR Zhige ZHANG STFC Rutherford Appleton Laboratory.
ISIS and SPiDeR
Zhige ZHANG
STFC Rutherford Appleton Laboratory
Content
• ISIS Concept– ISIS1
• ISIS2 – Design– test structure– ISIS2 So far
• SPiDeR – Project– Sensors
Z Zhang Vertex 2009 Putten2
ISIS Concept
• In-situ Storage Image Sensor• Parallel sampling for all the pixels• Store the raw charge locally ( next to the
pixels)• Read out later• Fast frame rate but limited number of frames • Burst events such as ILC bunch train
Z Zhang Vertex 2009 Putten3
Image sensor
• ISIS has been used in image sensor for high speed camera– Frames rate: 106 Frames/Second– Sensor size: 312x260– Frames storage: 103 frames
ETOH et al. IEEETRANS ELECTRON DEVICES, 50, (2003) pp 144-151
Z Zhang Vertex 2009 Putten4
ISIS1 • Test of concept
– 16 X 16 image pixels– 5 storage cells
– CCD process– Pixel size 160 X 40 µm
Z Zhang Vertex 2009 Putten5
p+ shielding implant
n+
buried channel (n)
Charge collection reflected charge
High resistivity epitaxial layer (p)
Sense node (n+) row selectreset
gateVDD
Photogatetransfer
gate
Output gate to column
load
Storage cell #1 - 5
substrate (p++)
Isolation gate
ISIS1
Z Zhang Vertex 2009 Putten6
0
10
20
30
40
50
60
70
0 5 10 15 20 25 30
VPG (V)
RPS
(b)
(c)
(a)
Zhang et al Nucl. Instr. and Meth. A 607 (2009) pp 538-543
• Deep p-well charge shielding on storage pixels
• Ratio of x-ray events on photo gate and storage cells– (a) without – (b) with (GV = 4V)– (c) with (GV = 8V)
• Deep p-well works
ISIS2
• Second generation of ISIS • Miniature design 20X20 µm2 pixel
size:• 0.18 µm CMOS process • non–overlapping gates • Deep p-well for charge shielding
Z Zhang Vertex 2009 Putten7
ISIS2 Cross Section
Z Zhang Vertex 2009 Putten8
• p+ shielding implant
• Charge injector
• buried channel (n)
• Charge collection
• p+ well
• reflected charge
• reflected charge• High resistivity epitaxial layer
(p)
• Storage • pixel #1-
20
• Sense
node
(n+)
• Row select
• Reset gate
• Source follower
• V
D
D
• Photo
• gate
• Reset transist
or
• Row select transistor
• Output
• gate
• Output
• substrate (p+)
Summinggate
ISIS2
• Test structure– Small version of one pixel– Photo, Summing and Output
gate – Readout electronics
• Allows test of basic functionality– Charge transfer – Readout– Fringe effect
Z Zhang Vertex 2009 Putten9
IDR IG PG SG OG RG RD OD RSEL
M0
OS
SS
ISIS2 test structure
ISIS2
• Low noise on readout electronics– Measure the x-ray
events on the output node
– 5.5 e- (STD) with CDS (800ns)
– Clear 55Fe Kb peak
– 1620/145 = 11.17 e-/ADC
– 24 µV/e-
Z Zhang Vertex 2009 Putten10
55Fe Ka
55Fe Kb
ISIS2 • High resistance on
the gate • Examined by
connecting test structure as a ‘big’ transistor
• 100 Hz applied to gate yellow line
• Green line is the output
• However the test structure can be controlled by slow clocking
Z Zhang Vertex 2009 Putten11
Charge capacity
Z Zhang Vertex 2009 Putten12
• Pixel size 1X5 µm• Gate voltage = 3.5V• Charge capacity
inside linear part – ~5500 e- @ -10 ⁰C– ~7500 e- @ 0 ⁰C– ~9500 e- @ 10 ⁰C– Close to the design
0 5 10 15 20 250
2000
4000
6000
8000
10000
12000
14000
16000
Charge Capacity vs gate voltage 1X5 µm @0 C ⁰
SG=3.5v
SG=3.75
SG=4V
LED duration (µs) for inject charge
e-
ISIS2 Dark Current
• Dark current collected under the 1x5 µm2
• Temperature range -10 to 20 C⁰
• Unit: e- / ms • Isolated pixel only • A guidance for the
testing
Z Zhang Vertex 2009 Putten13
-10 -5 0 5 10 15 200
2
4
6
8
10
12
14
16
18
Dark Current vs Temperature1x5 µm2
Temperature C⁰
e-
/ ms
ISIS2 Fringe Effect• Potential under the
output gate is pulled up by output node(5V)
• Charge leaked to output node directly from photo gate
• -0.2 V is the best setting for this device
• Several ways to modify the design
Z Zhang Vertex 2009 Putten14
-0.4 -0.2 0 0.2 0.4 0.6 0.8 10
100
200
300
400
500
600
Charge-hold PG vsSG
PGSG
OG(V)
Ou
tpu
t m
v
ISIS2 main array
Z Zhang Vertex 2009 Putten15
One pixel
Whole sensor
• 20 storage cells buried channel CCD
• Pixel size 80x10/20x40 µm2
• Storage cell charge capacity > 6ke-
• 256x32 pixels
ISIS2 55Fe events on main array
• Beginning of the study on main array
• Challenges– Slow clocking – Dark current – Charge transfer
Z Zhang Vertex 2009 Putten16
Y Li Oxford
SPiDeR• Silicon Pixel Detector R&D• Continue and extend the sensor development in
previous projects (CALICE and LCFI)– Goal: further develop monolithic silicon active pixel
detectors • Vertexing, tracking and electromagnetic calorimetry
• The sensors include– TPAC (CALICE) – CHERWELL
• ISIS (LCFI) (Charge Coupled CMOS)• FORTIS
– a demonstrator device for 4T (pinned photodiode) technology
• Digital Calorimeter test stack
Z Zhang Vertex 2009 Putten17
TPAC
Z Zhang Vertex 2009 Putten18
Tera-Pixel Active Calorimeter , it has per-pixel peramp,thresholding and
timestamp capability
TPAC stack behindtestbeam CERN 13-28 Aug
19Z Zhang Vertex 2009 Putten
FORTIS in testbeam testbeam CERN 13-28 Aug, Fortis sanwichedbetween elements of the EUDET Si telescope
Z Zhang Vertex 2009 Putten20
Hits on FORTIS testbeam CERN 13-28 Aug
21Z Zhang Vertex 2009 Putten
Z Zhang Vertex 2009 Putten22
Thanks