ISE in-Depth Tuturial

8/8/2019 ISE in-Depth Tuturial

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ISE In-Depth Tutorial www.xilinx.com UG695 (v 12.1) April 19, 2010

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6 www.xilinx.com ISE In-Depth TutorialUG695 (v 12.1) April 19, 2010

Saving the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Behavioral Simulation Using ISim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Locating the Simulation Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Specifying Simulation Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Adding Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Rerunning Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Analyzing the Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Chapter 5: Design Implementation

Overview of Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Getting Started. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Continuing from Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Starting from Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Specifying Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Creating Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Translating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Using the Constraints Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Assigning I/O Locations Using PlanAhead Software . . . . . . . . . . . . . . . . . . . . . . . . 105

Mapping the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Using Timing Analysis to Evaluate Block Delays After Mapping. . . . . . . . . . . . 110Estimating Timing Goals with the 50/50 Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Reviewing the Post-Map Static Timing Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Placing and Routing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Using FPGA Editor to Verify the Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Evaluating Post-Layout Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Viewing the Post-Place and Route Static Timing Report . . . . . . . . . . . . . . . . . . . . . . . 115Analyzing the Design using the PlanAhead Software . . . . . . . . . . . . . . . . . . . . . . . . . 116

Creating Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Creating a PROM File with iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Command Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Chapter 6: Timing Simulation

Overview of Timing Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Getting Started. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Required Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Required Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Specifying a Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Timing Simulation Using ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Specifying Simulation Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Adding Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125Adding Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127Rerunning Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Analyzing the Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Saving the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Timing Simulation Using Xilinx ISim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Specifying Simulation Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130


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12 www.xilinx.com ISE In-Depth TutorialUG695 (v12.1) April 19, 2010

Chapter 1: Overview of ISE Software

The following figure shows the Project Navigator interface.

Design Panel

The Design panel provides access to the View, Hierarchy, and Processes panes.

View Pane

The View pane radio buttons enable you to view the source modules associated with theImplementation or Simulation Design View in the Hierarchy pane. If you selectSimulation, you must select a simulation phase from the drop-down list.

Hierarchy Pane

The Hierarchy pane displays the project name, the target device, user documents, anddesign source files associated with the selected Design View. The View pane at the top ofthe Design panel allows you to view only those source files associated with the selectedDesign View, such as Implementation or Simulation.

Each file in the Hierarchy pane has an associated icon. The icon indicates the file type(HDL file, schematic, core, or text file, for example). For a complete list of possible source

X-RefTarget - Figure 1-1

Figure 1-1: Project Navigator


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Using Project Revision Management Features

Messaging features such as message filtering, tagging, and incremental messaging are alsoavailable from this view.

Using Project Revision Management Features

Project Navigator enables you to manage your project as follows.

Understanding the ISE Project File

The ISE project file (.xise extension) is an XML file that contains all source-relevant data forthe project as follows:

ISE software version information

List of source files contained in the project

Source settings, including design and process properties

The ISE project file does not contain the following:

Process status information

Command history Constraints data

Note: A .gise file also exists, which contains generated data, such as process status. You should not

need to directly interact with this file.

The ISE project file includes the following characteristics, which are compatible withsource control environments:

Contains all of the necessary source settings and input data for the project.

Can be opened in Project Navigator in a read-only state.

Only updated or modified if a source-level change is made to the project.

Can be kept in a directory separate from the generated output directory (working

directory).Note: A source-level change is a change to a property or the addition or removal of a source file.

Changes to the contents of a source file or changes to the state of an implementation run are not

considered source-level changes and do not result in an update to the project file.

Making a Copy of a Project

You can create a copy of a project using File > Copy Project to experiment with differentsource options and implementations. Depending on your needs, the design source files forthe copied project and their location can vary as follows:

Design source files can be left in their existing location, and the copied project pointsto these files.

Design source files, including generated files, can be copied and placed in a specifieddirectory.

Design source files, excluding generated files, can be copied and placed in a specifieddirectory.


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Chapter 2: HDL-Based Design

Optional Software Requirements

The following third-party synthesis tools are incorporated into this tutorial and may beused in place of Xilinx Synthesis Technology (XST):

Synopsys Synplify/Synplify Pro D-2010.03 (or above)

Mentor Precision Synthesis 2010a (or above)

The following third-party simulation tool is optional for this tutorial and may be used inplace of ISim:

ModelSim XE/SE/PE/DE 6.5c (or above)

VHDL or Verilog

This tutorial supports both VHDL and Verilog designs and applies to both designssimultaneously, noting differences where applicable. You will need to decide which HDLlanguage you would like to work through for the tutorial and download the appropriatefiles for that language. XST can synthesize a mixed-language design. However, thistutorial does not cover the mixed language feature.

Installing the Tutorial Project Files

The tutorial project files are provided with the ISE Design Suite 12 Tutorials available fromthe Xilinx website. Download either the VHDL or the Verilog design flow project files.

After you have downloaded the tutorial project files from the web, unzip the tutorialprojects into the c:\xilinx\12.1\ISE_DS\ISE\ISEexamples directory, replacingany existing files in that directory.

When you unzip the tutorial project files intoc:\xilinx\12.1\ISE_DS\ISE\ISEexamples , the directorywtut_vhd (for a VHDLdesign flow) orwtut_ver (for a Verilog design flow) is created withinc:\xilinx\12.1\ISE\ISEexamples , and the tutorial files are copied into the newly-

created directory.

The following table lists the locations of tutorial source files.

Note: The completed directories contain the finished HDL source files. Do not overwrite any files inthe completed directories.

This tutorial assumes that the files are unzipped underc:\xilinx\12.1\ISE_DS\ISE\ISEexamples , but you can unzip the source files intoany directory with read/write permissions. If you unzip the files into a different location,substitute your project path in the procedures that follow.

Table 2-1: Tutorial Directories

Directory Description

wtut_vhd Incomplete VHDL Source Files

wtut_ver Incomplete Verilog Source Files

wtut_vhd\wtut_vhd_completed Completed VHDL Source Files

wtut_ver\wtut_ver_completed Completed Verilog Source Files
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dcm1

Clocking Wizard macro with internal feedback, frequency controlled output, andduty-cycle correction. The CLKFX_OUT output converts the 50 MHz clock of theSpartan-3A demo board to 26.2144 MHz.

debounce

Schematic module implementing a simplistic debounce circuit for the strtstop, mode,and lap_load input signals.

lcd_control

Module controlling the initialization of and output to the LCD display.

statmach

State machine HDL module that controls the state of the stopwatch.

timer_preset

CORE Generator software 64x20 ROM. This macro contains 64 preset times from0:00:00 to 9:59:99 that can be loaded into the timer.

time_cnt

Up/down counter module that counts between 0:00:00 to 9:59:99 decimal. This macrohas five 4-bit outputs, which represent the digits of the stopwatch time.

Design Entry

For this hierarchical design, you will examine HDL files, correct syntax errors, create anHDL macro, and add a CORE Generator software core and a clocking module. You willcreate and use each type of design macro. All procedures used in the tutorial can be usedlater for your own designs.

Adding Source Files

HDL files must be added to the project before they can be synthesized. You will add fivesource files to the project as follows:

1. Select Project > Add Source.

2. Select the following files (.vhd files for VHDL design entry or .v files for Verilog designentry) from the project directory, and click Open.

clk_div_262k

lcd_control

statmach

stopwatch

time_cnt

3. In the Adding Source Files dialog box, verify that the files are associated with All, thatthe associated library is work, and click OK.

The Hierarchy pane in the Design panel displays all of the source files currently added tothe project, with the associated entity or module names. Each source design unit isrepresented in the Hierarchy pane using the following syntax: instance name - entity name -architecture name - (file name).


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Design Entry

Instantiated components with no entity or module declaration are displayed with aquestion mark.

Correcting HDL Errors

The syntactical correctness of the files is checked as the files are added to the project, andalso when they are saved. Messages are posted in the Console and in the Parser Messages

section of the Design Summary and indicate the success or failure as each of the files isparsed.

The time_cnt module contains a syntax error that must be corrected. An ERRORmessage in the Console indicates the failure and provides a summary and the line numberof the syntax problem.

To display the error in the source file, do the following:

1. In the Console or Errors panel, click the file name in the error message.

The source code appears in the Workspace with a yellow arrow icon next to the linewith the error.

2. Correct any errors in the HDL source file. The comments above the error explain this

simple fix.3. Select File > Save to save the file.

The parsing message in the Console should now indicate that the file was checkedsuccessfully and is now free of errors.

Creating an HDL-Based Module

Next you will create a module from HDL code. With the ISE software, you can easily createmodules from HDL code using the ISE Text Editor. The HDL code is then connected toyour top-level HDL design through instantiation and is compiled with the rest of thedesign.

You will author a new HDL module. This macro will be used to debounce the strtstop,mode and lap_load inputs.


Figure 2-4: Hierarchy Panel Showing Completed Design


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Design Entry

c. Leave the Bus designation boxes unchecked.

6. Click Next to view a description of the module.

7. Click Finish to open the empty HDL file in the ISE Text Editor.

Following is an example VHDL file.


Figure 2-6: New Source WizardDefine Module Page


Figure 2-7: VHDL File in ISE Text Editor


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Following is an example Verilog file.

In the ISE Text Editor, the ports are already declared in the HDL file, and some of the basicfile structure is already in place. Keywords are displayed in blue, comments in green, andvalues are black. The file is color-coded to enhance readability and help you recognizetypographical errors.

Using the Language Templates

The ISE Language Templates include HDL constructs and synthesis templates, whichrepresent commonly used logic components, such as counters, D flip-flops, multiplexers,

and primitives. You will use the Debounce Circuit template for this exercise.

Note: You can add your own templates to the Language Templates for components or constructs

that you use often.

To invoke the Language Templates and select the template for this tutorial, do thefollowing:

1. From Project Navigator, select Edit>Language Templates.

Each HDL language in the Language Templates is divided into five sections: CommonConstructs, Device Macro Instantiation, Device Primitive Instantiation, SimulationConstructs, Synthesis Constructs and User Templates. To expand the view of any ofthese sections, click the plus symbol (+) next to the section. Click any of the listedtemplates to view the template contents in the right pane.

2. Under either the VHDL or Verilog hierarchy, expand Synthesis Constructs, expandCoding Examples, expand Misc, and select the template called Debounce Circuit orOne Shot, Debounce Circuit. Use the appropriate template for the language you areusing.


Figure 2-8: Verilog File in ISE Text Editor


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Design Entry

Upon selection, the HDL code for a debounce circuit is displayed in the right pane.

Adding a Language Template to a File

You will now use the Use in File method for adding templates to your HDL file. Refer toWorking with Language Templates in the ISE Help for additional usability options,including drag and drop options.

To add the template to your HDL file, do the following:

1. With the debounce.v or debounce.vhd source file active, position the cursorunder the architecture begin statement in the VHDL file, or under the module and pindeclarations in the Verilog file.

2. Return to the Language Templates window, right-click on the Debounce Circuittemplate in the template index, and select Use In File.

3. Close the Language Templates window.


Figure 2-9: Language Templates


Figure 2-10: Selecting Language Template to Use in File


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4. Open the debounce.v or debounce.vhd source file to verify that the LanguageTemplate was properly inserted.

5. Verilog only: Complete the Verilog module by doing the following:

a. Remove the reset logic (not used in this design) by deleting the three linesbeginning with if and ending with else.

b. Change

toq

in all six locations.c. Change to clk; to sig_in; and to sig_out.

Note: You can select Edit > Find & Replace to facilitate this. The Find fields appear at the

bottom of the Text Editor.

6. VHDL only: Complete the VHDL module by doing the following:

a. Move the line beginning with the word signalso that it is between thearchitectureandbeginkeywords.

b. Remove the reset logic (not used in this design) by deleting the five lines beginningwith if (... and ending with else, and delete one of the end if;lines.

c. Change to clk; D_IN to sig_in; and Q_OUT to sig_out.

Note: You can select Edit > Find & Replace to facilitate this. The Find fields appear at thebottom of the Text Editor.

7. Save the file by selecting File>Save.

8. Select one of the debounce instances in the Hierarchy pane.

9. In the Processes pane, double-click Check Syntax. Verify that the syntax check passessuccessfully. Correct any errors as necessary.

10. Close the ISE Text Editor.

Creating a CORE Generator Software Module

The CORE Generator software is a graphical interactive design tool that enables you to

create high-level modules such as memory elements, math functions and communications,and I/O interface cores. You can customize and pre-optimize the modules to takeadvantage of the inherent architectural features of the Xilinx FPGA architectures, such asFast Carry Logic, SRL16s, and distributed and block RAM.

In this section, you will create a CORE Generator software module called timer_preset.The module will be used to store a set of 64 values to load into the timer.

Creating the timer_preset CORE Generator Software Module

To create a CORE Generator software module, do the following:

1. In Project Navigator, select Project>New Source.

2. Select IP (CORE Generator & Architecture Wizard).

3. In the File Name field, enter timer_preset.

4. Click Next.

5. Expand the IP tree selector to locate Memories & Storage Elements >RAMs &ROMs.


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Design Entry

6. Select Distributed Memory Generator, clickNext, and click Finish to open theDistributed Memory Generator customization GUI. This customization GUI enablesyou to customize the memory to the design specifications.

7. Fill in the Distributed Memory Generator customization GUI with the followingsettings:

Component Name: timer_preset(defines the name of the module)

Depth: 64 (defines the number of values to be stored)

Data Width: 20(defines the width of the output bus)

Memory Type: ROM


Figure 2-11: New Source WizardSelect IP Page


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8. Click Next.

9. Leave Input and Output options as Non Registered, and click Next.

10. To specify the Coefficients File, click the Browse button, and selectdefinition1_times.coe located in the project directory.


Figure 2-12: CORE Generator SoftwareDistributed Memory GeneratorCustomization GUI Page 1




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Design Entry

11. Check that only the following pins are used (used pins are highlighted on the symbolon the left side of the customization GUI):

a[5:0]

spo[19:0]

12. Click Generate.

The module is created and automatically added to the project library.

A number of files are added to the ipcore_dir sub-directory of the project directory.Following is a list of some of these files:

timer_preset.vhoor timer_preset.veo

These are the instantiation templates used to incorporate the CORE Generatorsoftware module into your source HDL.

timer_preset.vhd or timer_preset.v

These are HDL wrapper files for the core and are used only for simulation.

timer_preset.ngc

This file is the netlist that is used during the Translate phase of implementation.

timer_preset.xco

This file stores the configuration information for the timer_preset module and isused as the project source in the ISE project.

timer_preset.mif

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Instantiating the CORE Generator Software Module in the HDL Code

Next, instantiate the CORE Generator software module in the HDL code using either aVHDL flow or a Verilog flow.

VHDL Flow

To instantiate the CORE Generator software module using a VHDL flow, do the following:1. In Project Navigator, double-click stopwatch.vhd to open the file in ISE Text Editor.

2. Place the cursor after the following line:

-- Insert CORE Generator ROM component declaration here

3. Select Edit > Insert File, then select ipcore_dir/timer_preset.vho , and clickOpen.

The VHDL template file for the CORE Generator software instantiation is inserted.

4. Highlight the inserted code from:

-- Begin Cut here for INSTANTIATION Template ----

to

--INST_TAG_END ------ END INSTANTIATION Template -----

5. Select Edit> Cut.

6. Place the cursor after the following line:

--Insert CORE Generator ROM Instantiation here

7. Select Edit> Paste to place the core instantiation.

8. Change the instance name from your_instance_name to t_preset.

9. Edit this instantiated code to connect the signals in the stopwatch design to the ports ofthe CORE Generator software module as shown below.

10. The inserted code of timer_preset.vho contains several lines of commented textfor instruction and legal documentation. Delete these commented lines if desired.

11. Save the design using File> Save, and close the ISE Text Editor.


Figure 2-15: VHDL Component Declaration for CORE Generator Software Module


Figure 2-16: VHDL Component Instantiation of CORE Generator Software Module


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4. In the Select IP dialog box, select FPGA Features and Design> Clocking>Spartan-3E, Spartan-3A >Single DCM_SP.

5. Click Next, and click Finish. The Clocking Wizard is launched.

6. In the Architecture Wizard Setup page, select OK.

7. In the General Setup page, verify that RST, CLK0 and LOCKED ports are selected.

8. Select CLKFX port.

9. Enter 50 and select MHz for the Input Clock Frequency.

10. Verify the following settings: Phase Shift: NONE

CLKIN Source: External, Single

Feedback Source: Internal

Feedback Value: 1X

Use Duty Cycle Correction: Selected

11. Click the Advanced button.

12. Select Wait for DCM lock before DONE Signal goes high.

13. Click OK.

14. Click Next, and then click Next again.

15. Select Use output frequency and enter 26.2144 in the box and select MHz.

16. Click Next, and then click Finish.

Thedcm1.xaw file is added to the list of project source files in the Hierarchy pane of theDesign panel.


Figure 2-18: Selecting Single DCM_SP IP Type

26.2144Mhz( ) 218

100Hz=


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Design Entry

Instantiating the dcm1 MacroVHDL Design

Next, you will instantiate the dcm1 macro for your VHDL or Verilog design. To instantiatethe dcm1 macro for the VHDL design, do the following:

1. In the Hierarchy pane of the Project Navigator Design panel, select dcm1.xaw.

2. In the Processes pane, right-click View HDL Instantiation Template, and select

Process Properties.

3. Choose VHDL for the HDL Instantiation Template Target Language value, and clickOK.

4. In the Processes pane, double-click View HDL Instantiation Template.

5. Highlight the component declaration template in the newly opened HDL InstantiationTemplate (dcm1.vhi) shown below.

6. Select Edit>Copy.

7. Place the cursor in the following section of the stopwatch.vhd file:

-- Insert dcm1 component declaration here.

8. Select Edit > Paste to paste the component declaration.

9. Highlight the instantiation template in the newly opened HDL Instantiation Templateshown below.

10. Select Edit>Copy.

11. Place the cursor below the following line in the stopwatch.vhd file:

-- Insert dcm1 instantiation here.

12. Select Edit > Paste to paste the instantiation template.


Figure 2-19: VHDL DCM Component Declaration


Figure 2-20: VHDL DCM Component Instantiation


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13. Make the necessary changes as shown in the following figure.

14. Select File>Save to save the stopwatch.vhd file.

The dcm1 module should now appear beneath the stopwatch module in the designhierarchy.

Instantiating the dcm1 MacroVerilog

To instantiate the dcm1 macro for your Verilog design, do the following:

1. In the Hierarchy pane of the Project Navigator Design panel, select dcm1.xaw.

2. In the Processes pane, double-click View HDL Instantiation Template.

3. From the newly opened HDL Instantiation Template (dcm1.tfi), copy theinstantiation template shown below.

4. Paste the instantiation template into the following section in the stopwatch.v file:

//Insert dcm1 instantiation here.

5. Make the necessary changes as shown in the following figure.

6. Select File>Save to save the stopwatch.v file.

The dcm1 module should now appear beneath the stopwatch module in the designhierarchy.


Figure 2-21: VHDL Instantiation for dcm1


Figure 2-22: dcm1 Macro and Instantiation Templates


Figure 2-23: Verilog Instantiation for dcm1


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Synthesizing the Design


So far you have been using Xilinx Synthesis Technology (XST) for syntax checking. Next,you will synthesize the design using either XST, Synplify/Synplify Pro, or Precisionsoftware. The synthesis tool uses the designs HDL code and generates a supported netlisttype (EDIF or NGC) for the Xilinx implementation tools. The synthesis tool performs the

following general steps (although all synthesis tools further break down these generalsteps) to create the netlist:

Analyze/Check Syntax

Checks the syntax of the source code.

Compile

Translates and optimizes the HDL code into a set of components that the synthesis toolcan recognize.

Map

Translates the components from the compile stage into the target technologysprimitive components.

The synthesis tool can be changed at any time during the design flow. To change thesynthesis tool, do the following:

1. In the Hierarchy pane of the Project Navigator Design panel, select the targeted part.

2. Right-click and select Design Properties.

3. In the Design Properties dialog box, click the Synthesis Tool value and use the pull-down arrow to select the desired synthesis tool from the list.

Note: If you do not see your synthesis tool among the options in the list, you may not have the

software installed or may not have it configured in the ISE software. The synthesis tools are

configured in the Preferences dialog box. Select Edit>Preferences, expand ISE General, andclick Integrated Tools.

Changing the design flow results in the deletion of implementation data. You have not yetcreated any implementation data in this tutorial. For projects that contain implementation


Figure 2-24: Specifying Synthesis Tool


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Using the RTL/Technology Viewer

XST can generate a schematic representation of the HDL code that you have entered. Aschematic view of the code helps you analyze your design by displaying a graphicalconnection between the various components that XST has inferred. Following are the twoforms of schematic representation:

RTL ViewPre-optimization of the HDL code.

Technology View

Post-synthesis view of the HDL design mapped to the target technology.

To view a schematic representation of your HDL code, do the following:

1. In the Processes pane, expand Synthesize, and double-click View RTL Schematic orView Technology Schematic.

2. If the Set RTL/Technology Viewer Startup Mode dialog appears, select Start with theExplorer Wizard.

3. In the Create RTL Schematic start page, select the clk_divider and

lap_load_debounce components from the Available Elements list, and then click theAdd button to move the selected items to the Selected Elements list.

4. Click Create Schematic.X-RefTarget - Figure 2-25

Figure 2-25: Create RTL Schematic Start Page


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The RTL Viewer allows you to select the portions of the design to display as schematic.When the schematic is displayed, double-click on the symbol to push into the schematicand view the various design elements and connectivity. Right-click the schematic to viewthe various operations that can be performed in the schematic viewer.

You have completed XST synthesis. An NGC file now exists for the stopwatch design.

To continue with the HDL flow, do either of the following:

Go to Chapter 4, Behavioral Simulation, to perform a pre-synthesis simulation ofthis design.

Proceed to Chapter 5, Design Implementation, to place and route the design.

Note: For more information about XST constraints, options, reports, or running XST from the

command line, see the XST User Guide. This guide is available from the ISE Software Manualscollection, automatically installed with your ISE software. To open the Software Manuals collection,

select Help>Software Manuals. The Software Manuals collection is also available from the Xilinxwebsite.

Synthesizing the Design Using Synplify/Synplify Pro Software

Now that you have entered and analyzed the design, the next step is to synthesize thedesign. In this step, the HDL files are translated into gates and optimized to the target


Figure 2-26: RTL Schematic
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Mapper Report

The mapper report lists the constraint files used, the target technology, and attributes set inthe design. The report lists the mapping results of flattened instances, extracted counters,optimized flip-flops, clock and buffered nets that were created, and how FSMs were coded.

Timing Report

The timing report section provides detailed information on the constraints that youentered and on delays on parts of the design that had no constraints. The delay values are

based on wireload models and are considered preliminary. Consult the post-Place andRoute timing reports discussed in Chapter 5, Design Implementation, for the mostaccurate delay information.

Resource Utilization

This section of the report lists all of the resources that the Synplify software uses for thegiven target technology.

You have now completed Synplify synthesis. At this point, a netlist EDN file exists for thestopwatch design.


Go to Chapter 4, Behavioral Simulation, to perform a pre-synthesis simulation of

this design. Proceed to Chapter 5, Design Implementation, to place and route the design.

Synthesizing the Design Using Precision Synthesis

Now that you have entered and analyzed the design, the next step is to synthesize thedesign. In this step, the HDL files are translated into gates and optimized to the targetarchitecture.

Processes available for synthesis using the Precision software are as follows:

Check Syntax

Checks the syntax of the HDL code.

View Log File

Lists the synthesis optimizations that were performed on the design and gives a brieftiming and mapping report.

View RTL Schematic

Accessible from the Launch Tools hierarchy, this process displays the Precisionsoftware with a schematic view of your HDL code.


Figure 2-27: Synplify Estimated Timing Data


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View Technology Schematic

Accessible from the Launch Tools hierarchy, this process displays the Precisionsoftware with a schematic view of your HDL code mapped to the primitives associatedwith the target technology.

View Critical Path Schematic

Accessible from the Launch Tools hierarchy, this process displays the Precisionsoftware with a schematic view of the critical path of your HDL code mapped to theprimitives associated with the target technology.

Entering Synthesis Options and Synthesizing the Design

Synthesis options enable you to modify the behavior of the synthesis tool to optimizeaccording to the needs of the design. For the tutorial, the default property settings will beused.

To synthesize the design, do the following:

1. In the Hierarchy pane of the Project Navigator Design panel, select stopwatch.vhd(or stopwatch.v).

2. In the Processes pane, double-click the Synthesize process.

Using the RTL/Technology Viewer

Precision Synthesis can generate a schematic representation of the HDL code that you haveentered. A schematic view of the code helps you analyze your design by seeing a graphicalconnection between the various components that Precision has inferred. To launch thedesign in the RTL viewer, double-click the View RTL Schematic process. The followingfigure displays the design in an RTL view.

You have now completed the design synthesis. At this point, an EDN netlist file exists forthe stopwatch design.


Go to Chapter 4, Behavioral Simulation, to perform a pre-synthesis simulation ofthis design.

Proceed to Chapter 5, Design Implementation, to place and route the design.


Figure 2-28: Stopwatch Design in Precision Synthesis RTL Viewer


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Chapter 3

Schematic-Based Design

This chapter includes the following sections:

Overview of Schematic-Based Design

Getting Started

Design Description

Design Entry

Overview of Schematic-Based Design

This chapter guides you through a typical FPGA schematic-based design procedure usingthe design of a runners stopwatch. The design example used in this tutorial demonstratesmany device features, software features, and design flow practices that you can apply toyour own designs. The stopwatch design targets a Spartan-3A device; however, all of theprinciples and flows taught are applicable to any Xilinx device family, unless otherwisenoted.

This chapter is the first in the Schematic Design Flow. In the first part of the tutorial, youwill use the ISE design entry tools to complete the design. The design is composed ofschematic elements, CORE Generator software components, and HDL macros. After the

design is successfully entered in the Schematic Editor, you will perform behavioralsimulation (Chapter 4, Behavioral Simulation), run implementation with the Xilinximplementation tools (Chapter 5, Design Implementation), perform timing simulation(Chapter 6, Timing Simulation), and configure and download to the Spartan-3A(XC3S700A) demo board (see Chapter 7, iMPACT Tutorial).

Getting Started

The following sections describe the basic requirements for running the tutorial.

Required Software

To perform this tutorial, you must have Xilinx ISE Design Suite 12 installed. For thisdesign, you must install the Spartan-3A device libraries and device files.


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Chapter 3: Schematic-Based Design

This tutorial assumes that the software is installed in the default location, atc:\xilinx\12.1\ISE_DS\ISE. If you installed the software in a different location,substitute your installation path in the procedures that follow.

Note: For detailed software installation instructions, refer to the ISE Design Suite 12: Installation,

Licensing, and Release Notesavailable from the Xilinx website.

Installing the Tutorial Project Files

The tutorial project files are provided with the ISE Design Suite 12 Tutorials available fromthe Xilinx website. Download the schematic design files (wtut_sc.zip). The downloadcontains the following directories:

wtut_sc

Contains source files for the schematic tutorial. The schematic tutorial project will becreated in this directory.

wtut_sc\wtut_sc_completed

Contains the completed design files for the schematic tutorial design, includingschematic, HDL, and state machine files.

Note: Do not overwrite files under this directory.

The schematic tutorial files are copied into the directories when you unzip the files. Thistutorial assumes that the files are unzipped underc:\xilinx\12.1\ISE_DS\ISE\ISEexamples , but you can unzip the source files intoany directory with read/write permissions. If you unzip the files into a different location,substitute your project path in the procedures that follow.

Starting the ISE Software

To launch the ISE software, double-click the ISE Project Navigator icon on your desktop, orselect Start > AllPrograms > Xilinx ISE Design Suite 12.1 > ISE Design Tools > ProjectNavigator.

Creating a New Project

To create a new project using the New Project Wizard, do the following:

1. From Project Navigator, select File > New Project.

2. In the Location field, browse to c:\xilinx\12.1\ISE_DS\ISE\ISEexamples or

to the directory in which you installed the project.

3. In the Name field, enterwtut_sc.

4. Select Schematic as the Top-Level Source Type, and then click Next.

5. Select the following values in the New Project WizardDevice Properties page:

Product Category: All

Family: Spartan3A and Spartan3AN

Device: XC3S700A


Figure 3-1: Project Navigator Desktop Icon
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Design Description

Package: FG484

Speed: -4

Synthesis Tool: XST (VHDL/Verilog)

Simulator: ISim (VHDL/Verilog)

Preferred Language: VHDL or Verilog depending on preference. This will

determine the default language for all processes that generate HDL files.Other properties can be left at their default values.

6. Click Next, then Finish to complete the project creation.

Stopping the Tutorial

If you need to stop the tutorial at any time, save your work by selecting File > Save All.

Design Description

The design used in this tutorial is a hierarchical, schematic-based design, which means that

the top-level design file is a schematic sheet that refers to several other lower-level macros.The lower-level macros are a variety of different types of modules, including schematic-based modules, a CORE Generator software module, an Architecture Wizard module, andHDL modules.

The runners stopwatch design begins as an unfinished design. Throughout the tutorial,you will complete the design by creating some of the modules and by completing othersfrom existing files. Through the course of this chapter, you will create these modules,


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instantiate them, and then connect them. The following figure shows a schematic of thecompleted stopwatch design.

After the design is complete, you will simulate the design to verify its functionality. Formore information about simulating your design, see Chapter 4, Behavioral Simulation.

There are five external inputs and four external outputs in the completed design. Thefollowing sections summarize the inputs and outputs, and their respective functions.

Inputs

The following are input signals for the tutorial stopwatch design:

strtstop

Starts and stops the stopwatch. This is an active low signal which acts like thestart/stop button on a runners stopwatch.

reset

Puts the stopwatch in clocking mode and resets the time to 0:00:00.


Figure 3-2: Completed Stopwatch Schematic


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Design Description

clk

Externally generated system clock.

mode

Toggles between clocking and timer modes. This input is only functional while theclock or timer is not counting.

lap_load

This is a dual function signal. In clocking mode it displays the current clock value inthe Lap display area. In timer mode it will load the pre-assigned values from theROM to the timer display when the timer is not counting.

Outputs

The following are outputs signals for the design:

lcd_e, lcd_rs, lcd_rw

These outputs are the control signals for the LCD display of the Spartan-3A demoboard used to display the stopwatch times.

sf_d[7:0]

Provides the data values for the LCD display.

Functional Blocks

The completed design consists of the following functional blocks. Most of these blocks donot appear on the schematic sheet in the project until after you create and add them to theschematic during this tutorial.

The completed design consists of the following functional blocks:

clk_div_262k

Macro which divides a clock frequency by 262,144. Converts 26.2144 MHz clock into100 Hz 50% duty cycle clock.

dcm1

Clocking Wizard macro with internal feedback, frequency controlled output, andduty-cycle correction. The CLKFX_OUT output converts the 50 MHz clock of theSpartan-3A demo board to 26.2144 MHz.

debounce

Module implementing a simplistic debounce circuit for the strtstop, mode, andlap_load input signals.

lcd_control

Module controlling the initialization of and output to the LCD display.

statmach

State machine module which controls the state of the stopwatch.


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timer_preset

CORE Generator software 64X20 ROM. This macro contains 64 preset times from0:00:00 to 9:59:99 which can be loaded into the timer.

time_cnt

Up/down counter module which counts between 0:00:00 to 9:59:99 decimal. This

macro has five 4-bit outputs, which represent the digits of the stopwatch time.

Design Entry

In this hierarchical design, you will create various types of macros, including schematic-based macros, HDL-based macros, and CORE Generator software macros. You will learnthe process for creating each of these types of macros, and you will connect the macrostogether to create the completed stopwatch design. All procedures used in the tutorial can

be used later for your own designs.

Adding Source Files

Source files must be added to the project before the design can be edited, synthesized andimplemented. You will add six source files to the project as follows:

1. Select Project > Add Source.

2. Select the following files from the project directory and click Open.

cd4rled.sch

ch4rled.sch

clk_div_262k.vhd

lcd_control.vhd

stopwatch.sch

statmach.vhd

3. In the Adding Source Files dialog box, verify that the files are associated with All, thatthe associated library is work, and click OK.

The Hierarchy pane in the Design panel displays all of the source files currently added tothe project, with the associated entity or module names.

Opening the Schematic File in the Xilinx Schematic Editor

The stopwatch schematic available in thewtut_sc project is incomplete. In this tutorial,you will update the schematic in the Schematic Editor. After you create the project in theISE software and add the source files, you can open the stopwatch.sch file for editing.To open the schematic file, double-click stopwatch.sch in the Hierarchy pane of theDesign panel.


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Design Entry

The stopwatch schematic diagram opens in the Project Navigator Workspace. You will seethe unfinished design with elements in the lower right corner, as shown in the followingfigure.

Manipulating the Window View

The View menu commands enable you to manipulate how the schematic is displayed.Select View > Zoom > In until you can comfortably view the schematic.

The schematic window can be undocked from the Project Navigator framework byselecting Window > Float while the schematic is selected in the Workspace.

After being undocked, the schematic window can be redocked by selecting Window >Dock.

Creating a Schematic-Based MacroA schematic-based macro consists of a symbol and an underlying schematic. You cancreate either the underlying schematic or the symbol first. The corresponding symbol orschematic file can then be generated automatically.

In the following steps, you will create a schematic-based macro by using the New SourceWizard in Project Navigator. An empty schematic file is then created, and you can definethe appropriate logic. The created macro is then automatically added to the project library.


Figure 3-3: Incomplete Stopwatch Schematic


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The macro you will create is called time_cnt. This macro is a binary counter with five, 4-bitoutputs, representing the digits of the stopwatch.

To create a schematic-based macro, do the following:

1. In Project Navigator, select Project > New Source.

The New Source Wizard opens, which displays a list of all of the available source

types.

2. Select Schematic as the source type.

3. In the File name field, enter time_cnt.

4. Click Next, and click Finish.

A new schematic calledtime_cnt.sch is created, added to the project, and openedfor editing.

5. Change the size of the schematic sheet by doing the following:

Right-click on the schematic page and select Object Properties.

Click on the down arrow next to the sheet size value and select D = 34 x 22.

Click OK, and then click Yes to acknowledge that changing the sheet size cannotbe undone with the Edit > Undo option.

Defining the time_cnt SchematicYou have now created an empty schematic fortime_cnt. The next step is to add thecomponents that make up the time_cnt macro. You can then reference this macro symbol

by placing it on a schematic sheet.


Figure 3-4: New Source Dialog Box


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Design Entry

Adding I/O Markers

I/O markers are used to determine the ports on a macro or the top-level schematic. Thename of each pin on the symbol must have a corresponding connector in the underlyingschematic. Add I/O markers to the time_cnt schematic to determine the macro ports.

To add the I/O markers, do the following:

1. Select Tools > Create I/O Markers.

The Create I/O Markers dialog box opens.

2. In the Inputs field, enter q(19:0),load,up,ce,clk,clr.

3. In the Outputs box, enterhundredths(3:0),tenths(3:0),sec_lsb(3:0),sec_msb(3:0),minutes(3

:0).

4. Click OK.

The eleven I/O markers are added to the schematic sheet.

Note: The Create I/O Marker function is available only for an empty schematic sheet. However, I/O

markers can be added to nets at any time by selecting Add > I/O Marker and selecting the desired

net.

Adding Schematic Components

Components from the device and project libraries for the given project are available fromthe Symbol Browser, and the component symbol can be placed on the schematic. Theavailable components listed in the Symbol Browser are arranged alphabetically withineach library.

To add schematic components, do the following:

1. Select Add > Symbol, or click the Add Symbol toolbar button.


Figure 3-5: Create I/O Markers Dialog Box


Figure 3-6: Add Symbol Toolbar Button


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The Symbol Browser appears in the Options panel to the left of the schematic. TheSymbol Browser displays the libraries and their corresponding components.

Note: The Options panel changes depending on the action you are performing in the

schematic.

2. The first component you will place is a cd4rled, a 4-bit, loadable, bi-directional, BCDcounter with clock enable and synchronous clear. Select the cd4rled component, usingeither of the following methods:

Highlight the project directory category from the Symbol Browser dialog box andselect the component cd4rled from the symbols list.

Select All Symbols and enter cd4rled in the Symbol Name Filter at the bottomof the Symbol Browser.

3. Move the mouse back into the schematic window.

You will notice that the cursor has changed to represent the cd4rled symbol.

4. Move the symbol outline near the top and center of the sheet and click the left mousebutton to place the object.

Note: You can rotate new components being added to a schematic by selecting Ctrl+R. You

can rotate existing components by selecting the component, and then selecting Ctrl+R.


Figure 3-7: Symbol Browser


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Design Entry

5. Place three more cd4rled symbols on the schematic by moving the cursor withattached symbol outline to the desired location and clicking the left mouse button. Seethe following figure.

6. Follow the procedure outlined in steps 1 through 5 above to place the followingcomponents on the schematic sheet:

AND2b1

ch4rled

AND5

Refer to Figure 3-8 for placement locations.

7. To exit the Symbols mode, press the Esc key on the keyboard.


Figure 3-8: Partially Completed time_cnt Schematic


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For a detailed description of the functionality of Xilinx library components, right-click thecomponent and select Object Properties. In the Object Properties dialog box, selectSymbol Info. Symbol information is also available in the Libraries Guides. These guides areavailable from the ISE Software Manuals collection, automatically installed with your ISEsoftware. To open the Software Manuals collection, select Help > Software Manuals. TheSoftware Manuals collection is also available from the Xilinx website.

Correcting Mistakes

If you make a mistake when placing a component, you can easily move or delete thecomponent as follows:

To move the component, click the component and drag the mouse around thewindow.

To delete a placed component, use either of the following methods:

Click the component, and press the Delete key on your keyboard.

Right-click the component, and select Delete.

Drawing Wires

You can draw wires (also called nets) to connect the components placed in the schematic.Perform the following steps to draw a net between the AND2b1 and top cd4rledcomponents on thetime_cnt schematic:

1. Select Add > Wire, or click the Add Wire toolbar button.

2. Click the output pin of the AND2b1 and then click the destination pin CE on the

cd4rled component. The Schematic Editor draws a net between the two pins.3. Draw a net to connect the output of the AND5 component to the inverted input of the

AND2b1 component. Connect the other input of the AND2b1 to the ce input I/Omarker.

4. Connect the load, up, clk, and clr input I/O markers respectively to the L, UP, C, andR pins of each of the five counter blocksand connect the CEO pin of the first fourcounters to the CE pin of the next counter as shown in Figure 3-8.

To specify the shape of the net, do the following:

1. Move the mouse in the direction you want to draw the net.

2. Click the mouse to create a 90-degree bend in the wire.

Note: To draw a net between an already existing net and a pin, click once on the component pin and

once on the existing net. A junction point is drawn on the existing net.

Adding Buses

In the Schematic Editor, a bus is simply a wire that has been given a multi-bit name. To adda bus, use the methodology for adding wires and then add a multi-bit name. After a bushas been created, you have the option of tapping this bus off to use each signalindividually.


Figure 3-9: Add Wire Toolbar Button
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Design Entry

The next step is to create three buses for each of the five outputs of the time_cnt schematic.The results can be found in the completed schematic.

To add the buses hundredths(3:0), tenths(3:0), sec_lsb(3:0), sec_msb(3:0) and minutes(3:0)to the schematic, perform the following steps:

1. Select all of the output I/O markers by drawing a box around them and then drag the

group so that minutes(3:0) is below the Q3 output of the bottom counter block.2. Select Add > Wire, or click the Add Wire toolbar button.

3. Click in the open space just above and to the right of the top cd4rled, and then clickagain on the pin of the hundredths(3:0) I/O marker. The thick line shouldautomatically be drawn to represent a bus with the name matching that of the I/Omarker.

4. Repeat Steps 2 and 3 for the four remaining buses.

5. After adding the five buses, press Esc or right-click at the end of the bus to exit theAdd Wire mode.

Adding Bus Taps

Next, add nets to attach the appropriate pins from the cd4rled and ch4rled counters to thebuses. Use bus taps to tap off a single bit of a bus and connect it to another component.

Note: Zooming in on the schematic enables greater precision when drawing the nets.

To tap off a single bit of each bus, do the following:

1. Select Add > Bus Tap, or click the Add Bus Tap toolbar button.

The cursor changes, indicating that you are now in Draw Bus Tap mode.

2. In the Add Bus Tap Options that appear in the Options panel, choose the --< Rightorientation for the bus tap.


Figure 3-10: Adding a Bus


Figure 3-11: Add Bus Tap Toolbar Button


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3. Click on the hundreths(3:0) bus with the center bar of the cursor.

The Selected Bus Name and the Net Name values in the Options panel are nowpopulated.

Note: The indexes of the Net Name may be incremented or decremented by clicking the arrow

buttons next to the Net Name box.

4. With hundredths(3) as the Net Name value, move the cursor so the tip of the attachedtap touches the Q3 pin of the top cd4rled component.

Note: Four selection squares appear around the pin when the cursor is in the correct position.

5. Click once when the cursor is in the correct position.

A tap is connected to the hundredths(3:0) bus, and a wire named hundreths(3) isdrawn between the tap and the Q3 pin.

Click successively on pins Q2, Q1, and Q0 to create taps for the remaining bits of thehundredths(3:0) bus.

6. Repeat Steps 3 to 5 to tap off four bits from each of the five buses.

Note: It is the name of the wire that makes the electrical connection between the bus and the

wire (for example, sec_msb(2) connects to the third bit of sec(3:0)). The bus tap figure is for

visual purposes only. The following section shows additional electrical connections by nameassociation.

7. Press Esc to exit the Add Net Name mode.

8. Compare your time_cnt schematic with Figure 3-8 to ensure that all connections aremade properly.

Adding Net Names

First, add a hanging wire to each of the five inputs of the AND5 component and to the TCpin of each of the counter blocks.

Next, add net names to the wires. To add the net names, do the following:

1. Select Add > Net Name, or click the Add Net Name toolbar button.

2. In the Add Net Name Options that appear in the Options panel, do the following:

a. In the Name field, enter tc_out0.

b. Select Increase the Name.

The net name tc_out0 is now attached to the cursor.

3. Click the net attached to the first inputof the AND5 component.The name is attached to the net. The net name appears above the net if the name isplaced on any point of the net other than an end point.

4. Click on the remaining input nets of the AND5 to add tc_out1, tc_out2, tc_out3 andtc_out4.

The Schematic Editor increments the net name as each name is placed on a net.Alternatively, name the first net tc_out4 and select Decrease the name in the Add NetNames Options, and nets are named from the bottom up.


Figure 3-12: Add Net Name Toolbar Button


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Design Entry

5. Repeat step 2 and then click successively on the nets connected to the TC output to addtc_out0, tc_out1, tc_out2, tc_out3, and tc_out4 to these nets.

Note: Each of the wires with identical names are now electrically connected. In this case, the

nets do not need to be physically connected on the schematic to make the logical connection.

Finally, connect the input pins of the counters through net name association as follows:

1. Select Add > Wire or click the Add Wiretoolbar button, and add a hanging net to thefour data pins of each of the five counters.

2. Select Add > Net Name, or click the Add Net Name toolbar button.

3. In the Add Net Name Options that appear in the Options panel, enter q(0) in theName field.

4. Select Increase the name.

The net name q(0) is now attached to the cursor.

5. Click successively on each of the nets connected to data inputs, starting from the top sothat the net named q(0) is attached to the D0 pin of the top counter and the net namedq(19) is attached to the D3 pin of the bottom counter. See the following figure.

Note: If the nets appear disconnected, select View > Refresh to refresh the screen


Figure 3-13: Completed time_cnt Schematic


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Checking the Schematic

The time_cnt schematic is now complete. Verify that the schematic does not contain logicalerrors by running a design rule check (DRC). To do this, select Tools > Check Schematic.The Console should report that no errors or warnings are detected. If an error or warningis displayed, fix the reported problem before proceeding.

Saving the Schematic

Save the schematic as follows:

1. Select File > Save, or click the Save toolbar button.

2. Close the time_cnt schematic.

Creating and Placing the time_cnt SymbolThe next step is to create a symbol that represents the time_cnt macro. The symbol is aninstantiation of the macro. After you create a symbol for time_cnt, you will add the symbolto a top-level schematic of the stopwatch design. In the top-level schematic, the symbol ofthe time_cnt macro will be connected to other components in a later section in this chapter.

Creating the time_cnt Symbol

You can create a symbol using either a Project Navigator process or a Tools menucommand.

To create a symbol that represents the time_cnt schematic using a Project Navigatorprocess, do the following:

1. In the Hierarchy pane of the Design panel, selecttime_cnt.sch.

2. In the Processes pane, expand Design Utilities, and double-click Create SchematicSymbol.

To create a symbol that represents the time_cnt schematic using a Tools menu command,do the following:

1. With the time_cnt schematic sheet open, select Tools > Symbol Wizard.

2. In the Symbol Wizard, select Using Schematic, and select time_cnt.

3. Click Next, then Next, then Next, and then Finish to use the wizard defaults.

4. View and then close the time_cnt symbol.


Figure 3-14: Save Toolbar Button


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Placing the time_cnt Symbol

Next, place the symbol that represents the macro on the top-level schematic(stopwatch.sch) as follows:

1. In the Hierarchy pane of the Design panel, double-click stopwatch.sch to open theschematic.


3. In the Symbol Browser, select the local symbols library(c:\xilinx\12.1\ISE_DS\ISE\ISEexamples\wtut_sc ), and then select thenewly created time_cnt symbol.

4. Place the time_cnt symbol in the schematic so that the output pins line up with the fivebuses driving inputs to the lcd_control component. This should be close to gridposition [1612,1728]. Grid position is shown at the bottom right corner of the ProjectNavigator window, and is updated as the cursor is moved around the schematic.

Note: Do not worry about connecting nets to the input pins of the time_cntsymbol. You will dothis after adding other components to the stopwatch schematic.

5. Save the changes and close stopwatch.sch.

Creating a CORE Generator Software Module

The CORE Generator software is a graphical interactive design tool that enables you tocreate high-level modules such as memory elements, math functions, communications,and I/O interface cores. You can customize and pre-optimize the modules to takeadvantage of the inherent architectural features of the Xilinx FPGA architectures, such asFast Carry Logic, SRL16s, and distributed and block RAM.

In this section, you will create a CORE Generator software module called timer_preset.The module is used to store a set of 64 values to load into the timer.

Creating the timer_preset CORE Generator Software Module

To create a CORE Generator software module, do the following:

1. In Project Navigator, select Project>New Source.

2. Select IP (Coregen & Architecture Wizard).

3. In the File name field, enter timer_preset.

4. Click Next.

5. Double-click Memories & Storage Elements > RAMs & ROMs.




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6. Select Distributed Memory Generator, then clickNext, and click Finish to open theDistributed Memory Generator customization GUI. This customization GUI enablesyou to customize the memory to the design specifications.

7. Fill in the Distributed Memory Generator customization GUI with the followingsettings:

Component Name: timer_preset (defines the name of the module)

Depth: 64 (defines the number of values to be stored)

Data Width: 20 (defines the width of the output bus)

Memory Type: ROM

8. Click Next.


Figure 3-16: New Source WizardSelect IP Page


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9. Leave Input and Output options as Non Registered, and click Next.

10. To specify the Coefficients File, click the Browse button, and selectdefinition1_times.coe.

11. Check that only the following pins are used (used pins are highlighted on the symbolon the left side of the customization GUI):

a[5:0]

spo[19:0]

12. Click Generate.

The module is created and automatically added to the project library.

A number of files are added to the ipcore_dir sub-directory of the project directory.Following is a list of some of these files:

timer_preset.sym

This file is a schematic symbol file.

timer_preset.vhd or timer_preset.v

These are HDL wrapper files for the core and are used only for simulation.

timer_preset.ngc

This file is the netlist that is used during the Translate phase of implementation.


Figure 3-17: CORE Generator SoftwareDistributed Memory GeneratorCustomization GUI


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timer_preset.xco

This file stores the configuration information for the timer_preset module and is usedas a project source.

timer_preset.mif

This file provides the initialization values of the ROM for simulation.

Creating a DCM Module

The Clocking Wizard, a Xilinx Architecture Wizard, enables you to graphically selectDigital Clock Manager (DCM) features that you want to use. In this section, you will createa basic DCM module with CLK0 feedback and duty-cycle correction.

Using the Clocking Wizard

Create the dcm1 module as follows:

1. In Project Navigator, select Project > New Source.

2. Select theIP (Coregen & Architecture Wizard)

source type.3. In the File Name field, enter dcm1.

4. Click Next.

5. In the Select IP dialog box, select FPGA Features and Design> Clocking>Spartan-3E, Spartan-3A >Single DCM_SP.

6. Click Next, then click Finish.

The Clocking Wizard opens.

7. Verify that RST, CLK0 and LOCKED ports are selected.

8. Select CLKFX port.


Figure 3-18: Selecting Single DCM Core Type


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9. Type 50 and select MHz for the Input Clock Frequency.

10. Verify the following settings:

Phase Shift: NONE

CLKIN Source: External, Single

Feedback Source: Internal

Feedback Value: 1X

Use Duty Cycle Correction: Selected

11. Click the Advanced button.

12. Select the Wait for DCM Lock before DONE Signal goes high option.

13. Click OK.

14. Click Next, and then Next again.

15. Select Use output frequency and enter 26.2144 in the box and select MHz.

16. Click Next, and then click Finish.

The dcm1.xaw file is created and added to the list of project source files in the Hierarchypane of the Design panel.


Figure 3-19: Xilinx Clocking WizardGeneral Setup

26.2144Mhz( ) 218

100Hz=


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Creating the dcm1 Symbol

Next, create a symbol representing the dcm1 macro. This symbol will be added to the top-level schematic (stopwatch.sch) later in the tutorial.

1. In Hierarchy pane of the Project Navigator Design panel, select dcm1.xaw.

2. In the Processes pane, double-click Create Schematic Symbol.

Creating an HDL-Based Module

With the ISE software, you can easily create modules from HDL code. The HDL code isconnected to your top-level schematic design through instantiation and compiled with therest of the design.

You will author a new HDL module. This macro will be used to debounce the strtstop,mode, and lap_load inputs.

Using the New Source Wizard and ISE Text Editor

In this section, you create a file using the New Source wizard, specifying the name and

ports of the component. The resulting HDL file is then modified in the ISE Text Editor.

To create the source file, do the following:

1. Select Project > New Source.

2. Select VHDL Module or Verilog Module.

3. In the File Name field, enter debounce.

4. Click Next.

5. Enter two input ports named sig_in and clk and an output port named sig_out for thedebounce component as follows:

a. In the first three Port Name fields, enter sig_in,clk and sig_out.

b. Set the Direction field to input forsig_in and clk and to output for sig_out.

c. Leave the Bus designation boxes unchecked.X-RefTarget - Figure 3-20

Figure 3-20: New Source Wizard for Verilog


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6. Click Next to view a description of the module.

7. Click Finish to open the empty HDL file in the ISE Text Editor.

The VHDL file is shown in the following figure.

The Verilog HDL file is shown in the following figure.


Figure 3-21: VHDL File in ISE Text Editor


Figure 3-22: Verilog File in ISE Text Editor


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In the ISE Text Editor, the ports are already declared in the HDL file, and some of the basicfile structure is already in place. Keywords are displayed in blue, comments in green, andvalues are black. The file is color-coded to enhance readability and help you recognizetypographical errors.

Using the Language Templates

The ISE Language Templates include HDL constructs and synthesis templates whichrepresent commonly used logic components, such as counters, D flip-flops, multiplexers,and primitives. You will use the Debounce Circuit template for this exercise.

Note: You can add your own templates to the Language Templates for components or constructs

that you use often.

To invoke the Language Templates and select the template for this tutorial, do thefollowing:

1. From Project Navigator, select Edit>Language Templates.

Each HDL language in the Language Templates is divided into five sections: CommonConstructs, Device Primitive Instantiation, Simulation Constructs, SynthesisConstructs, and User Templates. To expand the view of any of these sections, click the

plus symbol (+)next to the section. Click any of the listed templates to view thetemplate contents in the right pane.

2. Under either the VHDL or Verilog hierarchy, expand Synthesis Constructs, expandCoding Examples, expand Misc, and select the template called Debounce Circuit.Use the appropriate template for the language you are using.

When the template is selected in the hierarchy, the contents display in the right pane.


Figure 3-23: Language Templates


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Adding a Language Template to a File

You will now use Use in File method for adding templates to your HDL file. Refer toWorking with Language Templates in the ISE Help for additional usability options,including drag and drop options.

To add the template to your HDL file, do the following:

1. With the debounce.v or debounce.vhd source file active, position the cursor underthe architecture begin statement in the VHDL file, or under the module and pindeclarations in the Verilog file.

2. Return to the Language Templates window, right-click on the Debounce Circuittemplate in the template index, and select Use In File.

3. Close the Language Templates window.

4. Open the debounce.v or debounce.vhd source file to verify that the LanguageTemplate was properly inserted.

5. Verilog only: Complete the Verilog module by doing the following:

a. Remove the reset logic (not used in this design) by deleting the three lines

beginning withif

and ending withelse

.b. Change to qin all six locations.

c. Change to clk; to sig_in; and to sig_out.

Note: You can select Edit > Find & Replace to facilitate this. The Find fields appear at the


6. VHDL only: Complete the VHDL module by doing the following:

a. Move the line beginning with the word signalso that it is between thearchitectureandbeginkeywords.

b. Remove the reset logic (not used in this design) by deleting the five linesbeginning with if (... and ending with else, and delete one of theend if; lines.

c. Change to clk; D_IN to sig_in; and Q_OUT to sig_out.Note: You can select Edit > Find & Replace to facilitate this. The Find fields appear at the


7. Save the file by selecting File>Save.

8. Select one of the debounce instances in the Hierarchy pane.

9. In the Processes pane, double-click Check Syntax. Verify that the syntax check passessuccessfully. Correct any errors as necessary.

10. Close the ISE Text Editor.


Figure 3-24: Selecting Language Template to Use in File


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Creating Schematic Symbols for HDL Modules

Next, create the schematic symbols for both the debounce and statmach HDL files asfollows:

1. In the Hierarchy pane of the Project Navigator Design panel, select debounce.vhd ordebounce.v.

2. In the Processes panel, expand Design Utilities, and double-click Create SchematicSymbol.

3. Repeat this procedure for the statmach.vhd file.

You are now ready to place the symbols on the stopwatch schematic.

Placing the statmach, timer_preset, dcm1, and debounce Symbols

You can now place the statmach, timer_preset, dcm1, and debounce symbols on thestopwatch schematic (stopwatch.sch).

To place the symbols, do the following:

1. In the Hierarchy pane of the Project Navigator Design panel, double-clickstopwatch.sch.

The schematic file opens in the Workspace


The Symbol Browser appears in the Options panel to the left of the schematic. TheSymbol Browser displays the libraries and their corresponding components.

3. View the list of available library components in the Symbol Browser.

4. Locate the project-specific macros by selecting the project directory name in theCategories window.

5. Select the appropriate symbol, and add it to the stopwatch schematic in theapproximate location, as shown in Figure 3-26.

Note: Do not worry about drawing the wires to connect the symbols. You will connect

components in the schematic later in the tutorial.

6. Save the schematic.




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The following figure shows the stopwatch schematic with placed symbols.X-RefTarget - Figure 3-26

Figure 3-26: Placing Design Macros


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