Inverter Dynamic

8/10/2019 Inverter Dynamic

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DynamicCharacteristicsofCMOSInverter

1


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Power

Dissipation

in

Inverter

Circuits

Staticpowerdissipation(Ps)dueto

leakagecurrents

othercurrentdrawncontinuouslyfromthepowersupply

Dynamicpower

dissipation

(Pd)

due

to

charging

and

dischargingloadcapacitance

Shortcircuit

power

dissipation

(Psc)

during

the

finite

riseandfalltimesofinput

2P=Ps+Pd+Psc


3/27

CMOS

Inverter

Static

Power NostaticcurrentinCMOSaslongasVinVDD+VTP

Leakagecurrent

isdeterminedbytheofftransistorinfluencedby

transistorwidth

supply

voltage MOSthresholdvoltage

3


4/27

Leakage

(Static)

Power

Consumption

Subthreshold

current

is

the

dominant

factor.

Allleakagecurrentincreaseexponentiallywith

temperature!

4

VDDIleakage

Subthresholdleakage

Gateleakage

Drain(diode)

leakage

DIBL


5/27


6/27

DynamicPowerDissipation

6

outDN LdV

i t Cdt

outDP LdV

i t Cdt

2

0

2

1

T

T

d out DD o ooutL utLut

T

v t dV

dt V vCd

dVC

dP t dt

t tT

0

0

1

DD

DD

V

d out DDL out L oout

V

utP C dV v t V v t C dVT

0

2 2

0

1

2 2

DD

DD

V

out out

d DD ou

V

L L tP C C V V

V V

T

21d L DD

C VPT

2

d L DDC VP f


7/27

ShortCircuitPowerConsumption

Duringswitching

Finiteslopeofinputsignalcausesadirectpath

betweenVDDandGNDforashortperiodoftime

Boththetransistorsareconducting

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8/27

ShortCircuitPowerConsumption

Imaxisdeterminedby

SaturationcurrentofNMOSandPMOS

Dependson

sizes

processtechnology

temperature

Imaxisastrongfunctionof

Ratiobetweentheinputandoutputslopes

afunction

of

CL 8


9/27

ShortCircuit

Power

Consumption

ApproximateISCas

atriangular

function

Energypercycle

92 2 2

fmax r f max

SC DD D

r

D SC

I t

E

t tI t

V V I

SC DD SC P V I f


10/27

ImpactofCLonPSC

10

With

large

CL

Inputmovesthroughthetransientregionbeforethe

outputstartstochange

VDSofPMOS

is

0duringthisperiod PMOSshutsoffwithoutdeliveringanycurrent

ISC

0


11/27

ImpactofCLonPSC

11

Withsmall

CL

Outputfalltimeismuchsmallerthantheinputrisetime

PMOSVDS

VDD

formostofthetransitionperiod

PMOSdeviceisinsaturation

ISCPMOSsaturationcurrent


12/27

Observationson

PSC

Short circuit dissipation is minimized when

output rise (fall) time larger than input rise (fall) time

Output rise (fall) time too large slows down the gate

Can cause short circuit currents in the fan-out gates

Local vs. global conflict

Short circuit dissipation is minimized by

Matching the rise/fall times of the input and output signals

For the overall circuit, the rise (fall) times of all signals should

be kept within a range

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13/27

ObservationsonPSC Shortcircuitcurrentisreducedwhenthepowersupplyis

lowered.

WhenVDD


14/27

NMOS/PMOSRatio

WidthofPMOSisincreasedsothattheresistancematchesthatof

NMOS

PMOS

to

NMOS

width

equals

to

the

ratio

of

mobility

(n/p),

typically2to3.5(ifstrainedsiliconisused,1)

Motivationbehindthisapproachistocreateaninverterwith

symmetricalVTC

PLH=PHL

Ratiomaynotyieldstheminimumoverallpropagationdelay

Ifsymmetryandreducednoisemarginsarenotofprimeconcern

speedupinverterbyreducingthewidthofthePMOSdevice

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15/27

NMOS/PMOSRatio

Rationalitybehindthestatement wideningthe

PMOSis

Improves

the

tPLHof

the

inverter

by

increasing

the

chargingcurrent

DegradesthetPLHbecauseofalargerparasitic

capacitance Whentwocontradictoryeffectsarepresent,

theremustexistatransistorratiothatoptimizes

thepropagation

delay

of

the

inverter

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17/27

CascadedInverter WithReqp(Reqn)theequivalentonresistanceofthe

PMOS(NMOS) overtheintervalofinterest

with

PLH= R

eqpC

Land

PHL= R

eqnC

L

Theaveragepropagationdelayis

r(=Reqp/Reqn)representstheresistanceratioof

identicallysizedPMOSandNMOStransistors.

17

1 212

eqp

p qdn ew ngnC CR

RC

1 21 12

dn gn wp eqnC

rRC C


18/27

CascadedInverter

Theoptimalvalueof(opt)canbefoundbysetting

thefirst

differential

of

pwithrespecttoto0

Ifwiring

capacitance

is

not

negligible,

larger

value

of

shouldbeused

18

1 21 12

dn gn wp eqnC r RC C

1 2

1 wopt

dn dn

Cr

C C


19/27

CascadedInverter The

optimum

value

of

isaround1.9

19

Smallerdevicesizesyield

fasterdesignatthe

expense

of

symmetry

and

noisemargin

IfCwisnegligible,

(Cdn1+Cgn2>>Cw),

opt=

r0.5

,

incontrasttothefactorr

normallyusedinthenon

cascadedcase.


20/27

SuperBuffer

CL

Givenalarge

capacitive

load

CL

Howtosizetheinverters?

Howmanystagesareneededtominimizethedelay?

SuperBuffer

Achainofinvertersdesignedtodrivealargecapacitiveloadwith

minimalsignalpropagationdelaytime.

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21/27

InverterSizing Let

CirefandRrefbethereferenceintrinsiccapacitanceand

equivalentonresistanceoftheinverter,andSbethe

sizingfactor

21

0.69 eq intrinsic xtp eR C C

0.69

ref

eep xtir fS

S

RC C

0.69 1ref iref

x

ref

p

i

e tC

RS

CC

0 1pe

pt

ir f

ex

CS

C


22/27

InverterSizing

CgandCintrinsicareproportionaltothegatesizeone

canwrite

(thus

isthesizingfactor)Cintrinsic=Cg

NisNumberofinverterstages

Thedelayofjth inverterstagecanbewrittenas

22

, 1

, 0

,

1 g j

p j p

g j

C

C

01

pe

p

t

ir f

ex

C

C


23/27

InverterSizing

Totaldelaycanbecalculatedas

WithCg,N+1=CL

Minimumpisobtainedbysetting

23

, 1

, 0

,0 0

1 g j

p p j p

g

N N

j j j

C

C

0 1pe

pt

ir f

ex

CC

,

0p

g j

for each jC


24/27

InverterSizing

Eachinverterissizedupbythesamefactorfwithrespecttotheprecedinggate,andthussamedelay

GivenCg,0andCL(Fistheeffectivesizeratio)

24

, 1 ,

, , , 10 ; 1

p g j g j

g j g j g j

C C

for j NC C C

,

1

0

1N

NL

gCf

CF


25/27

InverterSizing

Theminimumdelayis

Evaluating

25

01

1 1

N

p p

FN

0p

N

11 ln 0

1

NN F FF

N

1 ff e

1f ln f


26/27

InverterSizing

Forthespecialcasewhen=0(noselfloading),

Inreality,

the

self

loading

cannot

be

ignored

26

1f ln f f e


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Buffer

Design

27

1

1

1

1

8

64

64

64

64

4

2.8 8

16

22.6

N f tp

0 64 65

1 8 18

2 4 15

3 2.8 15.3

Inverter Dynamic

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