ESE 570 MOS INVERTERS DYNAMIC CHARACTERISTICSese570/spring2015/ESE570_InvDyn15.pdf · MOS Inverter...

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 1

ESE 570 MOS INVERTERS DYNAMIC CHARACTERISTICS


UsuallyCdb >> Cgd & Csb >> Cgs

i≈i# ## # # # worst case

extrinsicparasitic

caps

n = fan-out ≥ 1

Cgb

= Cgbn

+ Cgbp

Cload

= C#dbn

+ C#dbp

+ C#gdn

+ C#gdp

+ Cint

+ nCgb

≈ C#dbn

+ C#dbp

+ Cint

+ n Cgb

Intrinsic Parasitic Caps


Cload

≈ Cdbn

+ Cdbp

+ Cint

+ nCgb where n = fan-out ≥ 1


VDD

0 t

VDD

0

V50% = VDD/2


VDD

VDD

0

0

V50% = VDD/2


VDD

0

V10% = 0.1 VDD

V90% = 0.9 VDD


MOS Inverter Dynamic Performance 1. ANALYSIS (OR SIMULATION): For a given MOS inverter schematic +

Cload, estimate (or determine) the propagation delays τPHL and/or τPLH, OR the rise/fall times τrise and/or τfall.

2. DESIGN: For given specs for the propagation delays τPHL and/or τPLH, OR the rise/fall times τrise and/or τfall + Cload, determine the MOS inverter schematic.

METHODS:1. Average Current Model

2. Differential Equation Model

where3. 1st Order RC Delay Model

iC=C loadd V out

dt⇒∫dt=C load∫

d V out

iC

>PHL≈C load

8V HL

I avg , HL=C load

5V OH−V 50 p6I avg , HL

%

>PHL≈0.69 C load∗Rn

Assume Vin ideal

dt≈>PHL


VDD

0 t

t

VDD

VDD

VDD

0, 0,

CALCULATION OF PROPOGATION DELAY TIMES

VDD

0

VDD

0

>PHL≈C load8V HL

I avg , HL=

C load 5V DD−V DD /26I avg , HL

=C load Reff , HL

>PLH≈C load 8V LH

I avg , LH=

C load 5V DD /2−06I avg , LH

=C load Reff , LH

VDD/2)]

VDD/2)]


VDD V

DD

0, 0,

CALCULATION OF RISE & FALL TIMES

iC = i

DP - i

Dn

VDD

0

(0.9VDD– 0.1VDD)

(0.9VDD– 0.1VDD)

0.1VDD)]

0.9VDD)]


Calculating Propagation Delays By Solving the Circuit Differential Equation

Two Cases1. V

in abruptly rises => V

out falls =>

2. Vin abruptly falls => V

out rises =>

Let's assume Vin is an ideal step-input.

>PHL

>PLH

iDP

- iDn


C load

d V out

d t≈−iDn⇒dt=C load 5

−d V out

iDn6

1) Vin – ABRUPTLY RISES CASE -> >PHL

iDp≈0

Vin(t < t0) = 0 and Vout (t < t0) = VDD

LIN V50%

≤ Vout

< VDD

- VT0n

Vin(t = t0) = 0 -> VDD

V50%

= VDD

/2

V out=V DD−V T0n

t sat


CMOS Static Inverter Characteristics Recall


C loadd V out

d t≈−iDn⇒dt=C load 5

−d V out

iDn6

>pHL=∫t=t0

t=t50 dt=C load∫V out=V DD

V out=0.5V DD

5−1iDn

6dV out=C load Reff , HL

.=C load∫V DD

V DD−V T0n

5−1iDn

6dV out1C load∫V DD−V T0n

0.5VDD

5−1iDn

6dV out

nMOS SAT nMOS LIN

1) Vin – ABRUPTLY RISES CASE -> >PHL

50%

Vin(t = t0) = 0 -> VDD

V50%

= VDD

/2

tsat

- t0

t50%

- tsat

= t50%

- t0

t sat


1) Vin – ABRUPTLY RISES CASE => cont.>PHL

VDD

VDD

∫t0

t1'

dt=C load∫V DD

V DD−V T0n

5−1iDn

6dV out

∫t0

t1'

dt=−C load

kn

25V DD−V T0n6

2∫V DD

V DD−V T0n dV out

t1' −t0=

2C load V T0n

k n5V DD−V T0n62

dt=C load

−dV out

iDn

iDn=k n

25V in−V T0n6

2=−iC

for V DD−V T0n≤V out≤V DDand

iDn=−C load

dV out

dt=>

V50%

= VDD

/2

k n

25V in−V T0n6

2=−C load

dV out

dt

Vin = VDD

t sat

t0 < t < t

sat

t sat

t sat

t sat



iDn=k n

2[5V in−V T0n6V out−V out

2 ]=−iC

k n

2[5V DD−V T0n6V out−V out

2 ]=−C load

dV out

dt

VDD

0

V out≤V DD−V T0n

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VT0nV

out = V

DD - V

T0n

Vout

= V50%

∫t1'

t50p dt=C load∫V DD−V T0n

V 50p

5−1iDn

6dV out50% 50%

-

-

VDD

V50%

= VDD

/2 Vin = VDD and

tsat

< t < t50%

t sat

tsat

tsat

t sat

0.5VDD

0.5VDD



VDD V

DD

VDD

VDD

VDD

t1' −t0=

2 C load V T0n

k n 5V DD−V T0n62

VDD

VDD

VDD

VDD

VDD

VDD

Vout

= V50%

= 0.5VDD

Vout

= VDD

- VT0n

VDD

/2V

DD/2

VDD

/2V

DD/2

VDD

/2

Rn

tsat

tsat

tsat

tsat



VDD

VDD

VDD

VDD

Recall from static CMOS Inverter:

k R=k n

k p=

kn' 5W /L6n

k p' 5W /L6 p

==n5W /L6n= p5W /L6p

VDD

/2

(1) Vth → k

R; (2) τ

PHL → k

n; (3) k

R & k

n → k

p DESIGN:


.≈2C load 50.5V DD6

kn 5V DD−V T0n62

>PHL≈C load V DD

k n 5V DD−V T0n62≈Rn C load

SOMETIMES USED APPROXIMATION FOR τPHL

>PHL=∫t=t0

t=t1'

dt≈−C load

k n

25V DD−V T0n6

2∫V out=V DD

V out=0.5V DD dV out

t =t50%

Δ is less than 10%t sat


VDD

= 5 V, VGSn

= 5 V and VDSn

≥ 4V => iDn

= iDnsat

= 5mA

VDDV

50% = 0.5 V

DD = 2.5 V


Example 6.1 cont.

.= 1 pF0.625 x 10−3 A/V 255−16V

[2 V

55−16V1ln 5 4 55−16V

5V−16]

.= 1 pF0.625 x 10−3 A/V 54 6

[241ln 5 16

5−16]=0.52 ns

FA/V

=FA

V=C /VC / s

V=sUNITS:


>PHL≈C load V DD

k n 5V DD−V T0n62=

1 x 10−12 F∗5V10−2 A4V 2 54V 62

=0.5 ns

COMPARISON WITH SOMETIMES USED APPROXIMATION FOR τ

PHL

Approximation for τPHL

= 0.52 ns

k n=2 iDnsat

5V DD−V T0n62=

10 mA54V 62

=0.625 x 10−3 A /V 2where


A

DD DD

DD DD

0.99 mA


Example 6.2 cont.

DD

-6.25 x 10-10 s/V Vout

|Vout = 4.0V

Vout

= 4.5V

0.99 x 10-3 A4.04 ns

0.31 ns

tsat

tsat

tsat


Example 6.2 cont.

0.31 ns

Vin = 5 V

Vin = 5 V

3.39 ns

3.39 ns + 0.31 ns = 3.70 ns

tsat

tsat

tsat

tsat

tsat

0.5 V0.5 V


2) Vin – ABRUPTLY FALLS CASE => >PLH

i Dn≈0

Vout (t < t0) = 0, Vin(t = t0) = VDD -> 0

LIN - VT0p

< Vout

≤ VDD

/2SAT 0 < V

out ≤ - V

T0p

VDD

C load

d V out

d t≈iDp⇒dt=C load 5

d V out

iDp6

V50%

= VDD

/2

tsat


i Dn≈0

VDD

CMOS Static Inverter Characteristics Recall


C load

d V out

d t≈iDp⇒dt=C load 5

d V out

iDp6

>PLH2) Vin – ABRUPTLY FALLS CASE =>

VDD

>PLH=∫t=t 0

t=t 50p dt=C load∫V out=0

V out=V 50p

51

iDp6dV out=C load Reff , LH

.=C load∫0

−V T0p

51

iDp6dV out1C load∫−V T0p

V 50p

51

iDp6dV out

pMOS SAT pMOS LIN

50% 50%

50%

V50%

= VDD

/2

tsat

- t0

t50%

- tsat

= t50%

- t0

tsat


2) Vin – ABRUPTLY FALLS CASE => cont.>PLH

VDD

VDD

VDD

VDD

Recall from static CMOS Inverter:

k R=k n

k p=

kn' 5W /L6n

k p' 5W /L6 p

==n5W /L6n= p5W /L6p

VDD

/2

(1) Vth → k

R; (2) τ

PLH → k

p; (3) k

R & k

p → k

n DESIGN:

.≈Rp C load


SOMETIMES USED APPROXIMATION FOR τPLH

>PLH=∫t=t0

t=t sat dt≈C load

k p

25V DD−∣V T0p∣6

2∫V out=0

V out=0.5V DD dV out

.≈2C load 50.5V DD6

k p 5V DD−∣V T0p∣62

>PLH≈C load V DD

k p 5V DD−∣V T0p∣62≈R p C load

Δ is less than 10%

V50%

= VDD

/2

tsat


Inverter Dynamic Performance – Quick Review 1. ANALYSIS (OR SIMULATION): For a given MOS inverter schematic +

Cload, estimate (or determine) the propagation delays τPHL and/or τPLH, OR the rise/fall times τrise and/or τfall.

2. DESIGN: For given specs for the propagation delays τPHL and/or τPLH, OR the rise/fall times τrise and/or τfall + Cload, determine the MOS inverter schematic.

METHODS:1. Average Current Model

2. Differential Equation Model

3. 1st Order RC Delay Model

iC=C loadd V out

dt⇒∫dt=C load∫

d V out

iC

>PHL≈C load

8V HL

I avg , HL=C load

5V OH−V 50 p6I avg , HL

%

>PHL≈0.69C load∗Rn

Assume Vin ideal


5WL6

p==n

= p5WL6

n=>

CONDITIONS for Balanced CMOS Propagation Delays, i.e.

Quick Review τPLH & τPHL Differential Equation Model

i.e. Symmetrical Inverter


µp


27


>PHL≈C load V DD

k n 5V DD−V T0n62≈Rn C load

>PLH≈C load V DD

k p 5V DD−∣V T0p∣62≈R p C load

k n==n C ox

W n

Ln

k p==p Cox

W p

L p

W n

Ln≈

C load V DD

>PHL=n Cox 5V DD−V T0n62

W p

L p≈

C load V DD

>PLH =p C ox5V DD−∣V T0p∣62

ALTERNATIVE APPROXIMATE DELAY DESIGN FORMULASUsing the approximate delay formulas on slides 18 and 29:


VDD


Example 6.3 cont. t 5V out=1V 6

t 5V out=4 V 6

V out=1V

V out=4V

∫dt=−C load∫dV out

iDn5lin6

8.118.11

0


Example 6.3 cont.

8.11 Wn = 8.11 (1 µm) = 8.11 µm

8.11 µm = 10.81 µm


µp


Cload Cdbn + Cdbp + Cint + Cgbi≈i

i≈iCload Cdbn(Wn) + Cdbp(Wp) + Cint + Cgb

Design for Propagation Delays Using More Realistic Model for Cload

(Wn, Wp).


Design for Propagation Delays Using More Realistic Model for Cload cont.

Cload = α0 + αnWn + αpWp

α0 = 2YC

jswnK

eqn + 2YC

jswpK

eqp + C

int + C

gb

αn = (Y + x

j)C

j0nK

eqn + C

jswnK

eqn

αp = (Y + x

j)C

j0pK

eqp + C

jswpK

eqp

Cdbn (Wn) = [Wn (Y + xj)] Cj0n Keqn + (Wn + 2Y) Cjswn Keqn(sw)Cdbp (Wp) = [Wp (Y + xj)] Cj0p Keqp + (Wp + 2Y) Cjswp Keqp(sw)



= α0 + (α

n + (W

p/W

n) α

p)W

n

const.

>PLH=7 p

C load

W p>PHL=7n

C load

W nand

Cload = α0 + αnWn + αpWp

where

Γn and Γ

P are set largely by process parameters and VDD.

µp


Multiply and divide αpW

p by W

nMultiply and divide α

nW

n by W

p

Cload

= α0 + α

nW

n + (α

pW

p/W

n)W

n = α

0 + [α

n + α

pR]W

n

Cload

= α0 + (α

nW

n/W

p)W

p + α

pW

p = α

0 + [α

n/R + α

p]W

p

>PHL=7n

C load

W n>PLH=7 p

C load

W p

Cload = α0 + αnWn + αpWpCload = α0 + αnWn + αpWp

where R = Wp/W

n = constant

α0 + [α

n + α

pR]W

n

Wn

τPHL

Γ?n

τPLH

Γ?p

α0 + [α

n/R + α

p]W

p

Wp

V th⇒1k R

==p W p

=nW n

(Recall: when Lp=L

n)



α0 + [α

n + α

pR]W

n

Wn

τPHL

Γ?n τ

PLH Γ?

p

α0 + [α

n/R + α

p]W

p

Wp

where R = aspect ratio = Wp/W

n

= limit τPHL

= Γn [α

n + α

p R]

Wn → large

Pavg≈C load V DD2 f

α0 = f(C

int, C

gb).

absolute minimum

delays>PLH

Limit = limit τPLH

= Γp [α

n/R + α

p]

Wp → large

R = constant

R = constant

>PHLLimit

Hence increasing Wn and W

p will have diminishing influence on τ

PHL and

τPLH

as they become large, i.e.



= limit τPHL

= Γn [α

n + α

p R]

Wn → large absolute

minimum delays

>PLHLimit = limit τ

PLH = Γ

p [α

n/R + α

p]

Wp → large

R = constant

R = constant

>PHLLimit


VDD

= 3.3 VExternal load cap = 100 fFR = W

p/W

n = 2.75

Ln = L

p = 0.8 µm

0 5 10 15 20 25nMOS Channel Width W

n (µm)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

5.0

4.5

4.0

3.5

3.0

2.5

2.00 4 8 12 16 20A

rea

x τ PH

LProd

u ct (

nor m

)

minimum

VDD

= 3.3 VExternal load cap = 100 fFR = W

p/W

n = 2.75

Ln = L

p = 0.8 µm

0 5 10 15 20 25nMOS Channel Width W

n (µm)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

τ PHL (n

s)

nMOS Channel Width Wn (µm)



Taking Into Account Non-Ideal Input Waveformideal Vinnon-ideal VinVout to ideal VinVout to non-ideal Vin


1st Order RC DELAY MODELSEquivalent circuits used for MOS transistors● Ideal switch + “effective” ON resistance + load capacitance. ● Unit nMOS has “effective” ON resistance R

n= R

un/κ

n & capacitance Cd.

● Unit pMOS has “effective” ON resistance Rp = R

up/κ

p & capacitance κ

pCd;

where transistor scale factors κn ≥ 1 and κ

p ≥ 1, i.e. Wn = κnWun, Wp = κpWup

● Cgb = Cg and C

db = Csb = Cd for the unit n,pMOS transistors and scale with κn, κp.

NMOS and pMOS transistor at minimum gate length (L) ● Capacitance directly proportional to gate width (W)● Conductance directly proportional to gate width (W) ● Resistance is inversely proportional to gate width (W)

W un=W up=4<Lun=Lup=2<Example Unit Dimensions: ;

Example Unit

Transistors


1st Order RC – Elmore Delay Model

V1(t)

e−>PLH /R p C load=V DD−V 50p

V DD=1

2

V 50p=V DD

2=V DD 51−e−>PLH / Rnu C load6

>PLH=ln 526C load R p=0.69C load R p (0 -> 50%)

NOTE >D=R p C load (0 -> 63%) = 1 time constant

>PHL=ln 526C load Rn=0.69 C load RnALSO

V 15t 6=V DD51−e−t /R p C load6R

n or R

p

Cload

VDD

V1(0)

50%

50%

V 1506=V DD

>PLH>PLH

>PHL10

Step Source

t0

V 1506=0

>PLH10

Step Source

t0

>PHL

V 1506=V DD


Where Wn = κ

nW

un

nMOS 1st Order RC Delay Model – Equiv. Rn

Rn = R

un/κ

n

ASSUME: bulk and s at GND

κnCg

κnCd

κnCd

κn

ON/OFF

κn ≥ 1, usually κn = 1

Rn=Run≈V DD Lun

0.69=n Cox W un5V DD−V T0n62

Recall: >PHL≈C load V DD

k n 5V DD−V T0n62≈0.69 Rn C load

iff κn = 1


Where Wp = κ

pW

up

pMOS 1st Order RC Delay Model – Equiv. Rp

Rp = R

up/κ

p

ASSUME: bulk and s at VDD

κpCg

κpCd

κpCd

κp

ON/OFF

κp ≥ 1, usually κ

p = µn/µp

R p=Rup

; p≈

V DD Lup

0.69= p C ox; p W up5V DD−∣V T0p∣62

Recall: >PHL≈C load V DD

k p5V DD−V T0p62≈0.69 R p C load

d

s

Where, recall Lup = Lun and Wup = Wun

usually κn = 1


pMOS 1st Order RC Delay Model – Equiv. Rp → Rn

Where Wp = κ

pW

up

Rp = R

up/κ

p

ASSUME: bulk and s at VDD

κpCg

κpCd

κpCd

κp

ON/OFF

κp ≥ 1, usually κ

p = µn/µp

d

s

usually κn = 1

5W p

L p6=

=n

=p5W n

Ln6

R p≈V DD Lup

0.69= p Cox W p 5V DD−∣V T0p∣62 Rn≈

V DD Lun

0.69=n Cox W un5V DD−V T0n62

Lun=Lup

W un=W up

R p=Rup

; p≈

V DD Lup

0.69=p C ox=n

=pW up5V DD−∣V T0p∣6

2

.=Rn Iff |VT0p

| = VT0n

SYMMETRIC INVERTER


1st Order Delay Model - τPHL

κp

κp

1 1A Y

Rn

2Rnu

/κp

Cd

Cd

nCg

nκp Cg

κpCd

κpCd

VDD VDD

VDD VDD

VDDVDD

where Wn=W

unit => κ

n=1, Rn=Run

Wp = κ

pW

unit

κp = µ

n/ µ

p = 2

Y

Estimating τPHL

τPHL

Rp = R

pu/κ

p = R

n

Cs = Cd

1,κp

1,κp

1,κpn = fanout

2

1

Rp = R

n


Estimating τPHL

1st Order Delay Model - τPHL

VDDVDD

κpC

d

nκpC

g

κnC

κnC

Rn/κ

n

Reff,HL

= Rn = R

nu

Reff,LH

= Rp = R

pu/κp = R

n

Rp

Rp = R

n

Rn

Rn

Cd

Cd

Cd

τPHL

>PHL≈0.69C load∗Rn=0.69511; p65Cd1nC g 6Rn

ELMORE DELAY MODEL

nCg

nCg

YY

nκpCgκpCd

Cload

= (1 + κp)(Cd + nCg)

κpCd


Estimating τPLH

1st Order Delay Model - τPLH

τPLH

κpC

κnC

VDD VDDVDD

κnC

Reff,LH

= Rp = R

pu/κp = R

n

Y

Rp = Rn

Rn

Cd

Cd

C

C

>PLH≈0.69 C load∗Rn=0.69 511; p65C d1nC g6Rn

Y

nCg

Y

>PHL≈0.69C load∗Rn=0.69511; p65Cd1nC g 6Rn

κpC

d

κpC

d

nκpCg

nκpCg

nCg

Cload

= (1 + κp)(Cd + nCg)

Rp = Rn


>PHL≈C load 8V HL

I avg , HL=

C load 5V OH−V 50 p6I avg , HL

>PLH≈C load 8V LH

I avg , LH=

C load 5V 50 p−V OL6I avg , LH

>PLH≈0.69C load∗R p

>PHL≈0.69 C load∗Rn

Average Current Model

Differential Equation Model

1st Order RC Elmore Model

Propagation Delay Model Summary

>PHL

>PLH

%

%

>PHL≈C load V DD

k n 5V DD−V T0n62

>PLH≈C load V DD

k p 5V DD−∣V T0p∣62APPROX:


CMOS Ring Oscillator

τPHL2 τ

PHL1τ

PLH2

τPHL3

τPLH3 τ

PLH1

t

= SYM INV

SYM INV => τPHL

= τPLH


CMOS Ring Oscillator cont.

where

SYM INV => τPHL = τPLH = τp

f = 1T=

16>p


Estimation of Interconnect Parasitics


Estimation of Interconnect Parasitics cont.

Ideal FF value: FF = 1

(1 < FF < 200) FF -> Increase as t/h -> Increase, W/h <- Decrease and W/L Increase

Actual FF value: 1 < FF ≤ 20

cross-talk

(See plot of FF in Fig. 6.18 of V3 & V4 of Text)



Cmf = CoxFt = 30 aF/um2, toxF = 0.6 um and Cpa = 1 to 10 pF

cross-talk

Cmff = PP + FF PP = Cpp F/µm2 * AreaFF = CFF F/µm * Perimeter


C gb=1800aF /=m2


Cm2d

0.3=m0.9=m

0.6=m

0.6=m

0.3=m

0.6=m

0.3=m

0.6=m

(PP + FF)


S1

S2

O1

O21

23 4

5

DIGITAL CIRCUIT PATH DELAY

Delays through logic blocks Net-related delays

Fanout to other logic blocks Interconnect (wiring)


1st Order RC – Segment Delay (Elmore Delay Model)

V1(t)

10

Step Source

t0

“1” = VDD

e−>PLH /R1 C1=V DD−V 50 p

V DD= 1

2

V 50 p=V DD

2=V DD 51−e−t PLH /R1 C 16

V 1506=0

>PLH=ln 526R1 C1=0.69 R1C1 (1 -> 50%)

NOTE >D=R1 C1

(1 -> 50%)

(0 -> 63%) = 1 time constant

>PHL=ln 526R1 C1=0.69 R1C1ALSO

V 15t 6=V DD51−e−t /R1 C 16

>PLH=>PHL=0.69>D

>PLH

10

Step Source

t0

>PHL

V 1506=V DD

%

%


INTERCONNECT DELAY CALCULATIONSRC Tree Network

R1

R2

R3

R4 R

5

R6

R7

R8

C1

C2

C3

C4

C5

C6

C7

C8

1

2

3

4 5

6 7 8

S

1. Lump total wire resistance of each wire segment into single Rj between nodes in network.

2. Lump total capacitance into single node capacitor to GND.3. Model RC tree Topology:

(a) Single input node “S”; (b) All C

i between node i and GND;

4. Unique resistive path from source node S to any node k (k ≠ S).

10

Step Source

t0

V1(0)

V3(0)

V1(0)

V4(0)

V5(0)

V6(0)

V7(0)

V8(0)

Lumped RC Model for a Wire Segment

10

Step Source

t0

>PLH

>PHL


RC Tree Network

R1

R2

R3

R4 R

5

R6 R

7R

8

C1

C2

C3

C4

C5

C6

C7

C8

1

2

3

4 5

6 7 8

S

10

Step Source

>PLH=0.69>Di=0.69∑k=1

N

C k RikRik=∑ R j 3R j :[ path 5S3 i 6∩ path 5S 3 k 6]

Elmore delay at node “i”

Rik is the “shared path resistance”

where

Elmore delay at node “7”>D7=R1 C11R1C 21R1C 31R1C 41R1C515R11R66C615R11R61R76C715R11R61R76C8

R71

R72 R

73R

74 R76

R75 R

77R78

INTERCONNECT DELAY CALCULATIONS

1st Order Time-Constant Model for the Net @ node “i”.



>Di=∑k=1

N

C k Rik

Rik=∑ R j3 R j:[ path 5S3 i 6∩ path 5S 3 k 6]

>D5=?Elmore delay at node “5”:




>Di=∑k=1

N

C k Rik

Rik=∑ R j3 R j:[ path 5S3 i 6∩ path 5S 3 k 6]

>D5=R1C115R11R26C 215R11R26C315R11R21R46C415R11R21R41R56C5

1R1C61R1C71R1C8

>D5=R1C115R11R26C 215R11R26C315R11R21R46C415R11R21R41R56C5

>D1=R1 C11R1 C21R1 C31R1 C41R1 C51R1C 61R1 C71R1 C8

>D8=R1 C11R1C 21R1 C31R1 C41R1C515R11R66C615R11R61R76C7

15R11R61R71R86C8

INTERCONNECT DELAY CALCULATIONSINTERCONNECT DELAY CALCULATIONSINTERCONNECT DELAY CALCULATIONS

Elmore delay at node “5”

Elmore delay at nodes “1” and “8”

R51

R52

R53 R

54

R55

R56 R

57R

58


R1

R2

R3R

2R

N

C1

C2

C3 C

N

S 1 2 3 N O

RC Chain or Ladder Network

>DN=0.69∑k=1

N

C k RNk=∑j=1

N

C j∑k=1

j

Rk

Elmore delay at node “N”

Let the RC Ladder Network be uniform, i.e. Ri = rL/N for all i ≤ N and C

j = cL/N

for all j ≤ N such that

>DN=∑j=1

N

5 cLN

6∑k=1

j

5 rLN6= L2

N 2 5rc12 rc13rc1...1N rc6=rc L25 N112N

6

For large N, as (distributed RC line)N 3∞ >DN 3rc L2

2


Wire Length L

>PLH=0.69>DN≈0.35 r c L2


Rn, κ

nC

Rp, κ

pC

ScL/N cL/N cL/N cL/N

rL/N rL/NrL/N rL/N rL/N

>PLHwire=0.35 r c L2

>PLHtotal=>PLHinv1>PLHwire=0.69C load Rn10.35 r c L2

>PHLinv=0.69C load Rn

>PLHtotal≈>PLHinv⇒>PLHwire≪>PLHinv

Let the goal be for the layout to enable >PLHtotal≈>PLHinv

0.35 r c L2≪0.69C load Rn

L≪4 >PLHinv

0.35 r c=4 0.69C load Rn

0.35 r c

Practical Interconnect Length Rule-of-Thumb

L≤ 110 4 >PLHinv

0.35 r c= 1

10 4 0.69C load Rn

0.35 r c


vin

vout

dt

vin, v

out

Pavg=1T ∫0

Tv 5t 6i 5t 6dt

vDSn 5t 6=vout 5t 6 v SDp5t 6=V DD−vout 5t 6

Pavg≈1T∫0

T /2v DSn 5t 6 iDn 5t 6dt1 1

T ∫T /2

TvSDp5 t 6 iDp5 t 6dt

iDn5t 6=−C load

dv out

dt iDp5t 6=C load

dvout

dt

VDD

0


Pavg≈1T ∫0

T /2vout 5−C load

d vout

dt6dt1 1

T ∫T /2

T5V DD−vout 65C load

d vout

dt6dt

vin, v

out

.= 1T[−C load

vout2

2]vout=V DD

vout=0

11T[C load 5V DD vout−

vout2

26]

vout=0

vout=V DD

VDD

0

Pavg≈1T ∫V DD

0−C load vout 5t 6dvout1

1T ∫0

V DD C load 5V DD−vout 5t 66dvout



f = operating frequency or switching frequency

Pavg≈1T[−C load

vout2

2]vout=V DD

vout=0

11T[C load 5V DD vout−

v out2

26]

vout=0

vout=V DD

.= 1T

C load V DD2

C load3C total

In General:

Ctotal

= total chip capacitance

Pavg≈C load V DD2 f =F∗V 2∗Hz=Q

V∗V 2∗s−1=A∗V =W

Units calculation


EXAMPLE: Consider 0.1 µm CMOS chip with a clock rate of 100 MHz, VDD

= 2V and an average C

load = 3 fF per gate.

(a). What is the dynamic power dissipation per gate? (b). If the chip incorporates 200,000 gates, what is the power dissipation for the

chip? (a).

Pavg / gate≈3 x10−15 Fgate

∗4V2∗100 x 106 s−1=1.2=W / gate(b).

Pavg=Pavg / gate∗200,000 gates≈1.2=W / gate∗2 x 105 gates=0.24 WPESSIMISTIC -> NOT ALL 200,000 GATES SWITCH AT THE SAME TIME OR AT 100 MHZ!

Pavg≈C EFF V DD2 f C EFF=9C load

CEFF

= effective capacitance -> avg. capacitance switched per cycle at f Hz.e.g. if α = 0.2, P

avg = 0.24 W -> 48 mW



Buffer to Drive Large CLOAD

CLOAD

standard CMOS logic on die

INV1

A DESIGN STRATEGY: Make buffer (W/L)n and (W/L)

p sufficiently

large to drive CLOAD

with a specified τP.

Buffer

How do you feel about this design strategy?


Buffer to Drive Large CLOAD

CLOAD


INV1

A DESIGN STRATEGY: Make buffer (W/L)n and (W/L)

p sufficiently

large to drive CLOAD

with a specified τP.

Buffer

How do you feel about this design strategy?

Cin

What happens to Cin as (W/L)

n and (W/L)

p sufficiently large?

What is the impact on the standard CMOS logic on the die?


Super-Buffer to Drive Large CLOAD

CLOAD

CLOAD

PROBLEM: A minimum sized inverter drives a large load C

LOAD, leading to excessive delay, even

with a large buffer (large W/L).

SOLUTION: Insert N inverter stages in cascade with increasing W/L between INV1 and load C

LOAD. The total delay through N smaller stages

will be less than the delay through a single large stage driving C

LOAD.

VDD

VDD N = 3


INV1

CLOAD


INV1

Stage-0

cascadea -> stage scale factor > 1Wni = aiWn0, Lni = Ln0 and Wpi = aiWp0, Lpi = Lp0 for i = 0, 1, 2, ..., N

Stage load capacitances Cloadi are also scaled by a

Cloadi = ai Cload0

= ai (Cd + aCg) for i = 0, 1, 2, .., N

when i = N: CloadN = aN Cload0

= aN (Cd + aCg) => let CLOAD = aN(aCg) = aN+1Cg


cont.

CLOAD/Cg = aN+1 => N=ln 5C LOAD /C g 6

ln a−1

NOTE for CMOS INV:

N is rounded up to nearest integer value.

Cd = C

dbn + C

dbpC

g = C

gbn + C

gbp

CLOAD



cont.

NOTE: ALL inverters Stage-0 through Stage-N have the same gate delay

Let τ0 = gate delay for INV1 (with a = 1) in a ring oscillator with load C

load = C

d + C

g

> p=>PHL1>PLH

2=7

C load

W

For Stage-0:

CLOAD

CLOAD

>d0

>0=

C load0 /W 0

5C d1C g6/W 0=

C d1aC g

C d1C g⇒> p0=>0

C d1a C g

Cd1C g

Cd

Cd

Cd

Cd

Cd


Choose N and a to minimize τtotal

orFor Stage-0:

>p0

>0=

C load0 /W 0

5C d1C g 6/W 0=

Cd1aC g

C d1C g⇒>p0=>0

C d1aC g

C d1C g

For Stage-1: >p1

>0=

C load1 /aW 0

5C d1C g 6/W 0=5a Cd1a2 C g 6/a

Cd1C g⇒>p1=>0

Cd1aC g

C d1C g=> p0

For Stage-N:>pN

>0=

C load1 /aN W 0

5C d1C g 6/W 0=5aN C d1aN11 C g 6/a

N

C d1C g⇒>pN=>0

C d1aC g

C d1C g=>p0

TOTAL DELAY >total=5N116⋅>p0=5N116⋅>0⋅Cd1aC g

C d1C g


cont.

Cd C

d

Cd C

d

Cd

Cd

Cd

Cd

Cd

Cd

Cd

Cd

Cd

Cd

Cd

Cd

Cd


Since Cd > Cg, Cd = 0 is only an academic special case.

Wni = aiWn0 Wpi = aiWp0

aopt ≥e=2.718

>total=5N116⋅>0⋅C d1aC g

Cd1C g

N11=ln 5C LOAD/C g 6

ln a

>total=ln 5C LOAD /C g 6

ln a⋅>0⋅

Cd1aC g

C d1C g

TO MINIMIZE τtotal

:d >total

d a=>0 ln 5

C LOAD

C g6⋅[ −1/a

5ln a62C d1aC g

C d1C g1 1

ln aC g

C d1C g]=0

= 0

aopt [ ln aopt−1]=Cd

C g

ln aopt=1⇒aopt=e1=2.718

aopt2e=2.718

Since Cd > C

g, then C

d = 0 is only an academic special case.

N=ln 5C LOAD /C g 6

ln aopt−1 N is rounded up to nearest

integer value.


cont.C

d

Cd

Cd

Cd

Cd

Cd

Cd

Cd

Cd



cont.EXAMPLE: Design a Buffer using a scaled cascade of inverters to achieve minimum total delay ttotal when CLOAD = 100 Cg. Consider the case where Cd = 2Cg.

Plot using Excel, MathCad, MatLab. N11=ln 5C LOAD/C g 6

ln aopt

e3.13∗1.47=100≤C LOAD

C g≤e4∗1.47=365

3rd stage can be eliminated with little impact.

e

4.61

Cd = 2Cg => plot aopt as function of Cd/Cg: aopt = 4.35 => ln aopt = 1.47

⇒N=ln 5C LOAD /C g 6

1.47−1=2.133N =3

C LOAD≈100C g

Suitable Sub-Optimum Design?

NOTE: CLOAD/Cg = aN+1 = 82 for N = 2 = 358 >> 100 for N = 3

Cd

C g=aopt [ ln aopt−1]

Cd

Cd/C

g = 2

aopt=4.35

i Wni/Wn0 Wpi/Wp0 1 (aopt)

1 = 4.35 (aopt)1 = 4.35

2 (aopt)2 = 18.92 (aopt)

2 = 18.92

3 (aopt)3 = 82.31 (aopt)

3 = 82.31

ESE 570 MOS INVERTERS DYNAMIC CHARACTERISTICSese570/spring2015/ESE570_InvDyn15.pdf · MOS Inverter...

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Transcript of ESE 570 MOS INVERTERS DYNAMIC CHARACTERISTICSese570/spring2015/ESE570_InvDyn15.pdf · MOS Inverter...