Introduction to Embedded System I/O...

43
1 Introduction to Embedded System I/O Architectures

Transcript of Introduction to Embedded System I/O...

Page 1: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

1

Introduction to Embedded

System I/O Architectures

Page 2: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

2

I/O terminology

• Synchronous / Iso-synchronous / Asynchronous

• Serial vs. Parallel

• Input/Output/Input-Output devices

• Full-duplex/ Half-duplex

Page 3: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

3

Synchronous / Iso-synchronous /

Asynchronous

• Synchronous: Separation by a constant interval or phase difference (usually clock)

• Iso-synchronous: a special case of Synchronous when maximum time interval can be varied

• Asynchronous: data is transmitted and received at variable time intervals.

Page 4: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

4

Example

Synchronous: Frames data over LAN, inter-

processor communication

Iso-Synchronous: special mode of USB for

voice/video transfer

Asynchronous: UART Serial, modem

Page 5: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

5

Serial/Parallel

• Serial communication: Send one bit at a

time e.g. UART serial port

• Parallel communication: Send multiple bits

of data e.g. LCD connection, PCI, ISA bus

Page 6: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

6

Synchronous Serial transfer

Page 7: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

7

Typical Data Format Asynchronous

Communication

Page 8: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

8

Asynchronous Serial Transfer

Page 9: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

9

Full-Duplex and Half-Duplex

• Full-duplex: the communication can be

both ways simultaneously on a bi-directional line e.g., telephone

• Half-duplex the communication can be

only one-way on a bi-directional line e.g.,

a walkie-talkie

Page 10: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

10

Parallel Data Communication

• Typically used when the distance between

processor and other components is small,

less than a few meters

• Require high volume of data transfer

• Doesn’t mean faster transfer comparing

with serial data communication

Page 11: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

11

Parallel communication

• Advantage

High data transfer rate

• Disadvantage

– More number of wires

– Capacitive effects among wires make it applicable only with short wires

– High Capacitor results in longer delay

– Noise and cross talk effects

Page 12: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

12

Parallel port communication

Page 13: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

13

A single bus architecture was used on

early computers.

Processor

Memory

I/O

Hardware

System Bus

But Modern systems are more complex and

actually contain a hierarchy of different busses!

Page 14: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

14

An Embedded System

Page 15: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

15

Basic interfacing mechanism

• Protocols

• Arbitrations

• Addressing

Page 16: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

16

Example of read protocol

Page 17: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

17

Example of write protocol

Page 18: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

18

Basic communication protocol

• Strobe

• Handshake

Page 19: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

19

Strobe protocol

• Master assert req

signal

• Servant put data on

bus with time Taccess

• Master receive data

and deassert req

• Servant ready for next

request

Page 20: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

20

Hand-shake protocol

• Master assert req signal

• Servant put data on bus and assert ack

• Master receive data and deassert req

• Servant deassert ack after data completes

• Servant ready for next request

Page 21: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

21

Strobe and hand-shake combined

Page 22: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

22

Arbitration

• When the same set of

address/control/data lines are shared by

the different units, access to a bus is

arbitrated by a bus master

• A bus request is sent to all nodes on the

bus, the node that currently has accessed

to the bus responds with either a bus grant

or a bus busy.

Page 23: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

23

Arbitration

Page 24: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

24

System bus shared between

controllers and I/O

Page 25: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

25

Bus signals

• BR signal is a bus request signal

• BG signal is a bus grant signal

• Busy signal is a signal showing that Bus is

being used

Page 26: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

26

Methods in bus arbitration

• Daisy Chain method

• Independent Bus request and grant

method

• Polling method

Page 27: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

27

Daisy chain method

• Centralized bus arbitration process

• Bus control passes from one to the other based on priority

• BG signal will function likes a token and pass from high priority controller to lower priority controller

• At each instance of bus access, the ith controller gets the higher priority compared to bus (i+1)th

Page 28: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

28

Daisy Chain Method

Page 29: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

29

Independent request and grant

• Separate BR and BG signals

• Priority of the bus can be controlled dynamically

• Controller sends BRi and once it recieves BGi, it

issues Busy signal

• Any controller which find Busy signal will not

issue a bus request

Page 30: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

30

Independent request and grant

Page 31: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

31

Polling method

• Each controller has a predefined poll count

number

• After finish using the bus, the bus master

first sent its current poll count and keep

increment.

• On count==i, the controller i can send the

request (BR signal) and now it owns the

bus

Page 32: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

32

Polling

Page 33: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

33

Advantages/Disadvantages

• Daisy Chain Method

– Simple, control and priorities are fixed

– Can cause starvation

• Independent and grant

– Complex, require dynamic arbitration

– Nearly fair arbitration

• Polling Method

– Controller next to the bus master get highest priority

– Require polling (keep processor busy)

Page 34: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

34

Time multiplexing

Page 35: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

35

I/O addressing

• Bus-based I/O

Processor has address, data, and

control ports that form a single bus

• Port-based I/O

Processor has one ore more N-bit ports

Read and Write a port like a register

Page 36: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

36

Parallel I/O Peripheral

• Extend I/O capabilities

Page 37: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

37

Memory-mapped I/O vs. Standard I/O

Memory-mapped I/O

• Peripheral registers occupy memory space

same as memory

Standard I/O

• Additional pin indicates whether memory or

peripheral

Page 38: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

38

Memory Mapped I/O

Page 39: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

39

Standard I/O or I/O mapped I/O

Page 40: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

40

Memory-mapped I/O vs. Standard I/O

Memory-mapped I/O

• Request no special instructions

Standard I/O

• No loss of memory space

• Simpler address decoding

Page 41: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

41

I/O Transfers

• I/O devices are orders of magnitude slower than a

Processor. Handshake lines are used to synchronize each

transfer.

• I/O device sets a hardware handshake line when it is ready

to transfer data. (input ready, output ready)

• Before any data transfer, the Processor must check that the

I/O device is ready by reading the device’s handshake line.

• Handshake line bits are connected to another I/O port

(status port). Typically the next I/O address after the I/O data

port.

• When the Processor reads or writes the data port, the

handshake line is usually reset in hardware.

Page 42: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

42

Device Independent I/O

• Operating systems provide support for the

underlying I/O hardware.

• Many of the I/O devices can be supported in

applications programs by using the basic file

system API calls. (i.e. Parallel and Serial Ports)

• One important feature of an operating system is

the support it provides for file system I/O.

• It provides a uniform logical view of information

storage.

Page 43: Introduction to Embedded System I/O Architecturesesl.ait.ac.th/courses/UGMicroprocessor/class7.pdf · An Embedded System. 15 Basic interfacing mechanism • Protocols • Arbitrations

43

OS File I/O Operations

• Open (or Create): For a read operation on an existing file, the open operation searches for the file, for a write operation it searches for available space on the storage device and typically allocates buffer space to handle file transfers.

• Read: The next block of data is read from the open file. A file identifier or handle and a pointer to a buffer area in which to return the data read are arguments.

• Write: The next block of data to write to the open file. A file identifier or handle and a pointer to a buffer area from which to copy the data to write are arguments.

• Seek: Move to a specific location within a file. The argument is normally the record number to seek to. Seek is much faster than reading multiple times to move to a specific record in a file.

• Close: Close the open file. For a write operation, close flushes all write buffers and updates the directory entries for the new file.