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Introduction to CMOS VLSI Design CMOS Transistor Theory Eutectics.blogspot.in
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Introduction to CMOS VLSI Design: This Presentations is design in way to provide basic summary of CMOS Vlsi design This Presentation is Made at Eutectics.blogspot.in the following is the structure of presentation : 2: Outline 3: Introduction 4: MOS capacitor 5: Terminal Voltage 6: nMOS Cutoff 7: nMOS Linear 8: nMOS Saturation 9: I-V Characteristics 10 : Channel Charge 11: Carrier velocity 12: nMOS Linear I-V 13: nMOS Saturation 14: nMOS I-V Summary 15: Example 16: pMOS I-V 17: Capacitance 18: Gate Capacitance 19: Diffusion Capacitane 20: Pass Transistor 21: Pass transistor ckts 22: Effective Resistance 23: RC Delay Model 24: RC values 25: Inverter Delay Estimate

### Transcript of Introduction to COMS VLSI Design

• 1.Introduction to CMOS VLSI Design CMOS Transistor Theory Eutectics.blogspot.in

2. CMOS VLSI DesignEutectics.blogspot.in Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V Characteristics Gate and Diffusion Capacitance Pass Transistors RC Delay Models 3. CMOS VLSI DesignEutectics.blogspot.in Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance I = C (V/t) -> t = (C/I) V Capacitance and current determine speed Also explore what a degraded level really means 4. CMOS VLSI DesignEutectics.blogspot.in MOS Capacitor Gate and body form MOS capacitor Operating modes Accumulation Depletion Inversion polysilicon gate (a) silicon dioxide insulator p-type body + - Vg < 0 (b) + - 0 < Vg < Vt depletion region (c) + - Vg > Vt depletion region inversion region 5. CMOS VLSI DesignEutectics.blogspot.in Terminal Voltages Mode of operation depends on Vg, Vd, Vs Vgs = Vg Vs Vgd = Vg Vd Vds = Vd Vs = Vgs - Vgd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence Vds 0 nMOS body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation Vg Vs Vd Vgd Vgs Vds +- + - + - 6. CMOS VLSI DesignEutectics.blogspot.in nMOS Cutoff No channel Ids = 0 + - Vgs = 0 n+ n+ + - Vgd p-type body b g s d 7. CMOS VLSI DesignEutectics.blogspot.in nMOS Linear Channel forms Current flows from d to s e- from s to d Ids increases with Vds Similar to linear resistor + - Vgs > Vt n+ n+ + - Vgd = Vgs + - Vgs > Vt n+ n+ + - Vgs > Vgd > Vt Vds = 0 0 < Vds < Vgs -Vt p-type body p-type body b g s d b g s d Ids 8. CMOS VLSI DesignEutectics.blogspot.in nMOS Saturation Channel pinches off Ids independent of Vds We say current saturates Similar to current source + - Vgs > Vt n+ n+ + - Vgd < Vt Vds > Vgs -Vt p-type body b g s d Ids 9. CMOS VLSI DesignEutectics.blogspot.in I-V Characteristics In Linear region, Ids depends on How much charge is in the channel? How fast is the charge moving? 10. CMOS VLSI DesignEutectics.blogspot.in Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Qchannel = CV C = Cg = oxWL/tox = CoxWL V = Vgc Vt = (Vgs Vds/2) Vt n+ n+ p-type body + Vgd gate + + source - Vgs - drain Vds channel - Vg Vs Vd Cg n+ n+ p-type body W L tox SiO2 gate oxide (good insulator, ox = 3.9) polysilicon gate Cox = ox / tox 11. CMOS VLSI DesignEutectics.blogspot.in Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = E called mobility E = Vds/L Time for carrier to cross channel: t = L / v 12. CMOS VLSI DesignEutectics.blogspot.in nMOS Linear I-V Now we know How much charge Qchannel is in the channel How much time t each carrier takes to cross channel ox 2 2 ds ds gs t ds ds gs t ds Q I t W V C V V V L V V V V = = = ox= W C L 13. CMOS VLSI DesignEutectics.blogspot.in nMOS Saturation I-V If Vgd < Vt, channel pinches off near drain When Vds > Vdsat = Vgs Vt Now drain voltage no longer increases current ( ) 2 2 2 dsat ds gs t dsat gs t V I V V V V V = = 14. CMOS VLSI DesignEutectics.blogspot.in nMOS I-V Summary ( ) 2 cutoff linear saturatio 0 2 2 n gs t ds ds gs t ds ds dsat gs t ds dsat V V V I V V V V V V V V V < = < > Shockley 1st order transistor models 15. CMOS VLSI DesignEutectics.blogspot.in Example Example: a 0.6 m process from AMI semiconductor tox = 100 = 350 cm2 /V*s Vt = 0.7 V Plot Ids vs. Vds Vgs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 ( ) 14 2 8 3.9 8.85 10 350 120 / 100 10 ox W W W C A V L L L = = = 0 1 2 3 4 5 0 0.5 1 1.5 2 2.5 Vds Ids(mA) Vgs = 5 Vgs = 4 Vgs = 3 Vgs = 2 Vgs = 1 16. CMOS VLSI DesignEutectics.blogspot.in pMOS I-V All dopings and voltages are inverted for pMOS Mobility p is determined by holes Typically 2-3x lower than that of electrons n 120 cm2 /V*s in AMI 0.6 m process Thus pMOS must be wider to provide same current In this class, assume n / p = 2 17. CMOS VLSI DesignEutectics.blogspot.in Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion 18. CMOS VLSI DesignEutectics.blogspot.in Gate Capacitance Approximate channel as connected to source Cgs = oxWL/tox = CoxWL = CpermicronW Cpermicron is typically about 2 fF/m n+ n+ p-type body W L tox SiO2 gate oxide (good insulator, ox = 3.90 ) polysilicon gate 19. CMOS VLSI DesignEutectics.blogspot.in Diffusion Capacitance Csb, Cdb Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to Cg for contacted diff Cg for uncontacted Varies with process 20. CMOS VLSI DesignEutectics.blogspot.in Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing VDD Vg = VDD If Vs > VDD-Vt, Vgs < Vt Hence transistor would turn itself off nMOS pass transistors pull no higher than VDD-Vtn Called a degraded 1 Approach degraded value slowly (low Ids) pMOS pass transistors pull no lower than Vtp VDD VDD 21. CMOS VLSI DesignEutectics.blogspot.in Pass Transistor Ckts VDD VDD Vs = VDD-Vtn VSS Vs = |Vtp| VDD VDD -Vtn VDD -Vtn VDD -Vtn VDD VDD VDD VDD VDD VDD-Vtn VDD-2Vtn 22. CMOS VLSI DesignEutectics.blogspot.in Effective Resistance Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace Ids(Vds, Vgs) with effective resistance R Ids = Vds/R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay 23. CMOS VLSI DesignEutectics.blogspot.in RC Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width kg s d g s d kC kC kC R/k kg s d g s d kC kC kC 2R/k 24. CMOS VLSI DesignEutectics.blogspot.in RC Values Capacitance C = Cg = Cs = Cd = 2 fF/m of gate width Values similar across many processes Resistance R 6 K*m in 0.6um process Improves with shorter channel lengths Unit transistors May refer to minimum contacted device (4/2 ) Or maybe 1 m wide device Doesnt matter as long as you are consistent 25. CMOS VLSI DesignEutectics.blogspot.in Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter C C R 2C 2C R 2 1 A Y C 2C C 2C C 2C R Y 2 1 d = 6RC