Intel FPGA Arria 10 Reference Design Daughter Card€¦ · please refer to the Product Data Sheet...

$: Intel FPGA Arria 10 Reference Design Daughter Card€¦ · please refer to the Product Data Sheet ... Automatic fractional rate selection can be achieved with FPGA logic as ... This$
Intel FPGA Arria 10 Reference Design Daughter Card

Evaluation Board User Guide

1 of 26Semtech

Proprietary & Confidential

RDK-12GSRD-ALTRA00Evaluation Board User Guide Rev.0PDS-061487 February 2017

www.semtech.com

http://www.semtech.com/

Revision History

Contents

1. RDK-12GSRD-ALTRA00 User Guide ...........................................................................................................4

1.1 Hardware ...............................................................................................................................................4

1.1.1 Power..........................................................................................................................................5

1.1.2 Inputs and Outputs................................................................................................................5

1.1.3 Jumpers......................................................................................................................................6

1.1.4 Test Points.................................................................................................................................6

1.1.5 Assembly ...................................................................................................................................7

1.2 Integrating with Intel’s Loopback Reference Design ............................................................7

1.2.1 Device Initialization and GSPI Control ............................................................................8

1.2.2 Automatic Fractional Rate Selection...............................................................................9

1.2.3 Requirements ..........................................................................................................................9

1.3 Software .............................................................................................................................................. 10

1.3.1 Software Setup Instructions ............................................................................................ 10

2. RDK-12GSRD-ALTRA00 Schematics ....................................................................................................... 15

3. RDK-12GSRD-ALTRA00 Board Layout ................................................................................................... 22

4. RDK-12GSRD-ALTRA00 Bill of Materials................................................................................................ 24

Version ECO PCN Date Changes and/or Modifications

0 035268 — February 2017 New Document.


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OverviewTogether with the RDK-12GSRD-ALTRA00 Evaluation Board, this document serves as a guide for evaluating the GS12141 and the GS12181. The GS12141 is a Semtech 12G UHD-SDI Re-timing Adaptive Cable Equalizer. For more information on the GS12141, please refer to the Product Data Sheet (PDS-060553). The GS12181 is a Semtech 12G UHD-SDI Re-timing Cable Driver. For more information on the GS12181, please refer to the Product Data Sheet (PDS-060905). This document is partitioned into the following sections:

• RDK-12GSRD-ALTRA00 User Guide

• RDK-12GSRD-ALTRA00 Schematics

• RDK-12GSRD-ALTRA00 Board Layout

• RDK-12GSRD-ALTRA00 Bill of Materials

Figure A below shows a block diagram of the features and the functions of the RDK-12GSRD-ALTRA00.

The board includes one 12G SDI input connector, one GS12141 equalizer, a clock output, a GS12181 multi-rate cable driver, one 12G SDI output connector, a 27MHz crystal and a status indication LED.

The RDK-12GSRD-ALTRA00 also includes an external GSPI dongle to control the GS12141 and the GS12181 through the GSPI ports on the devices.

Figure A: Block Diagram

FMC Connector

12G-SDI EQGS12141

12G-SDI CDGS12181

LMH1981Sync stripper

LMH1983Line lock clock

LMK03328Lower jitter PLL

12G-SDI IN

12G-SDI OUT

DPx_M2C

DPx_C2M

GENLOCK IN SYNC_IN_HVF

SYNC_OUT_HVF

297MHz

27MHz

24.576MHz AUDIO_CLK

12V

3.3V

VADJ

4 pair serdes out

4 pair serdes in

GSPI_7_GPIO

16_GPIO

12V

3.3V


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1. RDK-12GSRD-ALTRA00 User Guide

1.1 HardwareFigure 1-1 shows the inputs, outputs and power connections for the RDK-12GSRD-ALTRA00 Daughter Card.

Figure 1-1: RDK-12GSRD-ALTRA00 Evaluation Board (Top View)

SDI_OUT(J2)

SDI_IN(J1)

CLOCK(J5)

GS12181

GS12141 Jumper

(J4):1–2 = FPGA Control2–3 = 297MHz/1.001NC = 297MHz

ExternalGSPIDongleInterface(J9)

1

2

3

LED(D1)


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Figure 1-2: RDK-12GSRD-ALTRA00 Evaluation Board (Bottom View)

1.1.1 PowerThe RDK-12GSRD-ALTRA00 Daughter Card obtains 3.3V from the Intel evaluation board via the FMC-FPGA connector (J6) as shown in Figure 1-2 above.

LED D1 is used to indicate if there is voltage present.

1.1.2 Inputs and OutputsThe RDK-12GSRD-ALTRA00 Daughter Card includes GS12141 and GS12181 SRD devices.

The 75Ω BNC connector J1 is an SDI input and the 75Ω BNC connector J2 is an SDI output.

The GS12141 automatically adjusts its gain to equalize and restore signals received over different lengths of coaxial cable having loss characteristics similar to Belden 1694A, and over multiple standards operating from 1Mb/s to 11.88Gb/s.

The GS12181 has programmable pre-emphasis to improve the transmitted eye quality over different cable lengths.

The GS12141 also has programmable pre-emphasis to improve the output eye quality.

FMC–FPGAConnector

(J6)


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1.1.3 JumpersBy default, jumper J4 is installed to allow the FPGA to automatically control the frame rate. See Table 1-1 below for more details.

1.1.4 Test Points

Figure 1-3: Test Points

Table 1-1: Jumper (J4)

Jumper Position Frame Rate

1 2 FPGA controlled

2 3 297MHz / 1.001

No Connect (NC) 297MHz

Table 1-2: Test Points

Test Point Function

TP1 Programmable GPIO0 for the GS12141







81 41

1

2

3

TP1, TP3, TP4

TP9, TP10, TP11, TP12


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1.1.5 Assembly

Figure 1-4: Assembly

1.2 Integrating with Intel’s Loopback Reference DesignTo achieve full functionality of the RDK-12GSRD-ALTRA00 Daughter Card some special provisions are required in Arria 10 FPGA implementation. The sections below outline these requirements. This content assumes that the FPGA design uses Intel's SDI II MegaCore receiver and transmitter IP, and was tested with Intel's "Multi Rate (up to 12G) SDI II Reference Design for Arria 10 Devices".

Figure 2-5 shows details of all signals on the FMC connector that interfaces with the RDK-12GSRD-ALTRA00 Daughter Card to the Arria 10 GX development board. Intel's SDI II Reference Design shows example usage when the Daughter Card is plugged into the FMC-B socket on the main board.

Applink Dongle

Semtech Daughter Card

Altera Evaluation Board


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1.2.1 Device Initialization and GSPI ControlAs described in an Application Note (PDS-061485), the GS12141 and GS12181 devices on the RDK-12GSRD-ALTRA00 Daughter Card may not have final production settings and may require configuration data to be written on power-up. The logic described in the Application Note performs all of the necessary initialization when correctly interfaced to the Daughter Card. This section assumes the use of the provided gspi_init_top_wrap.v sample implementation to achieve this. This module should be connected as follows to operate correctly:

gspi_init_top_wrap gspi_init_top_wrap_inst ( // reset and clocking .clk_100m (clk_fpga_b2_p ), // 100MHz clock .clk_100m_reset_n (cpu_resetn ), // synchronous reset // start, busy, done handshake .gspi_init_start (1'b1 ), .gspi_init_busy ( ), .gspi_init_done (gspi_init_done ), // GSPI interface .gspi_sclk (gspi_sclk ), .gspi_scs_n (gspi_scs_n ), .gspi_sdout (gspi_sdout ) );

assign gspi_fpga_en_n = gspi_init_done ? 1'b1 : 1'b0; assign gspi_header_en_n = gspi_init_done ? 1'b0 : 1'b1;

The GSPI control signals map to the FMC-B connector as follows (naming is based on Arria 10 GX development board schematic signal names):

// GSPI interface on FMC Port B assign fmcb_la_tx_n10 = gspi_sdout; // daughtercard's sdin assign fmcb_la_tx_p10 = gspi_sclk; // daughtercard needs to tie the two CSs together post level // shifter, so must drive with same value to prevent contention assign fmcb_la_tx_p16 = gspi_scs_n[0]; // gspi_scs_n_gs12141; assign fmcb_la_tx_n15 = gspi_scs_n[0]; // gspi_scs_n_gs12181; assign fmcb_la_rx_p9 = gspi_header_en_n; assign fmcb_la_rx_n9 = gspi_fpga_en_n;

Note: The gspi_fpga_en_n and gspi_header_en_n signals must be driven with opposite values to prevent signal contention on the Daughter Card. When driven as shown above, an External GSPI Dongle can still be connected to the J9 header on the Daughter Card, and the GSPI Initialization IP will take control of the GSPI bus for the required initialization.

Also, as shown above, the chip select signals going to the GS12141 and GS12181 devices must be driven with the same value to prevent contention on the Daughter Card.


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1.2.2 Automatic Fractional Rate SelectionWhole frame rates, also known as PAL frame rates, can be any of: 24, 25, 30, 50, 60 frames per second. Above SD-SDI serial rates, they are transmitted over SDI bit rates that are a multiple of 1.485Gb/s, and Intel's SDI II MegaCore transmitter requires a Tx reference clock of 297MHz.

Fractional frame rates, also known as NTSC frame rates, are typically 23.98, 29.97, or 59.94 video frames per second, or (whole rate)/1.001. Above SD-SDI serial rates, they are transmitted over SDI bit rates that are a multiple of 1.485Gbps/1.001, and Intel's SDI II MegaCore transmitter requires a Tx reference clock of 297MHz/1.001.

RDK-12GSRD-ALTRA00 Daughter Card can generate both 297MHz and 297MHz/1.001 Tx reference clock for the FPGA's use (fed to the Arria 10 GX development board differentially over pins D4 and D5 of the FMC connector). The rate can be manually selected using jumper J4 (see Figure 1-1 and Table 1-1). For any change in this setting to take effect, the LMK03328 PLL must be power-cycled by toggling its PDN pin.

Automatic fractional rate selection can be achieved with FPGA logic as follows:

• Set J4 jumper in 1-2 position to enable FPGA control. This makes the control available on pin G27 of FMC connector, which is connected to the FPGA on main board

• In the FPGA design, connect this pin to the inverse of sdi_rx_clkout_is_ntsc_paln output of the SDI II MegaCore receiver, as an open-collector output. Corresponding Verilog code could look like this:

assign lmk03328_ntsc_clk_n = ~sdi_rx_clkout_is_ntsc_paln; assign fmcb_la_rx_p10 = lmk03328_ntsc_clk_n ? 1'bz : 1'b0;

• The LMK03328 PLL's power-down (PDN) input is connected to pin H34 of FMC connector. In the FPGA design, wait for any changes on sdi_rx_clkout_is_ntsc_paln and sdi_rx_frame_locked outputs from the SDI II MegaCore receiver. When observed, toggle the PDN signal LOW than HIGH, also driving the output as an open-collector. Corresponding Verilog code could look like this:

reset_on_toggle #( .RESET_DEFAULT_STATE (1'b0) ) lmk_autorst_inst ( .clk (clk_fpga_b2_p ), .clk_reset_n (cpu_resetn ), .observed (sdi_rx_clkout_is_ntsc_paln_forced^rx_frame_locked), .out_reset_n (lmk03328_powerdown_n ) ); assign fmcb_la_tx_p15 = lmk03328_powerdown_n ? 1'bz : 1'b0;

1.2.3 RequirementsFor this automatic fractional rate selection functionality to work, the following configuration is required:

• SDI II MegaCore's receiver's rx_core_refclk and rx_cdr_refclk must be connected to 148.5MHz clock. In the Reference Design this is achieved by setting SDI REFCLK frequency on the Arria 10 GX development board to 148.5MHz (SW6.3 must be OFF)

• SDI II MegaCore's receiver's sdi_rx_coreclk_is_ntsc_paln input must be set to '0'


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1.3 SoftwareThis guide provides instructions for using the software associated with the RDK-12GSRD-ALTRA00 Reference Design Board.

1.3.1 Software Setup InstructionsUpon execution of the setup file, the following window will appear as shown in Figure 1-5. To install the software you must click next and follow the steps listed in the setup window.

Figure 1-5: RDK-12GSRD-ALTRA00 Software Installation Window

After accepting the EULA, the following dialogue box will be displayed, which provides some additional information on the installation.

Figure 1-6: Important Installation Information


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If the Microsoft Visual C++ 2010 Redistributable is not already installed, you will be prompted to accept the license agreement, as shown in Figure 1-7 below.

Figure 1-7: Microsoft EULA Installation

Once installation is complete, the following dialogue will appear. There is an option to launch the application immediately following installation.

Figure 1-8: Software Requirements


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Figure 1-9: Select Destination Folder

Figure 1-10: Select Start Menu Folder


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Figure 1-11: Select Additional Tasks

Figure 1-12: Ready To Install


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Figure 1-13: Installation Complete

Evaluation Board User Guide Rev.0PDS-061487 February 2017

SemtechProprietary & Confidential



2. RDK-12GSRD-ALTRA00 Schematics

Figure 2-1: SDI In

Inst

all R

49 &

R3

todi

sabl

e rfc

lk_i

n

CHAN

GED

R33

TO

0R

UPD

ATE

PORT

DIR

ECTI

ON

SCH

ANGE

D R

32 T

O 0

R

Def

ault

to h

ave

his G

SPI p

ath

enab

led

Adde

d FP

GA c

ontr

ol to

the

GSPI

pat

h by

Repl

aced

resis

tor R

57 to

10K

VCC_

1.8V

VCC_

1.8V

V_A

DJ

V_A

DJ

VCC_

1.8V

VCC_

1.8V

VCC_

1.8V

V_A

DJ

VCC_

1.8V

V_A

DJ

GSP

I_SD

IN

GSP

I_SC

LKG

SPI_

CS_G

S121

41

FMC_

GSP

I_SD

INFM

C_G

SPI_

SCLK

FMC_

GSP

I_CS

_GS1

2141

FMC_

GSP

I_CS

_GS1

2181

FMC_

GS1

2141

_GPI

O0

FMC_

GS1

2141

_GPI

O2

FMC_

GS1

2141

_GPI

O3

GSP

I_SD

OU

T

REF_

CLK_

OU

TG

SPI_

OU

T_IN

FMC_

GS1

2141

_OU

T+

FMC_

GS1

2141

_OU

T-

FMC_

GSP

I_SD

OU

T

GSP

I_SC

LKG

SPI_

SDIN

GSP

I_CS

_GS1

2181

GSP

I_CS

_GS1

2141

FMC_

GSP

I_O

En

C74.

7μF

C6 10nF

R522

Ω

C5 10nF

TP22

GPI

O2

C15

470n

F

C14

0.1μ

F

C1 10nF

U2

TXB0

304

VCCA

1

A1

2

A2

3

A3

4

A4

5

GND 6

B47

B38

B29

B110

VCCB

11

OE12

C13

0.1μ

F

R622

Ω

C4 10nF

R57

10kΩ

R3 NC/

100k

Ω

C2 10nF

C16

1μF

R230

kΩ

R722

Ω

TP3

GPI

O2

U3

74A

VC4T

D24

5BQ

VCCA

1

A1

3

A2

4

A3

5

A4

6

GN

D8

OE

9

B411

B312

B213

B114

VCCB

16

TAB

17

DIR

12

DIR

215

DIR

310

DIR

47

U1

GS1

2141

VEE_SDI11

SDI

2

SDI

3

VCC_SDI4

NC3

5

NC1

6

NC2

7

VEE_SDI28

NC4

9

CS10

SDIN

11

SDO

UT

12

SCLK

13

VSS114

VSS215

VDD16

GPI

O0

17

GPI

O1

18

VEE_CORE119

VCC_CORE120 VEEO1

21

DD

O1/

RCO

22

DD

O1/

RCO

23

VCCO_124 VCCO_025

DD

O0

26

DD

O0

27

VEEO228

VCC_CORE229

NC5

30

VEE_CORE231

REF_

CLK

32

GPI

O2

33

VCO

_FIL

T34

VCC_CORE335

GPI

O3

36

VEE_CORE337

VEE_CORE438

LF+

39

LF-

40

TABTAB

R1 0Ω

R32

0Ω

TP1

GPI

O1

X1

ASD

MB

EN1

GN

D2

outp

ut3

VDD

4

C3 10nF

C9

4.7μ

F

TP4

GPI

O3

C84.

7μF

TP5

GSP

I_SD

IN

R49

NC/

100k

Ω

R48

10kΩ

TP6

GSP

I_SC

LK

TP7

GSP

I_CS

_GS1

2141

J1Ca

mbr

idge

C-S

X-14

1 ed

ge

1

32

R422

Ω

C10

10nF

C11

4.7μ

F

R33

0Ω

C12

10nF

TP8

GSP

I_CS

_GS1

2181

TP2

GSP

I_SD

OU

T

C18

0.1μ

F

27M

Hz_

CLK_

IN




Figure 2-2: SDI Out

Def

ault

to h

ave

his G

SPI p

ath

enab

led

Adde

d FP

GA c

ontr

ol to

the

GSPI

pat

h by

Repl

aced

resis

tor R

59 to

10K

VCC_

1.8V

V_A

DJ

VCC_

1.8V

VCC_

1.8V

VCC_

2.5V

3.3V

VCC_

1.8V

3.3V

_A

VCC_

1.8V

VCC_

2.5V

GSP

I_O

UT_

IN

GSP

I_SC

LKG

SPI_

CS_G

S121

81

FMC_

GS1

2181

_IN

+

FMC_

GS1

2181

_IN

-

REF_

CLK_

OU

T

I2C_

SCL

I2C_

SDA

GSP

I_SD

OU

T

FMC_

GS1

2181

_GPI

O2

FMC_

GS1

2181

_GPI

O0

FMC_

GS1

2181

_GPI

O3

FMC_

GS1

2181

_GPI

O1

GSP

I_SD

ING

SPI_

SCLK

GSP

I_CS

_GS1

2181

GSP

I_CS

_GS1

2141

GSP

I_SD

OU

T

GSP

I_O

En

C20

10nF

TP10

GPI

O5

C29

4.7μ

F

R43

0Ω

C32

0.1μ

F

C33

470n

F

C21

10nF

TP11

GPI

O6

R41

0Ω

R44

0Ω

C30

10nF

C22

10nF

TP12

GPI

O7

C34

1μF

C109

0.1μ

F

R54

0Ω

TP13

GPI

O0

C26

4.7μ

F

U17

74A

VC4T

D24

5BQ

VCCA

1

A1

3

A2

4

A3

5

A4

6

GN

D8

OE

9

B411

B312

B213

B114

VCCB

16

TAB

17

DIR

12

DIR

215

DIR

310

DIR

47

R36

0Ω

J9

FCI9

8414

G06

16U

LF

1 3 5 7 9 11 13 15

2 4 6 8 10 12 14 16

R38

0Ω

R42

DN

P

TP21

GPI

O1

C23

10nF

C107 0.

1μF

C27

4.7μ

F

R39

0Ω

R34

5Ω

R55

0Ω

R930

kΩ

R40

10kΩ

C24

10nF

C108

0.1μ

F

R875

Ω

R59

10kΩ

U4

GS1

2181

VEE_DDI11

NC1

2

NC2

3

VCC_DDI4

TERM

5

DD

I6

DD

I7

VEE_DDI28

NC3

9

CS10

SDIN

11

SDO

UT

12

SCLK

13

VSS114

VSS215

VDD16

GPI

O0

17

GPI

O1

18

VEE_CORE119

VCCO1P8_120

VEEO221

SDO

122

SDO

123

VCCO_124 VCCO_025

SDO

026

SDO

027

VEEO128

VCCO1P8_029

NC4

30

VEE_CORE231

REF_

CLK

32

GPI

O2

33

VCO

_FIL

T34

VCC_CORE35

GPI

O3

36

VEE_CORE337

VEE_CORE438

LF+

39

LF-

40

TABTAB

C19

10nF

U5

TXB0

304

VCCA

1

A1

2

A2

3

A3

4

A4

5

GND6

B47

B38

B29

B110

VCCB

11

OE12

J2 Cam

brid

ge C

-SX-

141

edge

1

32

C25

10nF

R35

0Ω TP15

GPI

O0

R56

0Ω

C28

4.7μ

F

C31

0.1μ

F

TP9

GPI

O4

R37

DN

P


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Figure 2-3: Clock Circuit, Genlock

3.3V

_A

3.3V_PLL2

3.3V_PLL1

3.3V

_A

3.3V_OUT1

3.3V

_A

3.3V

_A

3.3V

_A3.

3V_P

LL2

3.3V

_A3.

3V_P

LL1

3.3V

_A3.

3V_O

UT1

3.3V

_A

3.3V

_A3.

3V_A

3.3V

_A

3.3V

_A

FPG

A_H

SYN

CnFP

GA

_VSY

NCn

FPG

A_F

LDn

LMH

1983

_IN

IT

I2C_

SCL

I2C_

SDA

FMC_

AU

DIO

_CLK

+FM

C_A

UD

IO_C

LK-

LMH

1983

_NO

_REF

LMH

1983

_NO

_ALI

GN

LMH

1983

_NO

_LO

CK

LMH

1981

_FLD

2n

LMH

1981

_HSY

NCn

LMH

1981

_VSY

NCn

LMH

1981

_VID

EO_F

MT

LMK0

3328

_PD

N

I2C_

SDA

I2C_

SCL

27M

Hz

CLK_

297M

Hz+

CLK_

297M

Hz-

CLK_

RATE

_SEL

L1

BLM

15A

G22

1SN

1D

C80

0.1μ

F

C101 0.1μF

C77

0.1μ

F

J4

CON

3

1 2 3

C43 0.1μF

C51

33nF

U6

LMH

1983

VDD

11

VDD

22

HIN

3

VIN

4

FIN

5

INIT

6

AD

DR

7

SDA

8SC

L9

VDD

310

NO

_LO

CK11

NO

_ALI

GN

12

NO

_REF

13

CLKO

UT4

-14

CLKO

UT4

+15

VDD

616

FOU

T4(O

SCin

)17

GN

D1

18

VDD

419

VDD

520

GN

D2

21

FOU

T322

CLKO

UT3

+23

CLKO

UT3

-24

CBYP

325

CBYP

426

CBYP

227

CLKO

UT2

+28

CLKO

UT2

-29

FOU

T230

VDD

731

VDD

832

XOin

-33

XOin

+34

CLKO

UT1

-35

CLKO

UT1

+36

FOU

T137

VDD

938

GN

D3

39

VC_L

PF40

DA

P41

C56

0.1μ

F

C38

0.1u

F

C60

1μF

L3

BLM

15A

G22

1SN

1D

R11

3kΩ

U8

LMP7

711M

K

OU

TPU

T1

V-2

+IN

3

-IN4

EN5

V+6

C44 0.1μF

C41

0.1μ

F

C52

33nF

C102 0.1μF

R15

10kΩ

C57

1μF

C75

10μF

C53

47μF

C54

0.1μ

F

C50

10μF

C74

0.1μ

F

C36

10uF

R10

3kΩ

C68

0.1μ

F

C76

0.1μ

F

C61

0.1μ

F

C72

10μF

C70

1μF

C64

0.1μ

F

C45

0.1μ

F

C98 0.1μF

X2

357L

B3C0

27M1

1EO

H2

GN

D3

OU

TPU

T4

NC

5

VCC

6

J5

Cam

brid

ge C

-SX-

141

edge

1

32

C40 0.1μF

C67

0.1μ

F

C55

1μF

C73

0.1μ

F

C49

10μF

C46

0.1μ

F

L2

BLM

15A

G22

1SN

1D

C58

0.1μ

F

C78

10μF

U9

LMH

1981RE

XT1

GN

D1

2

VCC1

3

VIN

4

GN

D2

5

VCC2

6H

SOU

T7

VSO

UT

8

VFO

UT

9

GN

D3

10

VCC3

11

CSO

UT

12

BPO

UT

13

OEO

UT

14C99 0.1μF

R12

17.4

kΩ

C39 0.1μF

R60

10kΩ

R16

75Ω

C63

0.1μ

FC6

50.

1μF

C66

22μF

R13

10kΩ

U7

LMK0

3328ST

ATU

S01

STA

TUS1

2

CAP_

DIG

3

VDD

_DIG

4

VDD

_IN

5

PRIR

EF_P

6

PRIR

EF_N

7

REFS

EL8

HW

_SW

_CTR

L9

SECR

EF_P

10

SECR

EF_N

11

GPI

O0

12

PDN

13

OU

T0_P

14

OU

T0_N

15

OU

T1_N

16

OU

T1_P

17

VDD

O_0

118

VDD

O_2

319

OU

T2_P

20

OU

T2_N

21

OU

T3_N

22

OU

T3_P

23

GPI

O1

24

SDA

25

SCL

26

VDD

_PLL

227

CAP_

PLL2

28

LF2

29

GPI

O2

30

GPI

O3

31

GPI

O4

32

GPI

O5

33

LF1

34

CAP_

PLL1

35

VDD

_PLL

136

VDD

O_4

37

OU

T4_N

38

OU

T4_P

39

VDD

O_5

40

OU

T5_N

41

OU

T5_P

42

VDD

O_6

43

OU

T6_N

44

OU

T6_P

45

VDD

O_7

46

OU

T7_N

47

OU

T7_P

48

PAD

49

C59

1μF

C71

0.1μ

F

C100 0.1μF

C79

0.1μ

F

C42 22μF

C37

0.1u

F

C48

10μF

C47

0.1μ

F

C62

22μF

R14

10kΩ

C69

0.1μ

F


17 of 26Semtech


www.semtech.com



Figure 2-4: Level Translators

I2 C Le

vel S

hift

V_A

DJ t

o 3.

3V T

rans

latio

n

3.3V

_A

V_A

DJ

V_A

DJ

3.3V

_A

V_A

DJ

3.3V

_A

V_A

DJ

3.3V

_A

V_A

DJ

3.3V

_A 3.3V

_A

FMC_

FPG

A_H

SYN

CnFM

C_FP

GA

_VSY

NCn

FMC_

FPG

A_F

LDn

FMC_

LMH

1983

_IN

IT

FPG

A_H

SYN

CnFP

GA

_VSY

NCn

FPG

A_F

LDn

LMH

1983

_IN

IT

FMC_

I2C_

SDA

FMC_

I2C_

SCL

FMC_

LMH

1981

_HSY

NCn

FMC_

LMH

1981

_VSY

NCn

FMC_

LMH

1981

_VID

EO_F

MT

FMC_

LMH

1981

_FLD

2n

I2C_

SCL

I2C_

SDA

LMH

1981

_HSY

NCn

LMH

1981

_VSY

NCn

LMH

1981

_VID

EO_F

MT

LMH

1981

_FLD

n

LMH

1983

_NO

_REF

LMH

1983

_NO

_ALI

GN

LMH

1983

_NO

_LO

CKFM

C_LM

H19

83_N

O_R

EFFM

C_LM

H19

83_N

O_A

LIG

NFM

C_LM

H19

83_N

O_L

OCK

FPG

A_S

TATU

S1FM

C_FP

GA

_STA

TUS1

C81

0.1μ

F

R17

22Ω

R24

4.75

kΩ

C84

0.1μ

F

R21

4.75

kΩ

U14 PC

A93

06D

CUR

GN

D1

VREF

12

SCL1

3

SDA

14

SDA

25

SCL2

6

VREF

27

EN8

U10

74A

VC4T

D24

5BQ

VCCA

1

A1

3

A2

4

A3

5

A4

6

GN

D8

OE

9

B411

B312

B213

B114

VCCB

16

TAB

17

DIR

12

DIR

215

DIR

310

DIR

47

J3CO

N3

11

22

33

vss1

4

vss2

5

U13

74A

VC4T

D24

5BQ

VCCA

1

A1

3

A2

4

A3

5

A4

6

GN

D8

OE

9

B411

B312

B213

B114

VCCB

16

TAB

17

DIR

12

DIR

215

DIR

310

DIR

47

R18

22Ω

R22

4.75

kΩ

C82

0.1μ

F

TP18

HSY

NC

R19

22Ω

R47

10kΩ

R45

10kΩ

TP19

VSYN

C

R23

4.75

kΩ

R20

22Ω

U11

74A

VC4T

D24

5BQ

VCCA

1

A1

3

A2

4

A3

5

A4

6

GN

D8

OE

9

B411

B312

B213

B114

VCCB

16

TAB

17

DIR

12

DIR

215

DIR

310

DIR

47

C86

0.1μ

F

C85

0.1μ

F

TP20

FLD

2n

R46

10kΩ

3.3V

to V

_AD

J Tra

nsla

tion




Figure 2-5: FMC Connector

Key

feat

ures

of t

he F

MC

spec

ifica

tion

incl

ude:

• Up

to 2

0 hi

gh-s

peed

diff

eren

tial p

airs

sup

port

ing

10G

b/s

sign

alin

g.• 4

diff

eren

tial c

lock

s su

ppor

ting

2GH

z si

gnal

ing.

• 80

diffe

rent

ial I

/O o

r 160

sin

gle

ende

d ge

nera

l pur

pose

I/O

.• I

PMI p

rogr

amm

ing

and

card

info

rmat

ion

acce

ss.

• Sup

port

for u

ser s

elec

tabl

e I/O

vol

tage

sta

ndar

ds.

3.3V

12V

V_A

DJ

V_A

DJ

V_A

DJ

V_A

DJ

3.3V

FMC_

AU

DIO

_CLK

+FM

C_A

UD

IO_C

LK-

CLK_

297M

Hz-

CLK_

297M

Hz+

FMC_

I2C_

SDA

FMC_

I2C_

SCL

FPG

A_S

TATU

S1

LMK0

3328

_PD

N

FMC_

LMH

1981

_HSY

NCn

FMC_

LMH

1981

_VSY

NCn

FMC_

LMH

1981

_VID

EO_F

MT

FMC_

LMH

1981

_FLD

2n

FMC_

FPG

A_H

SYN

CnFM

C_FP

GA

_VSY

NCn

FMC_

FPG

A_F

LDn

FMC_

LMH

1983

_IN

IT

FMC_

LMH

1983

_NO

_REF

FMC_

LMH

1983

_NO

_ALI

GN

FMC_

LMH

1983

_NO

_LO

CK

FMC_

GSP

I_SD

OU

T

FMC_

GS1

2141

_GPI

O0

FMC_

GS1

2141

_GPI

O2

FMC_

GS1

2141

_GPI

O3

FMC_

GSP

I_SD

INFM

C_G

SPI_

SCLK

FMC_

GSP

I_CS

_GS1

2141

FMC_

GSP

I_CS

_GS1

2181

FMC_

GS1

2181

_GPI

O0

FMC_

GS1

2181

_GPI

O2

FMC_

GS1

2181

_GPI

O1

FMC_

GS1

2181

_GPI

O3

FMC_

120_

GSP

I_SD

INFM

C_12

0_G

SPI_

SDO

UT

FMC_

120_

GPI

O13

FMC_

120_

GPI

O14

FMC_

120_

GSP

I_CL

KFM

C_12

0_G

SPI_

CS1

FMC_

120_

GPI

O9

FMC_

120_

GPI

O10

FMC_

120_

GSP

I_CS

2FM

C_12

0_G

SPI_

CS3

FMC_

120_

GSP

I_CS

4

FMC_

120_

GPI

O5

FMC_

120_

GPI

O6

FMC_

120_

GPI

O1

FMC_

120_

GPI

O2

FMC_

120_

GPI

O3

FMC_

120_

GPI

O4

FMC_

120_

GPI

O7

FMC_

120_

GPI

O8

FMC_

120_

GPI

O11

FMC_

120_

GPI

O12

FMC_

120_

GPI

O15

FMC_

120_

GPI

O16

FMC_

12G

_IN

4-FM

C_12

G_I

N4+

FMC_

12G

_IN

3-FM

C_12

G_I

N3+

FMC_

12G

_IN

2-FM

C_12

G_I

N2+

FMC_

12G

_OU

T2-

FMC_

12G

_OU

T2+

FMC_

12G

_OU

T3-

FMC_

12G

_OU

T3+

FMC_

12G

_OU

T4-

FMC_

12G

_OU

T4+

FMC_

GS1

2141

_OU

T+FM

C_G

S121

41_O

UT-

FMC_

GSP

I_O

EnG

SPI_

OEn

FMC_

12G

_IN

1-FM

C_12

G_I

N1+

FMC_

GS1

2181

_IN

+FM

C_G

S121

81_I

N-

FMC_

12G

_OU

T1-

FMC_

12G

_OU

T1+

CLK_

RATE

_SEL

TP25

GPI

O5

J6B

asp-

1344

88-0

1_0

GN

D41

C1

DP0

_C2M

_PC2

DP0

_C2M

_NC3

GN

D42

C4

GN

D43

C5

DP0

_M2C

_PC6

DP0

_M2C

_NC7

GN

D44

C8

GN

D45

C9

LA06

_PC1

0

LA06

_NC1

1

GN

D46

C12

GN

D47

C13

LA10

_PC1

4

LA10

_NC1

5

GN

D48

C16

GN

D49

C17

LA14

_PC1

8

LA14

_NC1

9

GN

D50

C20

GN

D51

C21

LA_1

8_P_

CCC2

2

LA_1

8_N

_CC

C23

GN

D52

C24

GN

D53

C25

LA27

_PC2

6

LA27

_NC2

7

GN

D54

C28

GN

D55

C29

SCL

C30

SDA

C31

GN

D56

C32

GN

D57

C33

GA

0C3

4

12P0

V1C3

5

GN

D58

C36

12P0

V2C3

7

GN

D59

C38

3P3V

1C3

9

GN

D60

C40

PG_C

2MD

1

GN

D61

D2

GN

D62

D3

GBT

CLK0

_M2C

_PD

4

GBT

CLK0

_M2C

_ND

5

GN

D63

D6

GN

D64

D7

LA01

_P_C

CD

8

LA01

_N_C

CD

9

GN

D65

D10

LA05

_PD

11

LA05

_ND

12

GN

D66

D13

LA09

_PD

14

LA09

_ND

15

GN

D67

D16

LA13

_PD

17

LA13

_ND

18

GN

D68

D19

LA17

_P_C

CD

20

LA17

_N_C

CD

21

GN

D69

D22

LA23

_PD

23

LA23

_ND

24

GN

D70

D25

LA26

_PD

26

LA26

_ND

27

GN

D71

D28

TCK

D29

TDI

D30

TDO

D31

3P3V

AU

XD

32

TMS

D33

TRST

_LD

34

GA

1D

35

3P3V

2D

36

GN

D72

D37

3P3V

3D

38

GN

D73

D39

3P3V

4D

40

J6D

asp-

1344

88-0

1_0

GN

D10

4G

1

CLK1

_M2C

_PG

2

CLK1

_M2C

_NG

3

GN

D10

5G

4

GN

D10

6G

5

LA00

_P_C

CG

6

LA00

_N_C

CG

7

GN

D10

7G

8

LA03

_PG

9

LA03

_NG

10

GN

D10

8G

11

LA08

_PG

12

LA08

_NG

13

GN

D10

9G

14

LA12

_PG

15

LA12

_NG

16

GN

D11

0G

17

LA16

_PG

18

LA16

_NG

19

GN

D11

1G

20

LA20

_PG

21

LA20

_NG

22

GN

D11

2G

23

LA22

_PG

24

LA22

_NG

25

GN

D11

3G

26

LA25

_PG

27

LA25

_NG

28

GN

D11

4G

29

LA29

_PG

30

LA29

_NG

31

GN

D11

5G

32

LA31

_PG

33

LA31

_NG

34

GN

D11

6G

35

LA33

_PG

36

LA33

_NG

37

GN

D11

7G

38

VAD

J3G

39

GN

D11

8G

40

VREF

_A_M

2CH

1

PRSN

T_M

2C_L

H2

GN

D11

9H

3

CLK0

_M2C

_PH

4

CLK0

_M2C

_NH

5

GN

D12

0H

6

LA02

_PH

7

LA02

_NH

8

GN

D12

1H

9

LA04

_PH

10

LA04

_NH

11

GN

D12

2H

12

LA07

_PH

13

LA07

_NH

14

GN

D12

3H

15

LA11

_PH

16

LA11

_NH

17

GN

D12

4H

18

LA15

_PH

19

LA15

_NH

20

GN

D12

5H

21

LA19

_PH

22

LA19

_NH

23

GN

D12

6H

24

LA21

_PH

25

LA21

_NH

26

GN

D12

7H

27

LA24

_PH

28

LA24

_NH

29

GN

D12

8H

30

LA28

_PH

31

LA28

_NH

32

GN

D12

9H

33

LA30

_PH

34

LA30

_NH

35

GN

D13

0H

36

LA32

_PH

37

LA32

_NH

38

GN

D13

1H

39

VAD

J4H

40

J6C

asp-

1344

88-0

1_0

GN

D74

E1

HA

01_P

_CC

E2

HA

01_N

_CC

E3

GN

D75

E4

GN

D76

E5

HA

05_P

E6

HA

05_N

E7

GN

D77

E8

HA

09_P

E9

HA

09_N

E10

GN

D78

E11

HA

13_P

E12

HA

13_N

E13

GN

D79

E14

HA

16_P

E15

HA

16_N

E16

GN

D80

E17

HA

20_P

E18

HA

20_N

E19

GN

D81

E20

HB0

3_P

E21

HB0

3_N

E22

GN

D82

E23

HB0

5_P

E24

HB0

5_N

E25

GN

D83

E26

HB0

9_P

E27

HB0

9_N

E28

GN

D84

E29

HB1

3_P

E30

HB1

3_N

E31

GN

D85

E32

HB1

9_P

E33

HB1

9_N

E34

GN

D86

E35

HB2

1_P

E36

HB2

1_N

E37

GN

D87

E38

VAD

J1E3

9

GN

D88

E40

PG_M

2CF1

GN

D89

F2

GN

D90

F3

HA

00_P

_CC

F4

HA

00_N

_CC

F5

GN

D91

F6

HA

04_P

F7

HA

04_N

F8

GN

D92

F9

HA

08_P

F10

HA

08_N

F11

GN

D93

F12

HA

12_P

F13

HA

12_N

F14

GN

D94

F15

HA

15_P

F16

HA

15_N

F17

GN

D95

F18

HA

19_P

F19

HA

19_N

F20

GN

D96

F21

HB0

2_P

F22

HB0

2_N

F23

GN

D97

F24

HB0

4_P

F25

HB0

4_N

F26

GN

D98

F27

HB0

8_P

F28

HB0

8_N

F29

GN

D99

F30

HB1

2_P

F31

HB1

2_N

F32

GN

D10

0F3

3

HB1

6_P

F34

HB1

6_N

F35

GN

D10

1F3

6

HB2

0_P

F37

HB2

0_N

F38

GN

D10

2F3

9

VAD

J2F4

0

J6A

asp-

1344

88-0

1_0

GN

D1

A1

DP1

_M2C

_PA

2

DP1

_M2C

_NA

3

GN

D2

A4

GN

D3

A5

DP2

_M2C

_PA

6

DP2

_M2C

_NA

7

GN

D4

A8

GN

D5

A9

DP3

_M2C

_PA

10

DP3

_M2C

_NA

11

GN

D6

A12

GN

D7

A13

DP4

_M2C

_PA

14

DP4

_M2C

_NA

15

GN

D8

A16

GN

D9

A17

DP5

_M2C

_PA

18

DP5

_M2C

_NA

19

GN

D10

A20

GN

D11

A21

DP1

_C2M

_PA

22

DP1

_C2M

_NA

23

GN

D12

A24

GN

D13

A25

DP2

_C2M

_PA

26

DP2

_C2M

_NA

27

GN

D14

A28

GN

D15

A29

DP3

_C2M

_PA

30

DP3

_C2M

_NA

31

GN

D16

A32

GN

D17

A33

DP4

_C2M

_PA

34

DP4

_C2M

_NA

35

GN

D18

A36

GN

D19

A37

DP5

_C2M

_PA

38

DP5

_C2M

_NA

39

GN

D20

A40

RES1

B1

GN

D21

B2

GN

D22

B3

DP9

_M2C

_PB4

DP9

_M2C

_NB5

GN

D23

B6

GN

D24

B7

DP8

_M2C

_PB8

DP8

_M2C

_NB9

GN

D25

B10

GN

D26

B11

DP7

_M2C

_PB1

2

DP7

_M2C

_NB1

3

GN

D27

B14

GN

D28

B15

DP6

_M2C

_PB1

6

DP6

_M2C

_NB1

7

GN

D29

B18

GN

D30

B19

GBT

CLK1

_M2C

_PB2

0

GBT

CLK1

_M2C

_NB2

1

GN

D31

B22

GN

D32

B23

DP9

_C2M

_PB2

4

DP9

_C2M

_NB2

5

GN

D33

B26

GN

D34

B27

DP8

_C2M

_PB2

8

DP8

_C2M

_NB2

9

GN

D35

B30

GN

D36

B31

DP7

_C2M

_PB3

2

DP7

_C2M

_NB3

3

GN

D37

B34

GN

D38

B35

DP6

_C2M

_PB3

6

DP6

_C2M

_NB3

7

GN

D39

B38

GN

D40

B39

RES0

B40

TP23

GPI

O3

C103

10μF

TP24

GPI

O4

J6E

asp-

1344

88-0

1_0

GN

D13

2J1

CLK3

_M2C

_PJ2

CLK3

_M2C

_NJ3

GN

D13

3J4

GN

D13

4J5

HA

03_P

J6

HA

03_N

J7

GN

D13

5J8

HA

07_P

J9

HA

07_N

J10

GN

D13

6J1

1

HA

11_P

J12

HA

11_N

J13

GN

D13

7J1

4

HA

14_P

J15

HA

14_N

J16

GN

D13

8J1

7

HA

18_P

J18

HA

18_N

J19

GN

D13

9J2

0

HA

22_P

J21

HA

22_N

J22

GN

D14

0J2

3

HB0

1_P

J24

HB0

1_N

J25

GN

D14

1J2

6

HB0

7_P

J27

HB0

7_N

J28

GN

D14

2J2

9

HB1

1_P

J30

HB1

1_N

J31

GN

D14

3J3

2

HB1

5_P

J33

HB1

5_N

J34

GN

D14

4J3

5

HB1

8_P

J36

HB1

8_N

J37

GN

D14

5J3

8

VIO

_B_M

2C_1

J39

GN

D14

6J4

0

VREF

_B_M

2CK1

GN

D14

7K2

GN

D14

8K3

CLK2

_M2C

_PK4

CLK2

_M2C

_NK5

GN

D14

9K6

HA

02_P

K7

HA

02_N

K8

GN

D15

0K9

HA

06_P

K10

HA

06_N

K11

GN

D15

1K1

2

HA

10_P

K13

HA

10_N

K14

GN

D15

2K1

5

HA

17_P

_CC

K16

HA

17_N

_CC

K17

GN

D15

3K1

8

HA

21_P

K19

HA

21_N

K20

GN

D15

4K2

1

HA

23_P

K22

HA

23_N

K23

GN

D15

5K2

4

HB0

0_P_

CCK2

5

HB0

0_N

_CC

K26

GN

D15

6K2

7

HB0

6_P_

CCK2

8

HB0

6_N

_CC

K29

GN

D15

7K3

0

HB1

0_P

K31

HB1

0_N

K32

GN

D15

8K3

3

HB1

4_P

K34

HB1

4_N

K35

GN

D15

9K3

6

HB1

7_P_

CCK3

7

HB1

7_N

_CC

K38

GN

D16

0K3

9

VIO

_B_M

2C_2

K40


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Figure 2-6: Expansion Connector

3.3V

12V

12V

3.3V

12V

3.3V

3.3V

12V

FMC_

120_

GPI

O14

FMC_

120_

GPI

O3

FMC_

120_

GSP

I_SD

OU

T

FMC_

120_

GPI

O13

FMC_

120_

GPI

O5

FMC_

120_

GSP

I_SD

INFM

C_12

0_G

PIO

6

FMC_

120_

GPI

O12

FMC_

120_

GSP

I_CS

3FM

C_12

0_G

SPI_

CS2

FMC_

120_

GSP

I_CS

4

FMC_

120_

GPI

O7

FMC_

120_

GPI

O4

FMC_

120_

GSP

I_CS

1

FMC_

120_

GPI

O2

FMC_

120_

GPI

O8

FMC_

120_

GPI

O11

FMC_

120_

GPI

O15

FMC_

120_

GPI

O16

FMC_

120_

GPI

O1

FMC_

120_

GSP

I_CL

K

FMC_

120_

GPI

O10

FMC_

120_

GPI

O9

FMC_

12G

_IN

2-FM

C_12

G_I

N2+

FMC_

12G

_IN

1-FM

C_12

G_I

N1+

FMC_

12G

_IN

4-FM

C_12

G_I

N4+

FMC_

12G

_IN

3-FM

C_12

G_I

N3+

FMC_

12G

_OU

T1-

FMC_

12G

_OU

T1+

FMC_

12G

_OU

T2-

FMC_

12G

_OU

T2+

FMC_

12G

_OU

T3-

FMC_

12G

_OU

T3+

FMC_

12G

_OU

T4-

FMC_

12G

_OU

T4+

J7B

SMTV

HD

R4X3

0SEA

M8

C1C1

C2C2

C3C3

C4C4

C5C5

C6C6

C7C7

C8C8

C9C9

C10

C10

C11

C11

C12

C12

C13

C13

C14

C14

C15

C15

C16

C16

C17

C17

C18

C18

C19

C19

C20

C20

D1

D1

D2

D2

D3

D3

D4

D4

D5

D5

D6

D6

D7

D7

D8

D8

D9

D9

D10

D10

D11

D11

D12

D12

D13

D13

D14

D14

D15

D15

D16

D16

D17

D17

D18

D18

D19

D19

D20

D20

J7A

SMTV

HD

R4X3

0SEA

M8

A1

A1

A2

A2

A3

A3

A4

A4

A5

A5

A6

A6

A7

A7

A8

A8

A9

A9

A10

A10

A11

A11

A12

A12

A13

A13

A14

A14

A15

A15

A16

A16

A17

A17

A18

A18

A19

A19

A20

A20

B1B1

B2B2

B3B3

B4B4

B5B5

B6B6

B7B7

B8B8

B9B9

B10

B10

B11

B11

B12

B12

B13

B13

B14

B14

B15

B15

B16

B16

B17

B17

B18

B18

B19

B19

B20

B20


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Figure 2-7: Power Supplies

3.3V

3.3V

_A

3.3V

VCC_

1.8V

3.3V

VCC_

2.5V

C93

22μF

C88

22μF

R26

10kΩ

R29

10kΩ

C106

10μF

U15

SC42

12

NC1

1

EN2

VIN

3

NC2

4

NC3

5

VOU

T6

FB7

GND8PAD9

R28

100k

Ω

D1

YELL

OW

LED

C87

22μF

R30

100k

Ω

C91

0.1μ

F

R25

1kΩ

C97

10μF

C92

0.1μ

F

J10

WEI

DM

ULL

ER-1

5126

6

1 2

U16

SC42

12

NC1

1

EN2

VIN

3

NC2

4

NC3

5

VOU

T6

FB7

GND8PAD9

R31

400k

Ω

C96

0.1μ

F

C90

0.1μ

F

C89

0.1μ

F

C94

22μF

C104

4.7μ

F

L4

NRS

5020

T4R7

MM

GJ

C105

0.1μ

F

C95

4.7μ

FR2

726

0kΩ


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3. RDK-12GSRD-ALTRA00 Board Layout

Figure 3-1: Layer 1 (Top) Figure 3-2: Layer 2

Figure 3-3: Layer 3 Figure 3-4: Layer 4


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Figure 3-5: Layer 5 Figure 3-6: Layer 6

Figure 3-7: Layer 7 Figure 3-8: Layer 8 (Bottom)—as viewed through the board


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4. RDK-12GSRD-ALTRA00 Bill of Materials

Table 4-1: Bill of Materials

Quantity Reference Description

16C1, C2, C3, C4, C5, C6, C10, C12, C19, C20,

C21, C22, C23, C24, C25, C30Capacitor; 10nF 25V 0402

10 C7, C8, C9, C11, C26, C27, C28, C29, C95, C104 Capacitor; 4.7μF 6.3V 0402

51

C13, C14, C18, C31, C32, C37, C38, C39, C40, C41, C43, C44, C45, C46, C47, C54, C56, C58, C61, C63, C64, C65, C67, C68, C69, C71, C73, C74, C76, C77, C79, C80, C81, C82, C84, C85,

C86, C89, C90, C91, C92, C96, C98, C99, C100, C101, C102, C105, C107, C108, C109

Capacitor; 0.1μF 6.3V 0402

2 C15, C33 Capacitor; 470nF 10V 0402

7 C16, C34, C55, C57, C59, C60, C70 Capacitor; 1μF 10V 0402

10C36, C48, C49, C50, C72, C75, C78, C97, C103,

C106Capacitor; 10μF 10V 0603

7 C42, C62, C66, C87, C88, C93, C94 Capacitor; 22μF 10V 0805

2 C51, C52 Capacitor; 33nF 25V 0402

1 C53 Capacitor; 47μF 6.3V 0805

1 D1 Diode; LED 0603 (yellow)

3 J1, J2, J5Connector; BNC edgeCambridge C-SX-141 (BNC-RA-C-SX-069)

1 J3 Connector; BM03B-SRSS-TB

1 J4 Connector; 9-146280-0-34

1 J6 Connector; Samtech #ASP-134488-01

1 J7 Connector; Samtech #SEAM8-20-S02.0-S-04-2-K

1 J9 Connector; FCI #98414-G06-16ULF

3 L1, L2, L3 Inductor; Murata #BLM15AG221SN1D

1 L4 Inductor; Taiyo Yuden #NRS5020T4R7MMGJ

11R1, R36, R38, R41, R43, R44, R54, R55, R56,

R58, R59Resistor; 0Ω 0402

2 R2, R9 Resistor; 30kΩ 0402

1 R3 Resistor; 100kΩ 0402

8 R4, R5, R6, R7, R17, R18, R19, R20 Resistor; 22Ω 0402

3 R8, R15, R16 Resistor; 75Ω 0402


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2 R10, R11 Resistor; 3kΩ 0402

1 R12 Resistor; 17.4kΩ 0402

8 R13, R14, R26, R40, R45, R46, R47, R48 Resistor; 10kΩ 0402

4 R21, R22, R23, R24 Resistor; 4.75kΩ 0402



2 R28, R30 Resistor; 100kΩ 0402


2 R32, R35 Resistor; 0Ω 0402

2 R33, R34 Resistor; 5Ω 0402 (or 4.99Ω)

1 U1 IC; Equalizer, Semtech #GS12141 (QFN-40)

2 U2, U5 IC; TI #TXB0304 (UQFN-12)

5 U3, U10, U11, U13, U17 IC; NXP #74AVC4TD245BQ (DHVQFN-16)

1 U4 IC; Cable Driver, Semtech #GS12181 (QFN-40)

1 U6 IC; TI #LMH1983SQ/NOPB (WQFN-40)

1 U7 IC; TI #LMK03328RHST (QFN-48)

1 U8 IC; TI #LMP7711MK (TSOT-23)

1 U9 IC; TI #LMH1981MT (TSSOP-14)

1 U14 IC; TI #PCA9306DCUR (VSSOP-8)

2 U15, U16 IC; Semtech #SC4212MLTRT (MLPD-8)

1 X1 Crystal; ABRACON #ASDMB 27.0000MHzEY25

1 X2 Crystal; CTS #357LB3C027M0000

Table 4-1: Bill of Materials (Continued)

Quantity Reference Description


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IMPORTANT NOTICE

Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. Semtech reserves the right to make changes to the product or this document at any time without notice. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. Semtech warrants performance of its products to the specifications applicable at the time of sale, and all sales are made in accordance with Semtech’s standard terms and conditions of sale.

SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS, OR IN NUCLEAR APPLICATIONS IN WHICH THE FAILURE COULD BE REASONABLY EXPECTED TO RESULT IN PERSONAL INJURY, LOSS OF LIFE OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise.

The Semtech name and logo are registered trademarks of the Semtech Corporation. All other trademarks and trade names mentioned may be marks and names of Semtech or their respective companies. Semtech reserves the right to make changes to, or discontinue any products described in this document without further notice. Semtech makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose. All rights reserved.

© Semtech 2017

Contact InformationSemtech Corporation

200 Flynn Road, Camarillo, CA 93012Phone: (805) 498-2111, Fax: (805) 498-3804

www.semtech.com


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