Materials for Next Generation HDI

iNEMI PCB Laminate Workshop 2013.10.22

C.B. Katzko TTM Technologies Inc.

Background

IT Market Drivers and Impacts

• Pervasive communication & computing

• Ubiquitous wireless access – WiFi, 3G/LTE

• Rapid migration to cloud based services, hosted servers, “things”

• Impacts -

2

• End Users

• Web services & apps, SaS

• Heterogeneous “BYOD” hosting

• Mobile & desktop convergence

• Infrastructure

• Gigabit broadband + LTE

• Hosted servers/virtualization

• DIY server commoditization

Facebook Open Compute

“vanity-free” server sleds

Bring Your Own Device:

Walk NYC wayfinding kiosk

Chinatown, New York City

PC, Tablet & Smartphone Market Trends

• PC’s in decline : Tablets & Ultramobiles will overtake by 2014

• First time buyers shifting to Tablets & Smartphones

3

2012 2013 2014 2015

Mobile Phone 1,746,176,000 1,875,774,000 1,949,722,000 2,128,871,000

Tablet 116,113,000 197,202,000 265,731,000 467,951,000

Ultramobile 9,822,000 23,592,000 38,687,000 96,350,000

PC 341,263,000 315,229,000 302,315,000 271,612,000

0

500

1,000

1,500

2,000

2,500

3,000

3,500

Mill

ion

s

Worldwide Device Shipments by Segment (Units)

Source : Gartner 2013 April 04 - http://www.gartner.com/newsroom/id/2408515

• Long or “L” shaped HDI logic &

driver boards in phones/tablets

• Ultra book & All-in-One PCs

following tablet practice with SSDs

Handheld Design Practice

• Physical envelope dominated by

displays & batteries

• Modularized construction with flex

cables, sensors, antennas

4

HDI

heat

spreader

cameras

display panel

battery

NEXUS 7 2nd Gen Tablet Teardown

FPC

inductive

charger coil

speakers

Source : iFixit http://www.ifixit.com/Teardown/Nexus+7+2nd+Generation+Teardown/16072/1

Reference HDI Roadmaps

5

BGA Design Rules (microns)

BGA Pitch Signal Routing Inner Line Inner Space Laser Via Inner Pad Outer Pad SM Opening Remarks

0.40mm 1 Track 0.7 - 100 200 225 300 JISSO Roadmap

0.40mm 1 Track 60 65 75 200 200 275 Current Practice

0.40mm 2 Track 40 45 75 180 180 255 Next Gen High I/O SoC,

requires mSAP

0.30mm 1 Track 50 - 75 150 240 175 JISSO Roadmap

0.30mm 1 Track 50 50 75 200 240 175 Current Practice

0.30mm 2 Track 30 30 75 150 240 175 Forecast, requires SAP

0.25mm 1 Track 50 50 50 100 - - JISSO Roadmap,

requires mSAP

0.15mm 1 Track 25 25 30 75 - - JISSO Roadmap,

requires coreless & SAP

Dielectric Thickness (microns)

Min BGA Signal Routing Core Layer Build-up Layer Total Layers Remarks

0.40mm 1 Track 60 60 10 Current Practice STD HDI

0.30mm 1 Track 50 45 10 ~ 12 Current Practice ADV HDI

0.30mm 2 Track 40 40 10 ~ 12 Next Generation ADV HDI

0.25mm 1 Track 40 30 ~ 35 10 ~ 12 Forecast 2015-2016

Problems & Solutions

Electrical – The Low K Challenge

• Designs have reached the limits of FR4 materials

• Designs are constrained by tradeoffs:

• Layer count & overall thickness vs. dielectric layer thickness

• Dielectric layer thickness & Dk vs. line width limits

• Routability of CSP devices verses cross-talk

• Thermal robustness (Td/Tg) vs. resin Dk

• Mechanical strength vs. Dk (high RC FR4 or coreless)

• Impedance and RF values are hard to design & control

• Some of the tricks used for IC packaging don’t translate to the

scale or cost structure of HDI

7

Working Window of Materials/Process

8

0

10

20

30

40

50

60

70

4.5 4.4 4.3 4.2 4.1 4 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3 2.9 2.8 2.7 2.6 2.5

Lin

e W

idth

[µ

m]

Dielectric Constant

Mid/Low Loss HF FR4 Coreless

SA

P

mSA

P

sub

trac

tive

Forecast

Design Rules

Forecast FR4 Materials

• To meet emerging design requirements we need lower DK & finer lines

Electrical Solutions - Materials

• FR4 Materials – current/potential solutions

• Reduce thickness & Dk with high RC ultra-thin glass construction

• 1037, 1027 is short supply & difficult to weave/treat

• Lower Dk using ND glass – cost adder

• Trade off thermal robustness for lower Dk resin

• Coreless Materials – potential solutions

• Hybridize FR4 & coreless (RCC or film) for critical signal layers

• Increases cost, degrades rigidity & dimensional stability

• Complicates Laser drilling & plating of stacked vias

• Foil Materials – potential solutions

• Profile free reduces loss and facilitates fine line subtractive or mSAP

• Substandard peel strength, cannot meet IPC requrements

9

Electrical Solutions – Conductor Process

• mSAP Process

• Reduces conductor thickness and improves resolution

• Lower thickness reduces cross-talk & increases dielectric headroom

• Higher resolution to reduce line width (sub 45um)

• More expensive process:

• LDI image transfer of plating mask for resolution & alignment

• Complex pattern plate/via fill process

• Higher foil material cost

• Lack of industry capacity

• IC Design & Packaging

• Increase SoC integration

• Increased 2.5/3D package integration

10

0.30mm BGA 2 Track mSAP process

Mechanical - Bend, Drop & Flexural Strength

• Bend & drop induced failures in assembly & end use

• Insufficient stiffness of the PCB (thinness, high resin content)

• Fragility of small device solder joints (<0.50mm pitch)

• Component placement close to edges/stress points

• Insufficient mechanical support/dampening in some designs (2 side

assembly designs more vulnerable)

• Human handling & abuse; accidental dropping

• JEDEC 4 point drop testing is now inadequate

• Size, thickness and stiffness of PCB TV does not reflect current design

• 4 point suspension does not reflect actual bend/shock modes

• Trend is to test actual designs in casings at end of design cycle

11

Mechanical - Bend, Drop & Flexural Strength

• How can we provide designers better data?

• Characterize flexural strength (3 point, 4 point monotonic)

• Composites of actual materials used (glass style, resin content)

• Test composite with/without representative copper density

• Correlate to actual board designs (with plated holes)

• Redesign/standardize drop test vehicles to reflect design practice

• Provide guidelines instead of a fixed design?

12

Mechanical Improvements

• Solutions

• Materials

• Overall trend is to higher RC or coreless materials

• No significant improvements on the horizon

• Maximizing conductor & via density improves stiffness

• Mitigation methods

• Adhesive and foam bonding of components to casing

• Metal stiffeners/metal cans on boards or casings

• Stiffer casings, machined metal, honey comb plastic, metal

stiffeners

13

Conclusions

Where We Go From Here

• Next generation HDI design presents challenges to meet

electrical and mechanical design requirement forecasts

• Dielectric property headroom is the most pressing problem

requiring a multifaceted approach to leverage incremental

improvements in materials & conductor formation process

• Reliability related mechanical issues must be mitigated with the

use of adhesives, stiffeners and improvements to casings

• Improvements in SoC and package design can reduce the

complexity of PCB wiring to recover headroom

15

Thank You

Q&A