Space Vector Modulation for CascadedAsymmetrical Multilevel Converters Under Fault

ConditionsFernanda Carnielutti, Student Member, Humberto Pinheiro, and Cassiano Rech

Federal University of Santa MariaSanta Maria, RS, Brazil 97105-900

Abstract— This paper proposes a new space vector modulation(SVM) strategy for asymmetrical cascaded multilevel converters(ACMCs) operating under fault conditions. When the converterloses one power cell, the remaining ones can overmodulate, ifthe modulation strategy is not properly adapted to the faultcondition. As in ACMCs the series-connected power cells op-erate with distinct voltages and frequencies, the overmodulationproblem is more difficult to address, when compared to othermultilevel converters. In this context, the proposed SVM entirelyavoids overmodulation of the converter under any fault condi-tion. In an ACMC, the faults in the low-voltage-high-frequency(LVHF) cells are more problematic, as the converter loses thefine voltage adjustment capability provided by the PWM. Theproposed SVM is carried out in the converter output line-to-line voltages coordinate system, in which all the voltage vectorshave only integer entries. As a result, it is possible to simplifythe implementation of the proposed algorithm. Besides assuringthat the LVHF cells do not overmodulate as much as possible,the SVM flexibilizes the implementation of different switchingsequences for the remainder operational LVHF cells, makingit possible to optimize the quality of the output line-to-linevoltages, without penalizing the switching losses. Simulation andexperimental results are given to validate and to demonstrate theperformance of the proposed SVM.

I. INTRODUCTION

Multilevel converters are widely used nowadays in indus-try applications, such as high voltage and/or high power motordrives, power generation systems, Flexible AC TransmissionSystems (FACTs) [1], [2], etc. The classical topologies arethe neutral point clamped (NPC), flying capacitor (FC), cas-caded multilevel converters (CMCs) and modular multilevelconverter (MMC), with new topologies under development[1]. Among the multilevel converters, the CMC has severalinteresting features that make it attractive, specially for ap-plications that require high reliability rates. This is possibledue to the modularity of this converter, as it is composedof multiple series-connected power cells comprised of single-phase inverters, usually full-bridges. The power cells can havethe same (symmetrical) or different (asymmetrical) DC busvoltages [3].

The main difference between symmetrical and asymmetricalCMCs is that, for a given number of cells per phase, theasymmetrical can synthesize more steps in the output line-to-line voltages. A positive point in having the output line-to-linevoltages with more steps is that their waveforms more closely

resemble sine waves, resulting in low harmonic distortion[2]. Another important difference is that, in the symmetricalconverter, all the cells operate at the same frequency, while inthe asymmetrical, the higher and lower voltage cells operateat lower and higher frequencies, respectively [3]. On the otherhand, one disadvantage of the asymmetrical CMC over thesymmetrical is that the modulation of the first is inherentlymore complex, due to the higher number of voltage levels, thatis, more voltage vectors under the perspective of the SVM, andalso because of the limitation of the switching frequency ofthe higher voltage cells.

As already stated, one important feature of CMCs, in spiteof their DC bus voltages, is the modularity, which allows themto operate even with faults in the power cells. Under theseconditions, the faulty cells are bypassed, but the convertercontinues to operate. To accomplish this, the modulation stra-tegy must compensate for the loss of cells, keeping the outputline-to-line voltages balanced and with optimized amplitudesfor their fundamental components. Some modulation strategiesfor the operation of CMCs under fault conditions have alreadybeen reported [4]–[7], but these methods were designed onlyfor symmetrical CMCs. As the ACMCs are not as modular astheir symmetrical counterparts, due to the fact that the powercells have different ratings for their DC bus voltages andswitching frequencies, their modulation strategies are morecomplex.

To deal specifically with the issue of ACMCs operatingunder fault conditions, a carrier-based peak-reduction methodwas presented in [8], in which two homopolar componentsare added to the phase voltage references. These homopolarsare based on limitations in the phase voltages, imposed by thenumber of faulty cells. In this algorithm, the higher voltagecells are allowed to operate with a frequency different fromthe fundamental, and not necessarily at a constant switchingfrequency. Besides, the output line-to-line voltages may nothave half wave neither quarter wave symmetry, increasing theirharmonic content.

Another carrier-based modulation, both for symmetricaland asymmetrical CMs, was presented in [9], based on thegeometrical principles described in [10]. For each operationalcondition, the region of all possible common-mode voltagesvo for linear operation is derived. The modulating signals for

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each converter phase are defined as the sum of the phasereference and the chosen vo. The output voltage synthesizedby the higher voltage cells is obtained by the comparison ofthe modulator to a constant value [3], [9]. As a result, thesecells operate with low frequency. The reference for the nextset of cells is obtained through the subtraction of the voltagesynthesized by the high voltage cells from the modulatingsignal. Another linear region is derived, with an associatedvo. The modulating signals for the next cells are then the sumof the calculated reference and the new vo. This procedureis repeated until the last set of cells, that is, the ones withlower voltage, that operate with high-frequency pulse-widthmodulation PWM [3], [9]. With this method, it is possibleto achieve optimum amplitude values for the output line-to-line voltages, avoiding the overmodulation region as much aspossible.

However, when the converter loses one low-voltage-high-frequency (LVHF) cell, the geometrical approach can lead toovermodulation on the LVHF cells that remain operational [9].This arises from the comparison of the modulation signalswith constant values to define the voltages of the HVLF cells[3], forcing them to operate at the fundamental frequency.Besides, the resulting voltage is equal to the one that wouldbe obtained by choosing the nearest voltage vector for theHVLF cells in the SV method presented in [11], developed forACMCs under normal operational conditions. It will be provedin the following that the nearest high voltage vector should notalways be chosen. In this context, the SVM proposed in [11] ismodified here to address fauls in the LVHF cells, completelyavoiding overmodulation in the operational LVHF cells. Onthe other hand, the algorithm of [11] can be used, with nomodifications, to modulate the converter when there are faultsin the HVLF cells.

This paper is organized as follows: Section II describes theproposed SV modulation for ACMCs under fault conditions,both in LVHF and HVLF cells; Section III shows simulationand experimental results to validate the theoretical analysis;finally, the conclusions regarding this work are presented inSection IV.

II. PROPOSED SPACE VECTOR MODULATION FOR ACMCSUNDER FAULTS CONDITIONS

As previously exposed, faults in the LVHF cells ofACMCs are more problematic than faults in the HVLF cells.In the first case, depending upon the modulation of the HVLFcells when the converter loses one LVHF cell, the remainingLVHF cells can overmodulate. On the other hand, faults inthe HVLF cells are not so problematic, as the maximumvalues of line-to-line voltages that the converter is able tosynthesize are reduced when compared to faults in the LVHFcells, but overmodulation does not arise. For simplicity, andwithout losing the generality, the SVM be presented throughan example: a seven-level ACMC, as shown in Fig. 1, in whichthe cells A1, B1 and C1 have DC bus voltage values of 1puand A2, B2 and C2 of 2pu.

As stated in the previous section, the SVM proposed in

n

Cell

Bypass

a cb

Motor

1A

2A

1B

2B

1C

2C

Insu

late

dT

ran

sfo

rmer

Fig. 1. Seven level asymmetrical cascaded multilevel converter used todemonstrate the proposed SVM.

this paper is a modification of the algorithm first presented in[11]. The voltage vectors and the references are representedin the converter output line-to-line voltages coordinates, inwhich the first two entries of the vectors are the converteroutput line-to-line voltages vab and vbc, and the third oneis proportional to the converter common-mode voltage vo.The voltage for the HVLF cells is defined by the choiceof the high voltage vector whose sector in the SV diagramencompasses the reference. The references for the LVHF cellsare the result of the subtraction of the HVLF voltages fromthe total reference. The output voltages of the LVHF cellsare obtained by the choice of the three-nearest voltage vectors[12], implemented as a switching sequence defined offline, thatminimizes the number of commutations within each sector, aswell as in the transition between sectors [11].

The SV diagram for the converter in the output line-to-line voltages coordinates for normal operation is shown inFig. 2. The voltage vectors of the HVLF and LVHF cells arerepresented respectively by the larger and smaller dots. EachHVLF vector is surrounded by a subhexagon comprised of thevectors of the LVHF cells. Any reference voltage vector lyingwithin the region delimited by the LVHF vectors around agiven HVLF vector can be synthesized by averaging the three-nearest LVHF vectors without commutating the associatedHVLF vetor. Each one of the subhexagons is divided in24 sectors, delimited by three low voltage vectors and theirredundancies.

Under normal operation, there is a superposition of adjacentsubhexagons, as seen in Fig.2. However, when there is a faultin a LVHF cell, the SV diagram is modified, as shown in Fig. 3,for a fault in the LVHF cell of phase a. The intersection areasare lost, as the converter can now synthesize a smaller numberof voltage vectors, resulting in subparalleograms instead ofsubhexagons. Even though the superposition areas are lost,there are no ”holes” between adjacent sectors in the SV

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diagram. Each sector still is comprised of three low voltagevectors, but there are now less redundancies. For faults in theLVHF cells of other phases, the shape of the SV diagramis different, but, irrespectively of the phase, the maximummodulation index attained is the same, with the maximumoutput line-to-line voltages corresponding to the larger ellipseinscribed in the SV diagram.

Fig. 2. SV diagram for a 7-level ACMC represented in the output line-to-linevoltages coordinates under normal operational conditions.

Fig. 3. SV diagram for a 7-level ACMC represented in the output line-to-linevoltages coordinates, with a fault in the LVHF cell of phase a.

In [11], the selected HVLF vector is the nearest one to thereference. If the reference is located in two subhexagons atthe same time, the chosen vector is the one that yields thelesser number of commutations in respect to the previouslyimplemented one. The choice of the HVLF vector as theone nearest to the reference is valid for normal operational

conditions [11]. During faults, however, this is not the bestalternative, resulting in overmodulation of the LVHF cells.In the SV context, the overmodulation happens when thereference lies outside the SV diagram. For the same exampleof the fault in the LVHF cell of phase a, lets first chose theHVLF vector as the nearest one to the reference [11]. Fig.4 shows the sector of the SV diagram for the LVHF cellscentered at the origin. The sampled reference for the LVHFcells is shown as the smaller dots, and it can be clearly seenthat there are some regions in which it lies outside the SVdiagram.

Fig. 4. SV diagram for a sector of the LHVF cells with overmodulation,with a fault in the LVHF cell of phase a.

The problem in choosing the HVLF vector as the nearestone is that it may happen that the reference does not lie insidethe subparallelogram associated to the chosen HVLF vector,because of the loss of the superposition areas. The HVLF vec-tor that should be chosen is the one whose subparallelogramencompasses the reference, even if it is not the nearest one toit. For the fault condition under consideration, Fig. 5 showsa zoom of the SV diagram and the sampled reference. As anexample, for a sampled reference located at [-3.779 2.723]T ,the algorithm of [11] would chose [-4 2]T as the HVLF vector,as it is closer to the reference. But the reference lies insidethe sector relative to the vector [-4 4]T , and this one shouldbe implemented.

In this context, the algorithm of [11] was modified to dealwith the problem of faults in the LVHF cells. At each timerinterruption, the sector in which the sampled reference lies isidentified. The HVLF vector whose associated sector encom-passes the reference is then implemented by the converter. Atalmost all the time, the chosen vector is really the nearestone, but, when the reference lies in the place where in thenormal operational conditions there would be a superpositionarea, the chosen vector may not be the nearest one. With themodification in the algorithm of [11], the reference for theLVHF cells always lies entirely inside the SV diagram, asshown in Fig. 6 for the same operational conditions of Fig. 4.

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Fig. 5. Zoom of SV diagram and sampled reference.

Fig. 6. SV diagram for a sector of the the LHVF cells without overmodu-lation, with a fault in the LVHF cell of phase a.

The reference for the LVHF cells is obtained in the sameway as for normal operation. The reference is truncated, andthe three nearest LVHF vectors are chosen, just as in [11]and [12]. Their duty cycles are calculated, and used to updatethe values of the comparators for that specific sector, resultingin the output voltages for the operational LFHV cells. Theonly difference from normal operation is that, under faultconditions, there are some LVHF vectors that the converter canno longer implement. Consequently, there are fewer subsectorsinside the LVHF sector, as well as less redundancies. Theremaining LVHF vectors are organized offline in switchingsequences, just as in [11].

When compared to the faults in the LVHV cells, for faultsin the HVLF cells, the modulation is quite simpler, as theovermodulation problem does not arise. As for faults in theLVHF cells, the SV diagram is modified, as shown in Fig. 7,for a fault in the HVLF cell of phase a. The modulation both of

the HVLF and the LVHF cells is the same as the one describedin [11] for normal operational conditions, without the need tomodify the algorithm. The only limitations are the modulationindex, that can not achieve values as high as m = 1, andthe lesser number of implementable voltage vectors, includingsome redundant vectors. The switching sequences for theLVHF cells can be the same as the ones used in [11], as thesectors do not change their shapes, that is, they are the samesubhexagons as for normal operation, as seen in Fig. 7.

abv

bcv

-4 -2 2 4

-6

-4

-2

0

2

4

6

Fig. 7. SV diagram for a 7-level ACMC represented in the output line-to-linevoltages coordinates with a fault in the HVLF cell of phase a.

In the next section, simulation and experimental results areshown to demonstrate and validate the proposed modulationstrategy.

III. SIMULATION AND EXPERIMENTAL RESULTS

In this section, simulation and experimental results areshown to validate the proposed SVM strategy for ACMCsunder fault conditions. The converter is the same of Fig. 1. Theparameters are a carrier frequency of 3kHz, with interruptionsat the underflow and overflow of the timer, and a modulationindex m = 0.65. As the SVM inherently synthesizes outputline-to-line voltages 15% larger than conventional modulationstrategies, such as sinusoidal PWM, the amplitude of thephase reference is set to be 346.41V, resulting in outputline-to-line voltages with amplitude of the fundamental ofapproximately 600V, that is, 390V for a modulation index of0.65. In the experimental setup, the cells are controlled by aTMS320F28335 floating-point DSP from Texas Instruments.The DC bus voltage of the LVHF cells (1pu cells) has beenselected as 100V, and, of the HVLF (2pu cells), as 200V, tomatch the experimental setup available at the laboratory. Theresults were taken for faults in the LVHF and HVLF cells ofphase a, one at a time.

The simulated and experimental output line-to-line voltagesvab, vbc and vca, for the condition of a fault in the LFHVcell of phase a, are shown, respectively, in Figs. 8 (a) and (b).

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Even though their waveforms in time may differ, the amplitudeof their fundamentals are practically the same, being equal toVab = 389.9V, Vbc = 389.9V, and Vca = 389.8V. For a faultin the HVLF cell of phase a, the simulated and experimentaloutput line-to-line voltages are show in Figs. 9 (a) and (b).Their fundamental values are Vab = 389.6V, Vbc = 388.6V,and Vca = 388.7V. The output phase voltages vag , vbg and vcgare shown in Fig. 10 (a) and (b), respectively for the fault inthe LVHF and in the HVLF cells of phase a. It can be seenfrom the results that the output line-to-line voltages remainbalanced even under fault conditions.

0.05 (ms)

abv

bcv

cav

Voltage (V)

(a)

(b)

0

-400

400

0

-400

400

0

-400

400

Fig. 8. Converter output line-to-line voltages with a fault in the LVHF cellof phase a (a) Simulated (b) Experimental - Horizontal: 4ms/div; Vertical:500V/div.

IV. CONCLUSIONS

This paper proposed a new space vector modulation stra-tegy for asymmetrical multilevel cascaded converters operatingunder fault conditions. In the case of faults in an LVHFcell, the algorithm assures that the operational LVHF cellswill not overmodulate, by properly choosing the high voltagevectors for the HVLF cells. For faults in the HVLF cells,the modulation is the same as for normal operational condi-tions; the only limitations are the maximum modulation indexthat can be attained and the lesser number if implementablehigh voltage vectors. With the proposed SVM, the maximumconverter synthesis capability is totally explored under faultconditions. The algorithm can be extended to converters with

0.05 (ms)

abv

bcv

cav

Voltage (V)

(a)

(b)

0

-400

400

0

-400

400

0

-400

400

Fig. 9. Converter output line-to-line voltages with a fault in the HVLF cellof phase a (a) Simulated (b) Experimental - Horizontal: 4ms/div; Vertical:500V/div.

a higher number of levels. Finally, simulation and experimentalresults have proven that the LVHF cells do not overmodulateunder fault conditions, as theoretically predicted. Besides, theSV modulation flexibilizes the implementation of differentswitching sequences for the LVHF cells that can minimizethe THD and DF1 indexes, for example, as well as thecommutation losses.

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(b)

(a)

Fig. 10. Converter output phase voltages with (a) a fault in the LVHF cellof phase a, and (b) with a fault in the HVLF cell of phase a - Horizontal:4ms/div; Vertical: 500V/div.

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