IBM/Motorola/Apple PowerPC

Patrick Kang Temitope Akanni

Jane McHughKenneth Kincel

CS 480: Computer ArchitectureSummer 2002

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How Did PowerPC Start?

• In 1991 Intel’s domination of the PC market.

• Other competitors’ uphill struggle.• Realization of cooperating among the

competitors.• What to do about Intel’s domination.

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Birth of PowerPC• PowerPC Alliance, IBM, Apple, and

Motorola.• Development of PowerPC Architecture.• Some changes.• A three year of their hard work.• The new architecture in 1994.• Performance Optimization With Enhanced RISC Personal Computer.

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RISC vs. CISC

• Reduced Instruction-Set Computer

• More register• Faster and slower• Faster raw speed

(executing instructions per sec)

• Faster in terms of implementing one single instruction

• Complex Instruction-Set Computer

• Micro conversion layer

• Faster and slower• More powerful in

terms of what each instruction can do

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RISC vs. CISC

• A = B + C• ld[A], %r1

ld[B], %r2addcc %r1,%r2,%r3st %r3, [C]

• A = B + C• addcc [A], [B], [C]

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So, which one is faster?

• No simple answer• Neither• It all depends on what application you are

using.• You have the power to make one of these

faster by carefully choosing the best instruction for your application.

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Power Architecture

• Complex CISC instructions can be replaced with simple RISC instruction.

• Aspects of RISC computing incorporated into the Power architecture:– Instructions were fixed to four bytes in length– Load and store instructions were used to

provide all the access to and from memory

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Power Architecture

• Difference between earlier RISC machines and Power architecture:– Each function (floating-point, fixed-point, integer

computation were placed in their own units.• Emphasized the superscalar aspect of the Power

architecture. Instructions to and from different units can be accessed in parallel.

• PowerPC 601- the first microprocessor, architecture implemented in IBM RS/6000 workstations.

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PowerPC Architecture: A New Beginning

• The PowerPC is 64-bits in length and is compatible with the Power 32-bit data paths.

• Dynamic switching between the 64-bit and 32-bit is supported.

• Infrequently executed instructions in the Power architecture were discarded in the PowerPC.

• IBM 601 microprocessor used all but two of the instructions in the of the Power instructions set.

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PowerPC 750 Microprocessor

IBM PowerPC 604e

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PowerPC 604e• Implementation of the PowerPC

architecture specification, developed by Apple, IBM and Motorola

• Enhanced version of the PowerPC 604– Higher clock frequencies– Extended debug mode

• Designed for workstations, PC servers and power user desktop segments

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PowerPC 604e• Architecture consists of:

– PCU– 2 simple integer ALUs– 1 complex integer unit– Floating-point unit– LOAD/STORE unit– Branch unit– Instruction and data caches– CRU

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PowerPC 604e Architecture

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PowerPC 604e Memory System

• Single 32-bit address space• Memory space is byte-addressable • Supports big-endian and little-endian byte-

ordering• Only one load or store can be performed per

clock cycle• Uses a four-entry load buffer and a six-

entry store buffer

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PowerPC 604e Memory System

• Instruction cache– Size: 32 KBytes– Access Width: 128

bits wide– Block Size: 128

KBytes-8 Mbytes– Virtual Address

Space: 52 bits

• Data cache– Size: 32 KBytes– Access Width: 64 bits

wide– Block Size: 128

KBytes-8 Mbytes– Virtual Address Space:

52 bits

IBM PowerPC 750CX

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Chip MHz Bus Speed

L1 Cache

L2 Cache

L3 Cache

Mics Die Size

Trans Form Factor

Us Price Volts Watts SpecIntSpecFP

750CX 350 100 64KB-32K I-32K D

256K on-Chip

- .18 42 21.5 M

256-pinPBGA

? 1.8 ? 14.510.8

400 100 64KB-32K I-32K D

256K on-Chip

- .18 42 21.5 M

256-pinPBGA

? 1.8 4.0 16.211.5

64KB-32K I-32K D

256K on-Chip

- .18 42 21.5 M

256-pinPBGA

? 1.8 ? 18.011.9

64KB-32K I-32K D

256K on-Chip

- .18 42 21.5 M

256-pinPBGA

? 1.8 ? 19.712.5

64KB-32K I-32K D

256K on-Chip

- .18 42 21.5 M

256-pinPBGA

? 1.8 ? 20.812.7

Graph of Interesting Specs

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Interesting Features

• Two fixed-point (integer) execution units.

• 38 32-bit registers. 32 are architected general-purpose registers and six rename registers.

• L1 instruction cache has a 128-bit-wide read bus that allows four instructions to be fetched into the instruction queue every cycle.

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Integrated Cache

• What separates the 750CX from its predecessor the 750, commonly known as the G3, is that the 750CX has an integrated 256KB level 2 (L2) cache.

• Integrated cache runs at full CPU clock speed.

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Advantage of Integrated Cache

• Power Usage• Inexpensive to manufacture which equates

to lower cost for the consumers

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Future of the PowerPC

• Strong future with expanded possibilities– PC that automatically downloads software

updates and security controls– Intel Lecta to wirelessly host multimedia

applications for other home devices– Third Generation I/O to replace the common

PCI bus