HYBRID MICROCIRCUIT TECHNOLOGY HANDBOOK

Materials, Processes, Design,

Testing and Production

Second Edition

by

James J. Licari AvanTeco Corporation

Whittier, California

and

Leonard R. Enlow Rockwell Autonetics Anaheim, California

NOYES PUBLICATIONS Westwood, New Jersey, U.S.A.

Contents

1 Introduction 1 1.0 CLASSIFICATION OF MATERIALS FOR

MICROELECTRONICS 1 1.1 Conductors 1 1.2 Insulators 4 1.3 Semiconductors 6

2.0 CLASSIFICATION OF PROCESSES 10 3.0 DEFINITION AND CHARACTERISTICS OF HYBRID

CIRCUITS 11 3.1 Types and Characteristics 11 3.2 Comparison With Printed Wiring Boards 14 3.3 Comparison With Monolithic Integrated Circuits 18 3.4 Comparison with Multichip Modules 20

4.0 APPLICATIONS 21 4.1 Commercial Applications 22 4.2 Military/Space Applications 24 4.3 Power Applications 26

REFERENCES 31

2 Substrates 32 1.0 FUNCTIONS 32 2.0 SURFACE CHARACTERISTICS 33

2.1 Surface Roughness/Smoothness 33 2.2 Camber 35 2.3 Granularity 36

xiü

xiv Contents

3.0 ALUMINA SUBSTRATES 36 3.1 Grades of Alumina 38 3.2 Alumina Substrates For Thick Films 38 3.3 Alumina Substrates For Thin Films 39 3.4 Co-Fired CeramicTape Substrates 44

4.0 BERYLLIA SUBSTRATES 45 5.0 ALUMINUM NITRIDE 49 6.0 METAL MATRIX COMPOSITES 50 7.0 CERAMIC SUBSTRATE MANUFACTURE 57 8.0 ENAMELED METAL SUBSTRATES 57 9.0 QUALITY ASSURANCE AND TEST METHODS 59 REFERENCES 61

3 Thin Film Processes 63 1.0 DEPOSITION PROCESSES 63

1.1 Vapor Deposition 63 1.2 Direct Current (de) Sputtering 66 1.3 Radio-Frequency (RF) Sputtering 69 1.4 Reactive Sputtering 69 1.5 Comparison of Evaporation and Sputtering Processes 72

2.0 THIN FILM RESISTOR PROCESSES 72 2.1 Thin Film Resistors 72 2.2 TheNichrome Process 74 2.3 Characteristics of Nichrome Resistors 78 2.4 The Tantalum Nitride Process 82 2.5 Characteristics of Tantalum Nitride Resistors 83 2.6 Cermet Thin-Film Resistors 84

3.0 PHOTORESIST MATERIALS AND PROCESSES 86 3.1 Chemistry of Negative Photoresists 90 3.2 Chemistry of Positive Photoresists 90 3.3 Processing 94

4.0 ETCHING MATERIALS AND PROCESSES 96 4.1 Chemical Etching of Gold Films 97 4.2 Chemical Etching of Nickel and Nickel-Chromium Films . 97 4.3 Dry Etching 98

5.0 THIN-FILM MICROBRIDGE CROSSOVER CIRCUITS .. 100 REFERENCES 101

4 Thick Film Processes 104 1.0 FABRICATION PROCESSES 104

1.1 Screen-Printing 104 1.2 Drying 108

Contents xv

1.3 Firing 109 1.4 Multilayer Thick-Film Process 111 1.5 Multilayer Co-fired Ceramic Tape Processes 113 1.6 Fligh Temperature Co-fired Ceramic (HTCC) 116 1.7 Low-Temperature Co-fired Ceramic (LTCC) 122

2.0 DIRECT WRITING 126 2.1 Fine-Line Thick-Film Processes 127

3.0 PASTE MATERIALS 130 3.1 Types and Compositions 130 3.2 Conductor Pastes 132 3.3 Resistor Pastes 143 3.4 Dielectric Pastes 147 3.5 Thick-Film Capacitors 151

4.0 NON-NOBLE-METAL THICK FILMS 152 4.1 Processing of Copper Thick Films 155 4.2 Characteristics of Copper Thick-Film Conductors 157 4.3 Processing of Nitrogen-Fired Dielectrics 162 4.4 Processing of Nitrogen-Fired Resistors 163

5.0 POLYMER THICK FILMS 164 5.1 PTF Conductors 164 5.2 PTF Resistors 167 5.3 PTF Dielectrics 168

REFERENCES 168

5 Resistor Trimming 172 1.0 LASER TRIMMING 173 2.0 ABRASIVE TRIMMING 182 3.0 RESISTOR PROBING/MEASUREMENT TECHNIQUES 183

3.1 Probe Cards 183 3.2 Two-Point Probing 184 3.3 Four-Point Probing 185 3.4 Digital Voltmeters (DVM) 186

4.0 TYPES OF RESISTOR TRIMS 186 4.1 Plunge-Cut 186 4.2 Double-Plunge-Cut 186 4.3 L-Cut 188 4.4 Scan-Cut 188 4.5 Serpentine-Cut 188 4.6 Digital Cut 188

5.0 SPECIAL REQUIREMENTS 189 REFERENCES 189

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6 Parts Selection 191 1.0 GENERAL CONSIDERATIONS 191 2.0 PACKAGES 192

2.1 PackageTypes 193 2.2 Power Packages 201 2.3 Epoxy-Sealed Packages 201 2.4 Plastic Encapsulated Packages 202 2.5 Ball Grid Array (BGA) Packages 202 2.6 Package Testing 205

3.0 ACTIVE DEVICES 206 3.1 Passivation 206 3.2 Metallization 207 3.3 Transistors 207 3.4 Diodes 209 3.5 Linear Integrated Circuits 209 3.6 Digital Integrated Circuits 210

4.0 PASSIVE DEVICES 212 4.1 Capacitors 212 4.2 Resistors 217 4.3 Inductors 219 4.4 Procurement 222

REFERENCES 223

7 Assembly Processes 224 1.0 INTRODUCTION 224 2.0 DIE AND SUBSTRATE ATTACHMENT 225

2.1 Types and Functions 225 2.2 Adhesive Attachment 227 2.3 Metallurgical Attachment 239 2.4 Silver-Glass Adhesives 241

3.0 INTERCONNECTIONS 244 3.1 Wire Bonding 244 3.2 Automated Bonding 258 3.3 Flip-chip Interconnections 268

4.0 CLEANING 270 4.1 Contaminants and Their Sources 272 4.2 Solvents 272 4.3 Cleaning Processes 277

5.0 PARTICLE IMMOBILIZING COATINGS 288 5.1 Parylene Coatings 288 5.2 Solvent-Soluble Coatings 294 5.3 Particle Getters 295

Contents xvii

6.0 VACUUM-BAKING AND SEALING 295 6.1 Vacuum-Baking 295 6.2 Sealing 297 6.3 Metallurgical Sealing 299

REFERENCES 312

8 Testing 317 1.0 ELECTRICAL TESTING 318

1.1 Electrical Testing of Die 318 1.2 Electrical Testing of Hybrids 321

2.0 VISUAL INSPECTION 327 3.0 NONDESTRUCTIVE SCREEN TESTS 327

3.1 Thermal/Mechanical Tests 327 3.2 Burn-in 330 3.3 Particle-Impact-Noise Detection (PIND) Testing 336 3.4 Infrared (IR) Imaging 337 3.5 Acoustic Microscopy 342

4.0 DESTRUCTIVE SCREEN TESTS 343 4.1 Destructive Physical Analysis (DPA) 343 4.2 Moisture and Gas Analysis of Package Ambients 344

REFERENCES 346

9 Handling and Clean Rooms 348 1.0 HANDLING OF HYBRID CIRCUITS AND

COMPONENTS 348 1.1 Cleanliness of Tools 348 1.2 Storage 348 1.3 Clean Rooms 350

2.0 ELECTROSTATIC DISCHARGE 354 2.1 Development of Charge 354 2.2 Device Susceptibility 356 2.3 Static Damage 357 2.4 Coping with ESD 359

REFERENCES 362

10 Design Guidelines 363 1.0 HYBRID MICROCIRCUIT DESIGN TRANSMITTAL 363 2.0 SYSTEM REQUIREMENTS AFFECTING HYBRID

CIRCUIT DESIGN 364 2.1 Partitioning 364 2.2 Input/Output Leads 368 2.3 Component Density 369

xviii Contents

2.4 Power Dissipation 369 2.5 Mechanical Interface/Packaging Requirements 370

3.0 MATERIAL AND PROCESS SELECTION 370 4.0 QUALITY ASSURANCE PROVISIONS 372

4.1 Quality Engineering/Quality Assurance Requirements .... 372 4.2 Screen Tests 372 4.3 Preferred Parts List 372

5.0 HYBRID DESIGN PROCESS 373 5.1 Design and Layout 373 5.2 Computer-Aided Design (CAD) 374 5.3 Artwork 376 5.4 Design Review 377 5.5 Engineering-Model Design Verification 384 5.6 Modification and Redesign 384

6.0 SUBSTRATE PARASITICS 385 6.1 Capacitance Parasitics 385 6.2 Conclusions on Interelectrode Capacitance 389 6.3 Capacitance Computer Program 389 6.4 Inductive Parasitics 392 6.5 Conclusions on Parasitic Inductance 396

7.0 THERMAL CONSIDERATIONS 398 7.1 Conduction 399 7.2 Convection 399 7.3 Radiation 399 7.4 Circuit Design Thermal Criteria 400 7.5 Thermal Analysis Computer Programs 407 7.6 Thermal Testing 408

8.0 LAYOUT GUIDELINES COMMON TO BOTH THICK-AND THIN-FILM HYBRIDS 408 8.1 Preliminary Physical Layout 409 8.2 Estimating Substrate Area 409 8.3 Final Physical Layout 409 8.4 Assembly Aids 411 8.5 Device Placement 411 8.6 Wire Bonding Guidelines 413 8.7 Preferred Processes and Materials 415

9.0 GUIDE TO HIGH-PERFORMANCE HYBRID/MCM/ PACKAGE DESIGN 418 9.1 General 418 9.2 Signal Lines 418 9.3 Power and Ground Planes 419 9.4 Substrate and Conductor Material 420

Contents xix

10.0 EQUATIONS 420 11.0 CROSS-TALK 421 12.0 SIGNAL LINE CAPACITANCE 421 13.0 SIGNAL-LINE INDUCTANCE 421 14.0 MICROSTRIP PROPAGATION DELAY 422 15.0 TYPICAL MATERIAL THICKNESSES 422 16.0 THICK-FILM MATERIALS AND PROCESSES

DESCRIPTION 423 16.1 Thick-Film Substrates 423 16.2 Thick-Film Conductor Materials 426 16.3 Thick-Film Resistors 426 16.4 Overglaze Design Guidelines 428 16.5 Solder Application 431 16.6 Thick-Film Dielectrics 431

17.0 THICK-FILM DESIGN GUIDELINES 431 17.1 Artwork and Drawing Requirements 431 17.2 Multilayer Yields 435 17.3 Conductor Pattems—General Considerations 435 17.4 Vias—Conductor Connections Through Multilayer

Dielectric 439 17.5 Wire and Die Bonding Pads 440 17.6 Thick-Film Resistor Design Guidelines 446

18.0 THIN-FILM GUIDELINES 455 18.1 Standard Practices 455 18.2 Design Limitations 456

REFERENCES 461

11 Documentation and Specifications 462 1.0 DOCUMENTATION 462 2.0 MILITARY AND GOVERNMENT SPECIFICATIONS 464

2.1 MIL-M-38510—General Requirements for Microcircuits .. 465 2.2 MIL-H-38534—Hybrid Microcircuits, General

Specification For 466 2.3 MIL-STD-883—Test Methods and Procedures for

Microelectronics 466 2.4 MIL-PRF-38534—Performance Specification, Hybrid

Microcircuits, General Specification for 468 2.5 ExploringYourOptionsUnderMIL-PRF-38534 470 2.6 MIL-STD-1772 Certification Requirements for Hybrid

Microcircuit Facilities and Lines 481 2.7 The Elimination of MIL-STD-1772 482

REFERENCES 482

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12 Failure Analysis 483 1.0 TYPES AND CAUSES OF HYBRID FAILURES 483

1.1 Device Failures 484 1.2 Interconnection Failures 486 1.3 Substrate Failures 486 1.4 Package Failures 487 1.5 Contamination 487

2.0 FAILURE ANALYSIS TECHNIQUES 493 2.1 Electrical Analysis 493 2.2 Chemical Analysis 493 2.3 Thermal Analysis 494 2.4 Physical Analysis 494

3.0 ANALYTICAL TECHNIQUES 494 3.1 AES—Auger Electron Spectroscopy 494 3.2 ESCA—Electron Spectroscopy for Chemical Analysis ... 497 3.3 SIMS—Secondary-Ion Mass Spectrometry 497 3.4 SEM—Scanning Electron Microscopy 497 3.5 EDX—Energy Dispersive X-Ray Analysis 497 3.6 WDX—Wavelength Dispersive X-Ray Analysis 498 3.7 RBS—Rutherford Backscattering Spectrometry 498 3.8 LIMS—Laser Ionization Mass Spectrometry 499 3.9 EBIC—Electron Beam Induced Current 499 3.10 Infrared 500 3.11 SLAM and C-SAM 500

4.0 CAUSES OF HYBRID CIRCUIT FAILURES 500 4.1 Tin Whiskers 500 4.2 Metallic Smears 500 4.3 Particles 502 4.4 Flux Residues 502 4.5 Cracked/Broken Die 502 4.6 Collapsed Wires 502 4.7 Package Plating 503 4.8 Package Discoloration 503 4.9 Nickel Ion Contamination 504

5.0 CASE HISTORIES OF HYBRID CIRCUIT FAILURES .... 504 5.1 Corrosion of Aluminum Wire Bonds 504 5.2 Corrosion ofNichrome Resistors 506 5.3 Stress Corrosion of Kovar 507 5.4 Intermetallics In Wire Bonds 509 5.5 Die Bond Surface Oxidation 513 5.6 Loose Particle Short 515

Contents xxi

5.7 Wire Bond Short, Casel 516 5.8 Wire Bond Short, Case 2 517 5.9 Weak Wire Bonds, Case 1 520 5.10 Weak Wire Bonds, Case 2 521 5.11 Open Wire Bonds 523

REFERENCES 525

13 Multichip Modules: A New Breed of Hybrid Microcircuits 526 1.0 APPLICATIONS 528 2.0 INTERCONNECT SUBSTRATE DESIGNS AND

FABRICATION METHODS 535 2.1 MCM-D 535 2.2 "Chips Last" versus "Chips First" Designs 537 2.3 MCM-C 538 2.4 MCM-L 540 2.5 Combinations of MCM Technologies 540

3.0 ASSEMBLY METHODS 541 3.1 Plastic Encapsulation/Glob Topping 542

4.0 TESTING AND TESTABILITY 543 4.1 Hierarchical Test Methodology 544 4.2 Design For Test 545 4.3 Boundary Scan 546 4.4 Built-in Seif Test (BIST) 546 4.5 Known Good Die (KGD) 547 4.6 Multichip Module Test Equipment 551

5.0 ISSUES 552 SA Cost bbl 5.2 Thermal Management 552 5.3 Aluminum Nitride 553 5.4 CVD Diamond 556 5.5 Metal Matrix Composites 559 5.6 Rework and Repair 560

REFERENCES 561

Index 565