HX8861-H11 DS v03 - Phoenix Display

( DOC No. HX8861-H11-DS )

HX8861-H11 TFT LCD Timing controller with LVDS input and mini-LVDS output Version 03 May, 2014

-P.2- Himax Confidential

May, 2014 This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax.

1. General Description The HX8861-H11 is a timing controller embedded with a single pixel LVDS receiver and a 3-pair mini-LVDS transmitter for TFT LCD panel. The mini-LVDS is a low EMI and low voltage swing interface that transmits data between the timing controller and source drivers. The HX8861-H11 supports WXGA (1366X768) and other resolutions with EEPROM.

2. Features

Input frequency range from 25MHz to 110MHz mini-LVDS frequency range from 50MHz to 300MHz Support WXGA (1366X768) and other resolutions with EEPROM Built-in single pixel LVDS receiver Built-in mini-LVDS transmitter for low power consumption and low EMI Built-in single port 6-bit mini-LVDS 3-pair differential bus interface output Support both 6/8 bit inputs. 8-bit input and 6-bit output with FRC mode (16.7M colors) Embedded with aging generator for simplifying TFT LCD panel dynamic burn-in test Support DE mode only Support serial bus programming Support dual-gate panel structure Support gamma correction function Support POL 1, 1+2n, 2n, 2+2n (n=1 ~ 8) line, column inversion by ROM code setting Support LVDS input port mirror function by ROM code setting Support LVDS VESA/JEIDA format by ROM code setting Support mini-LVDS output skew control with EEPROM Support CE (hue/saturation, brightness/contrast, sharpness adjustment) function Support CABC (Content Adaptive Brightness Control) function Support SDRRS (Seamless Dynamic Refresh Rate Switching) function Support 5V tolerance input pads: CABC_EN, COLOR_EN, AGMODE, PWMI Supply voltage: VDD=2.5V/3.3V (2.3V~3.6V) 46-pin QFN package with E-PAD HX8861-H11DDKG: support ≧ 32K bit EEPROM only HX8861-H11DDKG-E: support 2K to 16K bit EEPROM only

HX8861-H11 TFT LCD Timing controller with LVDS input and mini-LVDS output Version 03 May, 2014



HX8861-H11 TFT LCD Timing controller with LVDS input and mini-LVDS output

DATA SHEET V03

3. Block Diagram

Agi

ng G

ener

ator

Imag

e D

ata

Pro

cess

ing

Dat

a R

e-or

der

LVD

S R

ecei

ver

min

i-LV

DS

T

rans

mitt

er

Pin/RegisterSetting

Processing

SystemControl &

Gate/SourceControl

SerialBus/ROM

Control

ROMDownloadRegisters

POL, TP1

STV, CPV, OE1, OE2

ROM

SDAT

SCLK

To All Blocks

To All Blocks To All Blocks

Miscellaneous Control

MLCLKP/N

ML2P/N

ML1P/N

ML0P/N

LV2P/N

LV1P/N

LV0P/N

LVCLKP/N

LV3P/N




DATA SHEET V03

4. Pin Assignment

171615141312 232221201918

28

29

30

31

24

25

26

27

394041424344 333435363738

1

9

8

7

6

5

4

3

2

VDDA

LV0N

LV1N

LV0P

LV1P

LV2N

LVCLKN

LV2P

LVCLKP

N.C

.

N.C

.

AG

MO

DE

VS

S

CA

BC

_EN

N.C

.

VD

D

PW

MO

VS

SA

ML2P

ML2N

ML1P

ML1N

ML0P

ML0N

VD

DM

VD

D

TP

1

PO

L

OE

1

SC

LK

SD

AT

CO

LOR

_EN

TE

ST

OE

2

PI

/HW

RS

TZ

MLCLKP

MLCLKN

CP

V

PW

MI

1110

LV3P

LV3N

32

VSSM

4546

VS

S

N.C

.

ST

V




DATA SHEET V03

5. Pin Description

Pin name Pin no. I/O Description LVDS input signals

LV0P/N LV1P/N LV2P/N LV3P/N

3,2 5,4 7,6

11,10

In LVDS differential data pairs.

LVCLKP/N 9,8 In LVDS differential clock pairs. mini-LVDS output signals

ML0P/N ML1P/N ML2P/N

28,27 30,29 32,31

Out mini-LVDS outputs to source drivers.

MLCLKP/N 26,25 Out mini-LVDS clock outputs to source drivers. PI 21 In External resistor input for mini-LVDS output swing control.

Gate/Source driver control signals-for normal or dual-gate mode

N.C. 15,22 23,46

Out No connection pin. It should be floating.

TP1 35 Out Data latch output to source driver. POL 36 Out Polarity inversion output to source driver. STV 37 Out Start pulse to gate driver. CPV 38 Out Gate driver clock. OE1 39 Out Output enable signal to gate driver. OE2 40 Out Gate pulse modulation signal.

Miscellaneous control signals PWMO 13 Out Backlight control output.

CABC_EN(1) 17 In CABC function selection, default CABC_EN=L. CABC_EN=H: Enable CABC function. CABC_EN=L: Disable CABC function.

/HWRSTZ 18 In Reset input (low active).

COLOR_EN(1) 19 In Color engine function selection, default COLOR_EN=L. COLOR_EN=H: Enable color engine function. COLOR_EN=L: Disable color engine function.

AGMODE(1) 20 In Aging pattern selection, default AGMODE=L. AGMODE=H and no clock in: BIST pattern. AGMODE=L and no clock in: Black pattern.

TEST 41 In Test mode selection, default TEST=L. TEST=H: Test mode. TEST=L: Normal operation.

SCLK 42 In/Out Control register input clock (using EEPROM). SDAT 43 In/Out Control register input data (using EEPROM).

PWMI(1) 44 In Backlight control input. Power supply

VDD 16,34 In Digital power supply. VDDA 1 In Power supply for analog. VDDM 33 In mini-LVDS power supply. VSS 14,45 In Grounding for VDD.

VSSA 12 In Grounding for VDDA. VSSM 24 In Grounding for VDDM.

E-Pad - - Exposed pad is connected to VSS internally, the soldering coverage rate should be over 75%.

Note: (1) 5V tolerance input pads.




DATA SHEET V03

6. Function Description 6.1 LVDS receiver

The HX8861-H11 has a built-in single pixel LVDS receiver that converts data from differential serialized format to parallel output.

Ideal strobe position for LVDS input

6.5T/7

1.5T/7

2.5T/7

3.5T/7

4.5T/7

5.5T/7

0.5T/7

LVCLKN

LV0P

LV0N

T

LVCLKP

R[1] R[0] G[0] R[5] R[4] R[3] R[2]

Figure 6.1: LVDS input data ideal strobe position

LVDS input data mapping

Figure 6.2: LVDS input data mapping (VESA format)

Figure 6.3: LVDS input data mapping (JEIDA format)




DATA SHEET V03

6.2 Aging function

The HX8861-H11 is embedded with an aging generator for simplifying TFT LCD model dynamic burn-in test. When AGMODE pin is pulled to VDD and no clock is detected, the HX8861-H11 will operate at aging mode and generate BIST (Built-In Self Test) patterns as Figure 6.4. When AGMODE pin is low or open, and no clock is detected, the HX8861-H11 will generate black pattern.

Figure 6.4: BIST patterns

Figure 6.5: Free run timing

Spec. Symbol Parameter

Min. Typ. Max. Unit

tF Detection time 50 - 100 ms

6.3 Serial bus configuration

The HX8861-H11 can easily adjust parameter by serial bus including source/gate control timing, output data mapping, etc.




DATA SHEET V03

6.4 CABC function

The CABC function generates a PWM signal to control backlight modulation. The duty ratio of PWM is generated by image histogram and works with gamma correction. PWMO frequency will follow PWMI frequency when PWMI is a modulation signal. PWMO frequency can generate specific frequency (refer to below table) by internal setting if the PWMI is DC level.

Spec. Symbol Parameter Condition Min. Typ. Max.

Unit

FI Backlight control input Frequency CABC

Enable/Disable100 - 30K Hz

DI Backlight control input Duty CABC

Enable/Disable1 - 100 %

CABC Disable 100 - 30K(1)

STV*2n(2) Hz

FO Backlight control output FrequencyCABC Enable 100 -

STV*2n(2)

100K(3) 30K(4)

Hz

DO Backlight control output Duty CABC Disable 1 - 100 % Note: (1) PWMO frequency will follow PWMI

(2) PWMO is the multiple of STV frequency (n=0~10, n is integer) and independent of PWMI. (3) When PWMI frequency is always DC level. (4) When PWMI frequency is not DC level and PWMO frequency will follow PWMI.

6.5 Color engine function

The HX8861-H11 with color engine IP can support hue/saturation, brightness/ contrast, sharpness adjustment function.

6.6 Gate/source control timing

The HX8861-H11 generates control signals for source and gate drivers according to the settings in EEPROM. Examples of timing specifications are shown as below.

Description Symbol WXGA Unit

Reset pulse leading to TP1 td1 2064 mini-LVDS Clock High duration of TP1 tw1 99 mini-LVDS Clock Reset pulse leading to POL (1+2 line) td2 900 mini-LVDS Clock High/Low duration of POL (1+2 line) tw2 2 Line Reset pulse leading to CPV rising td3 2064 mini-LVDS Clock High duration of CPV tw3 1167 mini-LVDS Clock Reset pulse leading to STV rising td4 900 mini-LVDS Clock High duration of STV tw4 1 Line Reset pulse leading to OE1/OE2 rising td5 1728/1389 mini-LVDS Clock High duration of OE1/OE2 tw5 450/429 mini-LVDS Clock

Note: (1) The timing can be customized by different panel characteristics through ROM code.




DATA SHEET V03

Internal DE

mini-LVDS data

ML0P/N

ML2P/N

TP1

POL(1+ 2 line)

STV

OE1/2

MLCLKP/N

td1

td2

td4

td5

tw2

tw4

tw5

Internal DE

mini-LVDS data

TP1

CPV

STV

OE1/2

MLCLKP/N

POL (1+2 Line)

tw1

Reset Pulse

CPV

td3

tw3

~

Figure 6.6: Control signal output timing characteristic




DATA SHEET V03

6.7 POL inversion

Figure 6.7: POL 1+2 line frame inversion

6.8 Input signal timing

Parameter Symbol Condition WXGA Unit

Min. 1420 Clock Typ. 1526 Clock Horizontal total timing HT Max. 2047 Clock

Horizontal active timing HVD Typ. 1366 Clock Min. 771 Line Typ. 790 Line Vertical total timing VT Max. 2047 Line

Vertical active timing VVD Typ. 768 Line

Figure 6.8: Input video signal format




DATA SHEET V03

6.9 Seamless Dynamic Refresh Rate Switching (SDRRS) Seamless Dynamic Refresh Rate Switching (SDRRS) is a power saving technology that lowers the pixel clock frequency and frame rate to TFT LCD in response to power policy, and display activity. The HX8861-H11 will detect the loss of signals and drive the panel into a safe refresh mode. As a result of the actions of the HX8861-H11, the switch between refresh rates will not cause a noticeable impact on display quality. SDRRS response time

Invalid data Data at clock rate 2

Clock refresh rate 2

First active line

Data at clock rate 2






Last active line

mini-LVDS Data

mini-LVDS Clock

LVDS Data

LVDS Clock

DE

Blanking

T3

LVDS clock differential pair held at logical 0 value

LVDS data differential pairs held at logical 0 value

T1

T2

BlankingT4

Figure 6.9: TCON receive lock time at switching refresh rates

Spec. Symbol Parameter

Min. Typ. Max. Unit

T1 VBlank at refresh rate 1 2 - 3 LineT2 LVDS clock differential pair held at logical 0 value 50 - 100 µs T3 TCON receive lock time - - 200 µs T4 Refresh rate 2 to first active line 200 - - µs

6.10 Spread Spectrum Clock Generator (SSCG)

The SSCG function is used for reducing EMI. The modulation of SSCG IP is symmetrically centered and triangular on the output frequency. The specifications are detailed listed at section 8.4.




DATA SHEET V03

6.11 EEPROM mapping memory

6.11.1 TCON only: 4K bit memory space

Block Address 000 001 Word Address 00---FF 00---FF

Function Timing Timing 6.11.2 TCON + color engine: 6K bit memory space

Block Address 000 001 010 Word Address 00---FF 00---FF 00---FF

Function Timing Timing Color engine 6.11.3 TCON + CABC: 8K bit memory space

Block Address 000 001 010 011 Word Address 00---FF 00---FF 00---FF 00---FF

Function Timing Timing CABC 6.11.4 TCON + CABC + color engine: 10K bit memory space

Block Address 000 001 010 011 100 Word Address 00---FF 00---FF 00---FF 00---FF 00---FF

Function Timing Timing Color engine CABC 6.11.5 TCON + DGC: 10K bit memory space

Block Address 000 001 010 011 100 Word Address 00---FF 00---FF 00---FF 00---FF 00-00---FF F

Function Timing Timing Red

Gamma (DGC)

Green Gamma (DGC)

Blue Gamma (DGC)

6.11.6 TCON + color engine + DGC: 12K bit memory space

Block Address 000 001 010 011 100 101 Word Address 00---FF 00---FF 00---FF 00---FF 00---FF 00---FF

Function Timing Timing Color engineRed

Gamma (DGC)

Green Gamma (DGC)

Blue Gamma (DGC)

6.11.7 TCON + DGC + CABC: 14K bit memory space

Block Address 000 001 010 011 100 101 110 Word Address 00---FF 00---FF 00---FF 00---FF 00-00---FF F 00---FF 00---FF

Function Timing Timing Red

Gamma (DGC)

Green Gamma (DGC)

Blue Gamma (DGC)

CABC

6.11.8 TCON + color engine + DGC + CABC: 16K bit memory space

Block Address 000 001 010 011 100 101 110 111 Word Address 00---FF 00---FF 00---FF 00---FF 00---FF 00---FF 00---FF 00---FF

Function Timing Timing Color engineRed

Gamma (DGC)

Green Gamma (DGC)

Blue Gamma (DGC)

CABC




DATA SHEET V03

7. DC Characteristics 7.1 Absolute maximum ratings

Spec. Parameter Symbol

Min. Typ. Max. Unit

Supply voltage VDD -0.3 - +4.0 V CMOS/TTL input voltage VIN -0.3 - VDD V CMOS/TTL output voltage VOUT -0.3 - VDD V LVDS receiver input voltage VIN -0.3 - VDD V Storage temperature TSTG -40 - 125

Junction temperature TJ - - 125

Thermal resistance (junction ambient) ΘJA - - 100(1) /WNote: (1) For 2-layer standard JEDEC PCB.

7.2 Recommended operating conditions

Spec. Parameter Symbol Min. Typ. Max.

Unit

3.0(1) 3.3(1) 3.6(1) V Supply voltage VDD 2.3(2) 2.5(2) 2.7(2) V

Operating temperature TA 0 25 70 LVDS receiver input voltage VIN 0 - 2.4 V

Note: (1) For +3.3V operation. (2) For +2.5V operation.




DATA SHEET V03

7.3 DC electrical characteristics


Unit

IDD Supply current F=75MHz,

PI=14KΩ, RL=100Ωpixel checker pattern

- 54 - mA

CMOS/TTL DC Specifications VIH High level input voltage - 0.7VDD - VDD V VIL Low level input voltage - VSS - 0.3VDD V VOH High level output voltage - 0.8VDD - VDD V VOL Low level output voltage - VSS - 0.2VDD V IIN Input current - -10 - 10 A

VDD=3.3V 50 100 150 KΩ

RPD Pull low resistance

VDD=2.5V

CABC_EN (Pin 17)COLOR_EN (Pin 19)AGMODE (Pin 20)

TEST (Pin 41) PWMI (Pin 44)

75 150 225 KΩ

LVDS DC Specifications VTH Differential input high threshold - - +100 mV VTL Differential input low threshold

VIC=1.2V -100 - - mV

VIC LVDS common mode voltage - 0.7 - 1.6 V VID LVDS swing voltage - 100 - 600 mV

mini-LVDS DC Specifications

Output differential voltage range 100 - 600 mVVOD

Output differential voltage deviationVOD_CODE

*0.85(1) -

VOD_CODE

*1.15(1) mV

Output offset voltage range 0.6 - 1.3 V VOS

Output offset voltage deviation

RL=100Ω (TA=25)

VOS_CODE

-0.2(1) -

VOS_CODE

+0.2(1) V

DCLK Output clock duty - 45 50 55 % Note: (1) The VOD_CODE and VOS_CODE can be programmable by different panel characteristics through ROM code.

LVCLKN

LVCLKP

LVCLKP-LVCLKN

GND

0V

VID

VID

VID

VID

VIC

Figure 7.1: LVDS VID and VIC definition




DATA SHEET V03

Figure 7.2: mini-LVDS VOD and VOS definition




DATA SHEET V03

PI vs. VOD (RL=100Ω)

5 7 9 11 13 15PI(KΩ)

0

200

400

600

800

VOD (mV)

Figure 7.3: PI and VOD relation curve

7.4 ESD parameters

Parameter Symbol Spec. Unit Human Body Model HBM 2000 V Machine Model (C=200pF, R=0Ω) MM 200 V




DATA SHEET V03

8. AC Characteristics 8.1 LVDS AC electrical characteristics

Figure 8.1: LVDS channel to channel skew

Figure 8.2: LVDS input SSC

Spec. Symbol Parameter Condition

Min. Typ. Max. Unit

F LVDS Input frequency - 25 - 110 MHz

TLVSK LVDS channel to channel skew F=65MHz VIC=1.2V

VID=200mV-600 - +600 ps

FLVMOD Modulating frequency of input clock during SSC

10 - 300 KHz

FLVDEV Maximum deviation of input clock frequency during SSC

-3 - +3 %

TCY-CY Cycle to cycle jitter

F=85MHz VIC=1.2V

VID=200mV- - 200 ps




DATA SHEET V03

Phase Lock Loop wake-up time

Invalid

VDD

LVCLKP/N

Internal CLK

10ms

VTH

Invalid

Figure 8.3: PLL wake up time

Power up sequence

Internal Reset

VDD

0V

TRST TRST

VTH

VHYS

Figure 8.4: Power on reset

Spec. Symbol Parameter Condition

Min. Typ. Max. Unit

VTH Reset threshold voltage - 1.7 1.9 2.1 V VHYS Hysteresis voltage - 200 - - mVTRST Time constant of RC - - 0.8RC - s




DATA SHEET V03

OE1

VDD

LVDS

/HWRSTZ

STV

TP1/POL/OE2

1 2 3 4 5 6

1 frameData Out

MLCLKP/N

CPV

PWMO

EEPROMDownload

T2(1)

TRC(1)

Note: (1) 0ms < T2 < 50ms, T2 <TRC

Figure 8.5: Power up sequence




DATA SHEET V03

8.2 mini-LVDS AC electrical characteristics 8.2.1 mini-LVDS output data format

Figure 8.6: mini-LVDS output data format mini-LVDS skew control

mini-LVDS output skew can be adjusted by ROM code setting

SKEW Setup time(Tst1) Hold time(Thd1) Unit 0 4T/16 4T/16 1 3T/16 5T/16 2 2T/16 6T/16 3 1T/16 7T/16 4 5T/16 3T/16 5 6T/16 2T/16 6 7T/16 1T/16

T (mini-LVDS clock cycle)

mini-LVDS reset pulse

MLCLKP/N 0v0v

Tst1 Thd1 Tst1 Thd1

b0 b1 b2 b3 b4 b5 ML0P/N

ML2P/N

MLCLKP/N

ML0P/N Data Data Data Data

0V

Starting Data Sampling

1 2

11.5 clocks “H” 1.5 clock “L”ML5P/N




DATA SHEET V03

8.2.2 mini-LVDS output data mapping @ WXGA (1366X768) 8.2.2.1 Normal mode

Single port 3-pair

Data pair One line data ML0P/N 1R 2R 3R 4R 5R 6R 7R 8R --- 1365R 1366RML1P/N 1G 2G 3G 4G 5G 6G 7G 8G --- 1365G 1366GML2P/N 1B 2B 3B 4B 5B 6B 7B 8B --- 1365B 1366B

8.2.2.2 Dual-gate mode

Support four types of dual gate mapping

Pattern A

Dual gate data mapping ML0 ML1 ML2 Odd line 1R 1B 2G Type 0 Even line 1G 2R 2B Odd line 1R 2R 2G

Type 1 Even line 1G 1B 2B Odd line 1G 1B 2G

Type 2 Even line 1R 2R 2B Odd line 1R 2R 2B

Type3 Even line 1G 1B 2G

Pattern B

Dual gate data mapping ML0 ML1 ML2

Odd line 1G 2R 2B Type 0 Even line 1R 1B 2G Odd line 1G 1B 2B

Type 1 Even line 1R 2R 2G Odd line 1R 2R 2B

Type 2 Even line 1G 1B 2G Odd line 1G 1B 2G

Type3 Even line 1R 2R 2B




DATA SHEET V03

8.3 mini-LVDS output data swap by ROM code setting

The HX8861-H11 supports 2 swap types for 3-pair mini-LVDS output, including PN and Port swap. All these swapping settings are independent. Users can combine each swapping setting.

8.3.1 3-pair mini-LVDS data swap

SWAP SWAP V PN PN Pin no. Pin name

Port V Port 28 ML0P ML0N ML2P 27 ML0N ML0P ML2N 30 ML1P ML1N ML1P 29 ML1N ML1P ML1N 32 ML2P ML2N ML0P 31 ML2N ML2P ML0N 26 MLCLKP MLCLKN MLCLKP 25 MLCLKN MLCLKP MLCLKN




DATA SHEET V03

8.4 SSCG AC electrical characteristics


Unit

FMOD Modulation frequency LVDS input frequency=80MHz - 125 - KHzLVDS input frequency=80MHz

ROM code Setting 0 - 1 -

LVDS input frequency=80MHzROM code Setting 1

- 2 - FDEV Spread range

LVDS input frequency=80MHz ROM code Setting 3

- 3 -

%

Figure 8.7: SSCG profile

8.5 Oscillator AC electrical characteristics

Spec. Symbol Parameter ConditionMin. Typ. Max.

Unit

FOSC Oscillator frequency - FOSC*0.85 FOSC FOSC*1.15 MHz




DATA SHEET V03

9. Package Outline Dimension




DATA SHEET V03

10. Reference Circuit 10.1 HX8861-H11DDKG

VD

D

PW

MI

JP2

C16

0.1uF

R1

92

2O

E2

R14

14K

VD

D

CA

BC

_EN

JP5

LV1P

AGMODE

LV0

P

LV0

N

LV2

P

LVC

LKN

LVC

LKP

LV1

P

LV2

N

LV1

N

COLOR_EN

VD

D

CO

LOR

_EN

JP1

HX8861-H11DDKG

(QFN46)

VDD34

TEST41

SCLK42

SDAT43

LV2

P7

LV2

N6

LV1

P5

LV1

N4

LV0

P3

LV0

N2

VD

DA

1

COLOR_EN19

AGMODE20

ML

1N2

9

ML1

P3

0

ML

0N2

7

ML0

P2

8

ML

CLK

N2

5

MLC

LK

P2

6

PI21

N.C.22

VSSA12

LVC

LKP

9

VSS14

N.C.15

VDD16

CABC_EN17

/HWRSTZ18

OE139

CPV38

N.C.23 V

SS

M2

4

ML

2N3

1

ML2

P3

2

STV37

TP135

POL36

E-pad47

PWMO13

LVC

LKN

8

LV3N10

LV3P11

VDDM33

OE240

N.C.46

VSS45

PWMI44

LV2N

C9

C10

VD

D

HWRST

PWMI

CABC_EN

LV0P

LV2P

VD

D

ML

CLK

N

R1

01

00M

LC

LKP

C5

0.1uF

ML

2P

ML

2N

R4

100

LV0N

ML

1P

ML

1N

R6

100

VDD

LVC

LK

N

ML

0P

ML

0N

R9

100

VD

D

CN

1

FI-X

30S-H

F

Vin

30

Vin

29

Vin

28

SE

LLVD

S2

7N

C2

6T

ST_P

G2

5G

ND

24

LV0N

1

LV0

P2

LV1

P4

LV2N

5

LV2

P6

GN

D1

7

LV

CLK

N8

LVC

LK

P9

GN

D1

4

LV3N

10

LV3

P1

1

NC

12

NC

13

NC

15

NC

16

GN

D7

NC

18

NC

19

NC

20

NC

21

NC

22

NC

23

LV1N

3LV

1N

LVC

LK

P

PWMO

LV3

N

C4

0.1uF

C3

0.1uF

LV3

P

LV3N

PO

L

TP

R1

22

2

R1

32

2

VD

D

SC

LK

SD

AT

R2 4.7K

CP

VR

17

22

U1

EE

PR

OM

A0

1

A1

2

A2

3

VS

S4

SD

A5

SC

L6

WP

7

VC

C8

R1

62

2S

TV

R1 4.7K

C1

0.1uF

OE

1R

18

22

R7

100

R5

100

R3

100

R8

100

DC setting Pin

PI_A

LV3P

HW

RS

T

VD

D

C1

1

0.1uF

R1

110

0k

CABC function

VC

C

R1

5100

U3

LDO

Gnd

Vin

Vou

t

VD

D

JP

4

AG

MO

DE

SDAT

HX8861-H11DDKG : EEPROM 24LC32

C13

C12

VD

DA

L2

BE

AD

VD

DA

SCLK

TES

T

VD

D

JP

6

C15

C14

VD

DM

VD

DM

L3

BE

AD

VD

DM

Reset

VD

DA

VD

D

VIN

(5V)

PW

MO

JP

3

TEST

L1

BE

AD

F1

C6

C7

C8




DATA SHEET V03

10.2 HX8861-H11DDKG-E

VD

D

PW

MI

JP2

C16

0.1uF

R1

92

2O

E2

R14

14K

VD

D

CA

BC

_EN

JP5

LV1P

AGMODE

LV0

P

LV0

N

LV2

P

LVC

LKN

LVC

LKP

LV1

P

LV2

N

LV1

N

COLOR_EN

VD

D

CO

LOR

_EN

JP1

LV2N

C9

C10

VD

D

HWRST

PWMI

CABC_EN

LV0P

LV2P

VD

D

ML

CLK

N

R1

01

00M

LC

LKP

C5

0.1uF

ML

2P

ML

2N

R4

100

LV0N

ML

1P

ML

1N

R6

100

VDD

LVC

LK

N

ML

0P

ML

0N

R9

100

VD

D

CN

1

FI-X

30S-H

F

Vin

30

Vin

29

Vin

28

SE

LLVD

S2

7N

C2

6T

ST_P

G2

5G

ND

24

LV0N

1

LV0

P2

LV1

P4

LV2N

5

LV2

P6

GN

D1

7

LV

CLK

N8

LVC

LK

P9

GN

D1

4

LV3N

10

LV3

P1

1

NC

12

NC

13

NC

15

NC

16

GN

D7

NC

18

NC

19

NC

20

NC

21

NC

22

NC

23

LV1N

3LV

1N

LVC

LK

P

PWMO

LV3

N

C4

0.1uF

C3

0.1uF

LV3

P

LV3N

PO

L

TP

R1

22

2

R1

32

2

VD

D

SC

LK

SD

AT

R2 4.7K

CP

VR

17

22

U1

EE

PR

OM

A0

1

A1

2

A2

3

VS

S4

SD

A5

SC

L6

WP

7

VC

C8

R1

62

2S

TV

R1 4.7K

C1

0.1uF

OE

1

HX8861-H11DDKG-E

(QFN46)

VDD34

TEST41

SCLK42

SDAT43

LV2

P7

LV2

N6

LV1

P5

LV1

N4

LV0

P3

LV0

N2

VD

DA

1

COLOR_EN19

AGMODE20

ML

1N2

9

ML1

P3

0

ML

0N2

7

ML0

P2

8

ML

CLK

N2

5

MLC

LK

P2

6

PI21

N.C.22

VSSA12

LVC

LKP

9

VSS14

N.C.15

VDD16

CABC_EN17

/HWRSTZ18

OE139

CPV38

N.C.23 V

SS

M2

4

ML

2N3

1

ML2

P3

2

STV37

TP135

POL36

E-pad47

PWMO13

LVC

LKN

8

LV3N10

LV3P11

VDDM33

OE240

N.C.46

VSS45

PWMI44

R1

82

2

R7

100

R5

100

R3

100

R8

100

DC setting Pin

PI_A

LV3P

HW

RS

T

VD

D

C1

1

0.1uF

R1

110

0k

CABC function

VC

C

R1

5100

U3

LDO

Gnd

Vin

Vou

t

VD

D

JP

4

AG

MO

DE

SDAT

HX8861-H11DDKG-E : EEPROM 24LC16

C13

C12

VD

DA

L2

BE

AD

VD

DA

SCLK

TES

T

VD

D

JP

6

C15

C14

VD

DM

VD

DM

L3

BE

AD

VD

DM

Reset

VD

DA

VD

D

VIN

(5V)

PW

MO

JP

3

TEST

L1

BE

AD

F1

C6

C7

C8




DATA SHEET V03

11. Ordering Information

Device Package Description HX8861-H11DDKG 46-pin QFN green package Support ≧32K bit EEPROM only HX8861-H11DDKG-E 46-pin QFN green package Support 2K to 16K bit EEPROM only

12. Revision History

Version Date Description of Changes 01 2012/01/16 New setup. 02 2012/06/19 Page 2, 24, 25

Add HX8861-H11DDKG-E: support 2K to 16K bit EEPROM only.

03 2014/05/27 All pages Remove ‘preliminary’ wording.

Page 14 Fill spec. in “Supply current (IDD)“ Modify “mini-LVDS DC specifications”.

Page 23 Modify spec. of “Oscillator frequency(FOSC)”

HX8861-H11 DS v03 - Phoenix Display

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