HPES : High Performance Embedded Systems · Consortium HPES Architecture Control / Command...
Transcript of HPES : High Performance Embedded Systems · Consortium HPES Architecture Control / Command...
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HPES : High PerformanceEmbedded Systems
HPES Team :
Charles H.-P., Fesquet L., Lesecq S., Mancini S., Marchand N., Méhaut J-F., Rastello F. , Rutten E., Bogdan Robu
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Processing evolution
Jack DongarraSupercomputing2013
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Processing evolution
Jack DongarraSupercomputing2013
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HPC Roadmap with Low Power Processors
2011 2012 2013 2014 2015 2016
Integrated ARM+ Accelerator
200 PFLOPS10 MWatt
ARM Multicore+ Discrete GPU
2017 2018 2019 2020
ARMMulticore
1 EFLOPS20 MWatt
1018 FLOPSGF
LOP
S / W
att
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<< le Kirin 980,
● le premier processeur mobile 7nm au monde,
● le premier processeur d'architecture cortex-A76 au monde,
● le premier processeur double NPU IA au monde, et
● le premier processeur au monde à supporter la 4G Cat. 21.
Le Kirin 980 combine de multiples innovations technologiques et mène la tendance IA pour offrir aux utilisateurs des performances mobiles impressionnantes avec une expérience plus pratique et intelligente.>>https://www.hihonor.com/fr/tech/kirin980/
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Scientific questions
● Multiples view on computing :– Control command
– Computer Architecture
– Compilation / optimization
● Strong convergence– High Performance Computing
● Evolving need (Scalability)
● Power limited (20 MW)
– Embedded system● Power efficient
● Scalability
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Computer Architecture
Scientific problems :
● Memory wall
● 3D Stacking
● Energy versus power
● Dark Silicon
Challenges :
● Moore law is over (mostly)
● Amdhal law is forever
Complete and autonomous system: Scalable processor Scalable dynamic memory Non Volatile memory Power management
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Compilation / optimization
Scientific problems : Adapt high level programs to low level computer architecture– Low level architecture become extremly complex and evolve quickly
– High level programs are not « hardware aware »
Challenges :– Performances are data dependent : how to adapt code to data sets
– Characterization are complex (timing, power, memory subsystem)
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Control command
Scientific problems :
Challenges : – Multi-level view is needed
– Modelisation of very complex objects (hardware, software + application + data sets)
System yControlleru
Ref(setpoint)
Observer
SSS
A
A
S: sensorA: actuator
x: system state(not always fully measured)
x
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Consortium HPES
Architecture Control / Command Compilation
TIMA Laurent FesquetStéphane Mancini
CEA Suzanne Lesecq Henri-Pierre Charles
INRIA Eric Rutten Fabrice Rastello
GIPSA Nicolas MarchandBogdan Robu
LIG Jean-François Méhaut
10
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Global Vision
● Understand and apply control command system on complex hybrid hardware / software stack
● Make hardware manageable
● Make software « performance aware »
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Initial schedule
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Work plan
● Internal workshops– 18/10/2013 : Suzanne Lesecq : Control Activities for SOC
– 28/11/2013 : HP Charles : ``Compilettes'' for dummies
– 27/01/2014 : Stéphane Mancini : Le cache ND-AP pré chargements adaptatif pour les tableaux
– 1/04/ 2014 : JF Méhaut : Improving the performance of transactional memory application on multicores : a machine learning based approach
● External workshop – « Journées de la compilation » Décembre 2013
– « Control of computing systems » May 2014 (persyval-lab exploratory project STAARS)
– Workshop during HiPEAC 2015 (European conference on Architecture & Compilation)
● PhD / Postdoc co-advised students– Postdoc : Lionel Vincent
– PhD student : Naweiluo Zhou
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Post doc : Lionel Vincent
Architecture Control / Command Compilation
TIMAStéphane Mancini
CEA Suzanne Lesecq Henri-Pierre Charles
« Memory hierarchy driven dynamic code generation »
● Design more efficient data management strategies by simultaneously considering HW & SW :– Software will be modified by dynamic compilations strategies, in order to fit the cache
– Extract application metrix and adapt its behaviour to software. The prefetching mechanism will try to predict next references from a customized function depending on the past references. To stabilize the system, the hardware/software interaction will be embedded in a control loop
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Initial Bibliography
Prefetcher
Software
Manual Compiler
Intel Compiler
Gnu Compiler
Hardware
Stride
Stream
GHB
Hybride
Mixt: HW/Sw/ Control
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PhD : Naweiluo Zhou
Architecture Control / Command Compilation
INRIA Eric Rutten
LIG Jean-François Méhaut
Application-aware policies and control for transactional memory systems
● Transactional Memory● Optimistic Approach for Synchronization on multiprocessorsAccesses to shared data encapsulated in transactions
● Issues : run-time adaptation, by autonomic management, of : parallelism level, thread mapping, transaction management
● Discrete Control● Control techniques for supervising discrete event systems
● Reactive synchronous language, used to design safe autonomic loops
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Application-aware policies and control for transactional memory systems
● Approaches● Identifying autonomic loops of transactional memory systems, including
application-dependent, potentially with control theory● Introducing reactive programming and discrete control in loops for thread
mapping and transaction management
● Controlling their coordination with discrete control
● Experimental platform● SMP-NUMA machine (192 cores, 800 GB memory)
● Software : TinySTM, BZR/Heptagon, Eigenbench, STAMP
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Conclusion● PERSYVAL : an unique opportunity to break barrier between our
teams– Claim : « Multi disciplinarity leads to innovation »
– Initial steps, but the road is free
● Persyval : funding for local collaborations : unique ! Dimensions :– Software / Hardware ;
– Academic / Engineering ;
– St Martin d’Hères / Presqu’ile
● Web site : https://persyval-lab.org/en/sites/hpes