Homework/Project Guide One can check the Xilinx ISE 9 Tutorial at the following link: http://www.xilinx.com/support/techsup/tutorials/tutorials9.htm Reading the documentation may save your time.

Before starting the homework/Project, you will need to create a folder first. Let’s assume that you are taking CMPEN297B class this semester. From the Start menu, click 'My Computer' and create C:\cmpen297B folder and collect all your homework projects in this folder.

Start the ISE Project Navigator.

Under the File pull down menu, select the New Project…

Before typing the Project Name, you MUST specify Project Location. Specify C:\cmpen297B folder that was just created.

Now type the project name. In this case, you will be creating the Homework 5 project and you will be turning in your project as your homework, so you must name the project with your last name. Make the project name as your last name

after "hw5_". For example, my project name will be 'hw5_choi'. Keeping this project/folder name convention is important, for you to get full credit of your work. When I name my project hw5_choi, the ISE program will create a sub-folder C:\cmpen297B\ hw5_choi and collects all the project files in it. If your last name is longer than 8 characters, use only the first 8 character of your last name.

Select the following properties into the homework 5 project wizard window. These same properties will be used for all the homework. Family => Spartan3 Top-Level Source Type => HDL Device => XC3S200 Synthesis Tool => XST (VHDL/Verilog) Package => VQ100 Simulator => ISE Simulator (VHDL/Verilog) or ModelSim Speed => -5 Preferred Language => VHDL

Click Next on the subsequent window.

Again click Next on the subsequent window.

Check the properties and click Next on the subsequent window.

You will see the similar ISE project navigator window shown below. Right click the device xc3s200-5vq100 and select the New Source… option.

Now select the Schematic on the left and type the file name. In this case, you will be creating a file with an AND gate. Also, ALL file names must contain your initials in the beginning. For example, my file name with 2-input AND gate circuit will be 'kcand2' for my first name initial "k" and my last name initial "c" is added to the beginning of the file name. Keeping this file name convention is important, for you to get full credit of your work. (click VHDL Module if you want to create VHDL project instead of Schematic)

Once you see the ISE project navigator window similar to the one below, click on the kcand2.sch tab on lower middle left (next to Design Summary tab).

And Maximize the ISE window as shown below.

Click on the bottom of “Symbols” window and drag down to enlarge the “Symbols” window as shown below.

Scroll the Symbols window list on the left and click the and2 item.

Move the cursor to the right, on the kcand2.sch window and click. Center the 2 input AND gate symbol and click zoom in. The AND gate symbol will follow the cursor, hit Esc key on your keyboard to end the Insert Symbol mode.

Click Add Wire button and add wires to AND2 gate symbol. Simply click at the symbol’s signal wire end, then drag to add the wire.

Add wires to all of AND2 gate input and output. Then, click on Add I/O Maker button and click on the wire ends to put I/O to wires.

Double click on the I/O, and change I/O names to ‘a’, ‘b’, and ‘z’.

Click Save button to save the schematic file just created. Then click Sources tab and Processes tab on the left side of the ISE window.

Double click Synthesize – XST on the left Processes window.

Then double click “Implement Design” on the left Processes window.

You must see the green check marks, otherwise check the error message and correct your schematic design. WARNING on the Console window can be ignored.

Now right click on the kcand2 in the left Sources window and select New Source… option. And type the file name, name with TBW – Test Bench WaveForm – to test your design.

Zoom in and click the blue tic marks to create your own input signals. Then click Save button.

Now go to Sources for: box selection on the upper left (above Sources window) and select Post-Route Simulation option. Then double click Simulate Post-Place & Route Model under the Xilinx ISE Simulator in the Processes window.

Then enter 10000 ns for simulation time and click on the “Run for Specified Time” button.

Then click on the “Zoom to Full View” button.

Make an observation and check to see if the output signal ‘z’ is correct. Try left click, right click, and other button click to explore the simulation window features and be familiar with the tool. You may print the ISE Simulator output wave. Or capture the Simulator window with Alt-Print Screen key and paste it on a MS Word file. Finally, go to ISE window, click on “Project” pull down menu on the top. Select the option “Cleanup Project Files”. Delete all the intermediate files by clicking “OK” when prompted. These are the files generated by “Synthesize” and “Implement” steps. Now the Homework 5 is almost ready to turn-in. Quit ISE. In your C:\cmpen297B folder, you will see hw5_yourname sub-folder. ZIP it and turnin through ANGEL the hw5_yourname.zip file.