0

Confidential

High Performance DRAM Trend

& Future Test Requirements

DRAM Product Planning and Enabling OfficeSK hynix Inc.

1

Contents

II

ICT Trend

Memory Requirement by Key Applications

III Test Requirements

I

Visualization(VR/AR)

Connected(IoT)

Network & Storage

A.I. & Machine learning

Big Data

IT Trends Mobile & Wearable

ICT Mega Trend

The usage of smartphone to access data keeps increasing, and this makes client focus on developing Hybrid PCs for better mobility

Source : Stat Counter, 2014.12

Searching Info

2009 2014

99%

1%

65%

35%

Through PC Decreases

Through Mobile Increases

Good Mobility

High Performance

Developing toward..

Laptop Hybrid PC

DesktopFor Gaming, Workstation

Transition from PC Era to Mobile Era

As smartphone reached saturation, Wearable & IoT devices are leading the Post Mobile era and expand the area with smartphone as a Hub device

$387 $2602018F2012

Smartphone ASP Forecast

0

20

40

60

80

100

120

25%

102%

2008 20142010

SmartphoneGrowth Rate

-77%p

Post Mobile Application

Mobile NetworkAutomotive

Wearable Device & Sensor

Security

Smart Home Applications

Home Network

Hub / CentralControl device

Smartphone

Source : IDC 2014 / IDC, Gartner, Strategy Analytics, TrendSpectrum, 2014.12

Post-Mobile Era

* UHD: 3840 x 2160 QHD: 2560 x 1440

Higher

Resolution

Higher Data

Usage

Graphic

Performance

Improvement

Development of visualization in displays for UHD contents is driving hardware performance improvement.

110”

Computing

Mobile

5.7”4.x”3.5”

~10”

~30”

<30”

Time / Phase

TV

~ HD FHD/QHD UHD

Screen Size

Visualization for User Experience w/ UHD Contents

Source : Cisco 2015

IoE brings all things together through P2P, P2M, and M2M connections

& enables entirely new sets of applications and ways of business

IOEPeople to Machine(P2M)

Machine to Machine(M2M)

People to People(P2P)

• Mobility• Security• Borderless NTW

• Cloud• Vertical Solutions• Social Media

IoT

Collaboration

Data &Analytics

IoE (Internet of Everything)

• Data Center• Big Data• Cloud

M2M

P2P

P2M

Everything is Connected (Internet of Everything)

Automotive in IoT

Vehicle to Home Vehicle to Vehicle

Vehicle to Infrastructure

Cloud

Infotainment

Vehicle to Mobile/Wearable

Telematics Driver assistance

• Home gateway (Home appliance)

• Vehicle condition

• Control (window, air, light)

• Call (Pick me up)

• Navigation

• HUD (Head up display)

• Rear seat entertainment

• Data analysis (OEMs, insurance)

• UX (Driving pattern)

• System update

• Communicate with traffic infra

• Recognition (Speed, surround)

• Vehicle communication

• Parking assistance

• Pedestrian recognition

• Voice, motion recognition

• LTE network

• Emergency call

Source : SK hynix marketing

Autonomous Driving

• Sensor Fusion & DNN

A device is not solely operated itself but it connects devices around you for better services.

Performance

Power Consumption

Cost

HPC Extension

Mega datacenter Extension

Scale-up or Scale-out

Rack Disaggregation

Software Defined

Datacenter

Datacenter is evolving as the data increase explosively

And a strong network is vital to positioning Datacenter for the IoT era

NetworkIPv6, ONIE, SDN NFV

Data Center Oriented Infrastructure Changes

Source : SK hynix DRAM product planning & enabling office

DRAM Scaling Limits

ICT Trend & Value-chain

Big Data

IoT, IoE

Data in Motion

Analytics

simultaneous

Preparations

Data Center Traffic3.1ZB @’13 8.6ZB @’18 (CAGR23%)

Vertical Integration towardService-centric Industry

2006 (~um) 2016 (1x nm)

~9$

~0.x$# of Process StepsCAGR < 5%

Technology Complexity ∝ Capex Expenditure

# of Process StepsCAGR > 5%ASP CAGR -30%

(1Gb Eq.)

Follow the scalability requirement of system with

existing infra- structure

DDR4, P-DDR4, P-LPDDR4

Architecture Breakthrough to meet future system

performance requirement

Total OptimizationMemory hierarchy tiering Stacking technology

Evolutionary

Revolutionary

Database Serversin-MemoryComputing

System Architecture

HPC Memory Bandwidth/node100~500GB/s @’15 2~4TB/s @’19

Computing Intensive Data Intensive

Data

Query

?

Memory Hierarchy

Simultaneous

Changes

Networks

Role Sharing of Memory Solutions: B/W vs. Capacity

HBM*(B/W) HCM*

(Capacity)

* HBM : High Bandwidth Memory* HCM : High Capacity Memory

++

ICT Industry Outlook – Changes & Preparations

Contents

II

ICT Trend

Memory Requirement by Key Applications

III Test Requirements

I

DRAM Technology Changes – Evolutionary & Revolutionary

DRAM will have two separate tracks due to various market requirements

High CapacityMemory

High Bandwidth Memory

Persistent Memory

Bandwidth/ Latency

Density

Storage

DRAM

② RevolutionaryPath

② RevolutionaryPath

② RevolutionaryPath

① EvolutionaryPath

Longevity

“Market”

① Evolutionary Path : DRAM Volume Market with proven technology & Infrastructure② Revolutionary Path : Satisfy Performance hunger, requires New Solution/biz/Service model

DRAM Technology Trend – Evolutionary Path

Majority of DRAM solutions are continuously evolving and breaking through its limitations of bandwidth to meet the industry’s requirements

DRAM Bandwidth Trend by Mode (Mbps)

2000

36004000

5000

6000

7000 7000 7000

8000

10000

12000

14000

16000

10661333 1333

1600 1600 1866 2133

2133 24002666

32003733

4266

5333 5333

6400

667 8001066 1066

1600 16001866

3200 32003733

4266

5333

6400 6400

7466

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023

DDR3

P-LPDDR4

LPDDR4

LPDDR4XGDDR3

GDDR5

P-GDDR5

LPDDR2 LPDDR3DDR4

P-DDR4

* Source: SK hynix

Up to 30X of OLTP Performance Gains

Up to 100X of Faster Star Join Queries

90% of Disk Space SavingsCPU

~0.5 inch, delivers 256GB/s each

In-Package Memory In-Memory Computing

~5 inch, deliversmax. 25.6GB/s

Conventional DDR3/4 subsystem

100X of Area/Bandwidth

* Microsoft SQL Server Blog

MemoryRequest/Query

Results

CPU M/C

CPU M/C

Query

Results

Memory

Logi

c

Memory

Logi

c

Memory

Logi

c

Memory

Logi

c

DRAM Technology Trend – Revolutionary Path (1/2)

DRAM Technology Trend – Revolutionary Path (2/2)

CPU DD

R M

C

Existing Memory

I/O

Storage

[Existing System]

CPU

DD

R M

C Existing Memory

I/O

Storage

NEW

MC

Capacity Memory Solution

[New System]

HBM

Glo

bal

PH

Y

Flow Control

Media Controller

Co

mm

on

PH

Y

NewMemory

(DRAM, NAND, Emerging Memory)

Capacity Memory Solution

To Host

Memory Media Controller Memory Media

• I/O Performance Wall Limit

• DRAM Refresh Power Issues

• DRAM Reliability Issues

High Capacity & Memory-agnostic Solution

In-Memory Computing

Big data applications require instant data processing and analysis,

which makes companies turn to in-memory computing

HDD Time = 50 milisec

Memory Bandwidth >100GB/s

Database Analytic Servers Visualization & Reporting

Computing Intensive

Memory Bandwidth 1GB/s ~ 4GB/s

Data Results

RequestQuery

AnalyticsIn-memory Computing

Visualization & Reporting

Request/Query

Results

In-Memory Computing

Memory

CPU

In-MemoryComputing

50ns

* Source: SK hynix

Data Intensive

Gaming Graphics

High-end gaming Graphics drives needs for HBM products

with limited power consumption.

0

200

400

600

800

1000

1200

1400

8GB

12GB 16GB

24GB

32GB

System BW [GB/s]

□ HBM○ GDDR6○ GDDR5x- GDDR5

0

200

400

600

800

1000

1200

1400

0

4000

8000

12000

16000

20000

24000

28000

32000

2006 2008 2010 2012 2014 2016 2018 2020 2022

FB Size(MB)

* Raw data from Wikipedia

High-end Graphic Card FB Size/ Memory BW Trend

Density/ BW configuration

System BW(GB/s)

2018 2020

FB Size ~17GB ~24GB

Bandwidth ~630GB/s ~1000GB/s

20172014 2015 2016 2018 2019 2020 2021

LPDDR2, 800/1066

LPDDR3, 1600/1866

LPDDR4, 3200/3733

LPDDR4X, 3733/4266

LPDDR5, 4800/5333 (6400?)Arising LPDDR4 Derivatives for Low Power Request

LPDDR4/4X(~3200)

LPDDR4(3200/3733)

LPDDR4X(3733)

LPDDR4X(4266)

LPDDR4X(4266)

LPDDR5(4800/5333)

LPDDR5(6400?)

LPDDR4/4X(~3200)

LPDDR4/4X(3733~)

LPDDR4/4X(3733~)

LPDDR3(~1866)

LPDDR3(~1866)

LPDDR3(~1866)

Time

Performance

FOWLP

Source : SK hynix marketing

Mobile

High performance, high density while keeping low power Additionally requires thinner PKG thickness

Wire Bonding (WB)

Planer PKGw/ WB

Future Memory Hierarchy by Applications

#1. Cost optimum memory for general memory usage cases. #2. Additional Bandwidth and Low Power Memory Cost solution (2.5D or 3D Stacking)

HPC & Server

(B/W & Capacity)

Network& Graphics

(B/W)

Client-DT& NB

(B/W & Cost)

Mobile& Wearable

(LP, Small Form Factor, B/W &

Cost)

+

Bandwidth Solution

Cost Solution

+

Bandwidth Solution

Bandwidth Solution

+

Bandwidth Solution Capacity Solution

B/W

B/W &Capacity

B/W

B/WB/W & Cost

Post-DDR4

LP & Bandwidth Solution

LP & B/W

+

Post-DDR4

+

Contents

II

ICT Trend

Memory Requirement by Key Applications

III Test Requirements

I

Future Memory System with 2.5D and 3D Stack

PHYTSVDA ball

DRAM Slice

DRAM Slice

DRAM Slice

DRAM Slice

Interposer

SoC

PHY

Sid

e M

old

ing

Sid

e M

old

ing

SoC

DRAM Slice

DRAM Slice

PCB

2.5D Stack for HBMx Products- 1K IOs

3D Stack Concept- 512 IOs (WIDE IO SDR/DDR)

Industry has been focused on high bandwidth and low power solution with 2.5D and 3D stack products.

It requires advanced memory testing capability for wide IO memory cube.

Base die in KGSD consists of PHY, TSV and DA area. • PHY interconnects to host PHY• TSV interconnects to core slices• DA interconnects to PKG ball for DRAM test (limited pins)

Fine Ball Grid Array HBM in SiP

KGSD

ADD/CMD, DQ (RX/TX),

SIGNAL Connectivity Test

TSV OVERLAPDRAM POWER

Supply

DA BALL(Direct Access)

DFT(TEST Logic)

PHYTSV AreaDFT Area

Base Die

PHYTSVDA ball

DRAM Slice

DRAM Slice

DRAM Slice

DRAM Slice

Interposer

SoC

PHY

Sid

e M

old

ing

Sid

e M

old

ing

HBM2 KGSD

IEEE 1500 MBIST

DRAM CORE DIE

DRAM CORE DIE

DRAM CORE DIE

DRAM CORE DIE

DRAM BASE DIE

DAB

SLICE 3

SLICE 2

SLICE 1

SLICE 0

PHY

Future Test Requirements for Wide IO Products

DA pad (8DQs (for 1024 IO) and

address and control signals )

Requires to KGSD test via microbumps at PHY area without damage of itself.

HBM2 Memory Cube

Future Test Requirements for High Speed

CPU

Server CPU & Memory

………… Vref

Data Eye at Receiver

1600Mbps 3200Mbps 6400Mbps

Trend to have Rx equalizer in DRAM for multi-drop topologyNo way to measure eye margin at high speed interface along with multi-drop system.

?

Test Considerations

Each application needs the specific Packaging & test equipmentSpecially Commodity Memory needs Innovative pass/fail judge scheme under multi-

drop system beyond 4Gbps

PKGing Socket Testing

Mobile(PKG) Many ballsMulti-stacking

Fine pitchFine ball

P2PData eye for 8.5Gbps

High performance memory(2.5D/3D)

TSV stacking No SocketInterposer/Silicon

BISTIO Connectivity

Computing (DIMM) Conventional Narrow DIMM Pitch 고려 필요

Test timeData eye @ Multi-drop(up to 6.4Gbps)