High efficiency heterojunction with intrinsic thin layer...

High efficiency heterojunction with intrinsic thin layer solar cell: A short review

S. M. Iftiquar*,1,Youngseok Lee2, Vinh Ai Dao1 , Sangho Kim2 and Junsin Yi1,2,* 1 College of Information and Communication, Sungkyunkwan University, Suwon 440-746, Korea 2 Department of Energy Science, Sungkyunkwan University, Suwon 440-746, Korea * Corresponding Author: Junsin Yi (E-mail: [email protected]), Tel: +82-31-290-7139, Fax: +82-31-290-7159 * S M Iftiquar (Email: [email protected])

Heterojunction with intrinsic thin layer (HIT) solar cell has attracted attention of photovoltaic research community due to its low process temperature, as compared to crystalline silicon (c-Si) solar cell and relatively high efficiency (η). In this solar cell structure, thin intrinsic amorphous silicon layers are used as surface passivator, which also acts as buffer layer at the top as well as bottom surfaces of n-type crystalline silicon (c-Si) wafer. A thin p-type a-Si top layer acts as an emitter while highly doped n+-type bottom layer is used as a back surface field. There have been suggestions that the device performance comes with significant tunnelling transport of the charge carriers across junction barriers, whereas other investigation suggests that the diffusion of the carriers may be adequate. Various experimental as well as theoretical investigations were carried out to characterize and improve performance of HIT solar cell. For example, it was reported that a thicker p-type emitter (up to 40nm) shows higher open circuit voltage, although short circuit current density (Jsc) and cell efficiency decreases. Recent investigation showed that when the p-type and i-type layer thickness increased (within 4 nm) the open circuit voltage (Voc) as well as the efficiency improves. Using thinner c-Si absorbed is another interesting aspect in which a light trapping scheme can be combined to achieve a better performance characteristics. There has been several theoretical as well as experimental investigations on the use of various types of emitter layer and intrinsic layer of the cell, and their role on the Jsc, Voc, η and fill factor (FF). Investigations of HIT solar cell on p-type c-Si wafers have also been carried out. In this article we will present a brief review on some of the important aspects of the HIT solar cell.

Keywords HIT solar cell; amorphous silicon, crystalline silicon

1. Introduction

Amorphous silicon is a low cost alternative to the crystalline silicon (c-Si) technology. Although the c-Si solar cells have high photo-voltaic (PV) conversion efficiency, however, this technology is also associated with higher production cost, thermal budget and requirement of good quality Si. Due to the higher processing temperature, the existing defects in c-Si wafers may exhibit further deteriorative effect. Thus a combination of both the crystalline and amorphous Si technology in the form of the heterojunction with intrinsic thin layer (HIT) solar cell became one of the best options. The HIT solar cell is patented by Sanyo Electric Company and became popular among researchers. The interesting features of the cells like the high PV conversion efficiency (η) and lower processing temperature, that made it attractive for its large scale commercialization, to satisfy the demand for alternative source of energy to the fossil fuel or nuclear energy. Development of HIT solar cells has been reported as early as 1991 [1,2] when p/n heterojunction solar cell was investigated with p-type a-Si:H and n-type c-Si wafers. An introduction of a thin intrinsic a-Si:H layer in between the p-type and n-type Si showed a further enhancement of the device performance and the blue response of the external quantum efficiency (QE) better.A systematic variation in the thickness of the i-type a-Si:H layer showed that with increase in its thickness, the Jsc, FF, efficiency decreased [3], highlighting the need of an optimized thickness. Since the demonstration of 15% cell efficiency as above, several interesting results were also reported. Glow discharge and DC magnetron sputtered deposition of the a-Si:H layers on the c-Si wafers and their investigation revealed that the a-Si/c-Si interface characteristics is one of the most important parameters that controls solar cell performance [4]. Cleef et al. and others have investigated p-type a-SiC:H materials for the HIT structure in 1998, that resulted in high FF of the device [5, 6]. It indicates that the valence band discontinuity in the interface between the p-type emitter and n-type c-Si leads to a significant loss in photo generated carriers. It has been suggested that the electron-hole recombination in the heterointerface may not influence the open circuit voltage, although it may influence the current density [6]. As light enters from air to Si surface, a certain amount of it will be reflected. Such a reflection loss can be reduced by a textured front surface [7]. With increased light trapping, the short circuit current density is expected to increase. However, with increased texturing, the surface becomes more defective and needs further optimized surface passivation. N-type [8] and p-type Si absorbers were investigated for such an improvement [9] although the n-type wafer performs better (17.6 % in above ref) in comparison to the p-type one (16.4% in above ref). Surface passivation of the c-Si wafer is one of most important steps to obtain higher minority carrier lifetime and open circuit voltage. If average surface defect density is Nts, then total surface defect will be NtsA1, where the A1 is

Materials and processes for energy: communicating current research and technological developments (A. Méndez-Vilas, Ed.)____________________________________________________________________________________________________

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total surface area. Thus, with increased surface area per unit solar irradiance may lead to reduced Voc. This situation arises with rough or textured surfaces. Even though recombination at the a-Si/c-Si interface is made negligible, it was suggested that it’s not only the interface recombination that is a crucial factor for optimized cell performance [10]. A part of the light trapping structure includes lower reflection and absorption loss at the front TCO layer. The reflection happens because of difference in refractive index between two layers. Refractive index (RI) of a-Si:H is within 4 to 5 and that of air is 1. Thus, TCO film having refractive index somewhere within the 1 & 5, may show better optical transmission. ITO film has lower RI than that of H doped In2O3 (IO:H). However, the optical absorption in IO:H is lower than that in ITO. It has been reported that, a better performance of a solar cell with IO:H as front electrode [11] is possible. Cost of Si raw material is another aspect to look into for large scale production. So, thinner wafers were also used for HIT solar cells eg. 250 μm [7], 98 μm [12]. Because of lower processing temperature, these cells did not show warping. Furthermore, with thinner absorbers the open circuit voltage increases, possibly because of reduced bulk recombination of the charge carriers. Carrier transport across the HIT cell structure is another aspect that has been investigated extensively. A drift diffusion of charge carriers take place at various stages, where the drift exists mostly in the region with high electric field and diffusion of carriers when the carrier concentration gradient exists. However at the heterojunction interface, it may be possible that the discontinuity in the energy bands will lead to trapping of charge carriers and tunneling. It has been reported that such a tunneling of charge carriers play an important role in performance of HIT solar cell [13, 14].

1.1 Operation of HIT solar cell

The principle of operation of the HIT solar cell can be described in equation (1), with current density(J) versus voltage (V) relation ( ) = ( ) − 1 + ( ) − 1 + − (1)

where q is electron charge, Jph is photo current density, J01,2 are reverse saturation current densities, n diode ideality factor, k Boltzmann constant, T temperature, Rs series resistance, Rp parallel resistance, A1 is a temperature independent constant. In a two diode model (D1, D2) the solar cell equivalent circuit can be drawn as in Fig. 1(a), while the Fig. 1(b) shows typical current - voltage characteristics at various temperatures. One of the basic features of the HIT solar cell can be illustrated with a schematic band diagram, fig 2(a). Because of different energy band structure of the layers, the unwanted reverse flow of charge carriers can be reduced to a great extent. The conduction and valence band discontinuities prevent electrons and holes to travel towards p-type and n-type layers respectively, whereas the valence and conduction band continuities help a smooth diffusion and tunneling of the holes and electrons towards the p-type and n-type layers respectively. A theoretical simulation indicated that a high discontinuity in the conduction band at the p/i interface prevents electron back diffusion from the i-type layer to the p-type layer and thus reducing loss of minority carriers at the p-type layer [15].

(a) (b)

Fig. 1. (a) Solar cell equivalent circuit, Jph – photo-generated current density. (b) Current density (J)-voltage characteristics of the HIT cell under dark, without intrinsic a-Si:H layer.


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(a) (b)

Fig. 2. Schematic diagram of (a) energy band structure of a HIT solar cell, Egi – optical gap with i as 1,2,3 for the layers, ΔEv, ΔEc are valence and conduction band discontinuities, (b) physical structure of popular HIT cell.

1.2 Historical Development of HIT solar cell efficiency

Towards the beginning of the HIT cell technology, in 1991, 16% solar cell efficiency was reported [1]. In 1992 the reported efficiency of the cell improved to 18% [2]. In 1994, it was 20% [3], that remained around 21% in 2000 [7] and in 2003 [16]. In 2011 it was reported to be 23% [17]. In 2011, it was reported that a 23% efficiency can be obtained from a cell with 743mV open circuit voltage [17]. Here it seems a thinner absorber layer (98 μm) gave such an improved result. With the p-type c-Si absorber, the results are not as good as the above (n-type absorber). In 1997 it was reported to be 10.6% [4].

2. Experimental Systems

In the following we describe some of the important experimental steps used in HIT solar cell, during its fabrication and characterization.

2.1 Wet chemical processing of c-Si wafers

The surface damages of the wafers are removed by isotropic etching of the wafer surfaces with the help of 8% NaOH solution in de-ionized-water (Di-W), at 80oC temperature for about 7 minutes. It may etch out about 5 micrometer thickness from wafer surface in this way. After that the wafers are rinsed in 10% HCl for 1 min, rinsed in Di-W for 1 min. Then the wafers are rinsed in 10%HF solution in 1 min, Di-W for 1 min. In order to obtain textured surface, anisotropic etching to be performed. Then RCA (or Radio Corporation of America) cleaning prepares the wafer for surface passivation. The RCA cleaning has generally two steps, standard cleaning 1 (SC-1) and SC-2. The SC-1 is used for removal of organic contaminants, by dipping the wafer in a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O) at a ratio of 1:1:5 at a temperature of 75 to 80oC for 10 minutes. Then the wafers are transferred to Di-W bath and rinsed for 1 minute at room temperature. In order to remove the possible oxide layer the wafers are dipped into dilute hydrofluoric acid (HF) solution (HF:H2O = 1:50) for a short time (1-2 minutes). Buffered HF (BHF) can also be used for this purpose. Part of the metallic contaminants that may exist even after the previous steps can be removed by the SC-2 cleaning. This is performed in a hydrochloric acid (HCl) solution with HCl : H2O2 : H2O =1:1:6 at 75 to 80oC temperature. Possible oxide layer at the top surface of the wafer is cleaned by BHF (which is a mixture of 6 volume of 40%NH4F in water, and 1 volume of 49%HF in water) [4]). The cleaned wafers are then quickly transferred to load-lock of an ultra-clean high vacuum deposition system. The front and back side of the wafers are covered with a few nm thick a-Si:H film for passivation of the surface defects. Then highly doped p-type a-Si:H films (~7nm) is deposited at the front surface that acts as emitted layer and n-type a-Si:H layer is deposited at the back, that acts as BSF, with a thin intrinsic a-Si:H buffer layer between the c-Si and n-type a-Si:H. Then metal electrodes can be formed by thermal evaporation or by screen printing [10].


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2.2 Deposition Methods or fabrication steps

Most of the HIT cell fabrications were performed by using plasma enhanced chemical vapor deposition (PECVD) technique for the amorphous silicon layer deposition, however sputtering was also used for this [4]. Hotwire CVD method of depositing amorphous silicon layers can greatly reduce ion bombardment related damage to the c-Si surface [6, 18,]. The HIT cell fabrication steps can be schematically summarized as in the following fig 3. Investigation showed that surface passivation with the amorphous silicon layers did not deteriorate the c-Si substrates [3], although there is a chance of ion bombardment in rasio frequency (RF) PECVD.

Fig. 3. Schematic representation of the process steps in fabricating HIT solar cell.

In RF PECVD system a 13.56 MHz electrical power creates the plasma while for the very high frequency (VHF) PECVD the frequency can range anywhere between 20 MHz to 100 MHz. In a hot wire (HW) CVD it is the thermal energy of a heater wire filament that provides the dissociation energy [19]. Usually phosphine (PH3) or diborane (B2H6) gases are used for n-type or p-type dopant gas respectively. In the plasma, a high velocity electron (around 70 eV thermal energy) collides with SiH4 to create nearly 58% neutral radicals and 42% charged ions. The electrically neutral derivative radical of silane can be written as → , , . Out of these the SiH3 radical helps to deposit high quality a-Si:H alloy films. The SiH2 and SiH radicals being highly reactive to hydrogen, a suitable hydrogen dilution helps in achieving optimum deposition condition. VHF deposition system generally gives better quality amorphous silicon layers, because of enhanced dissociation of gas molecules and lower rate of ion bombardment. It may also help to deposit amorphous, microcrystalline and epitaxial layers relatively easily, that gives a wide range of material structure. In HW-CVD there is a reduced ion bombardment to the c-Si surface, as compared to the RF PECVD system. It was reported that at a lower deposition temperature, the HIT cell performs better [20].

3. Effects on HIT cell performance

It is known that hydrogenated amorphous silicon material faces light induced degradation (LID). So the HIT solar cell may also face the LID. However, so far such a degradation has not been observed, or negligible [1,2]. The main reason may be because of the use of very thin amorphous silicon layer and the other can be the high electric field.

3.1 Doped amorphous silicon layer

Microcrystalline silicon is known to have wider optical gap and higher electrical conductivity in comparison to its amorphous silicon counter part. Also it is known that p-type amorphous silicon has lower optical gap in comparison to intrinsic amorphous silicon, because of the presence of the boron as p-type dopant. So using a microcrystalline p-type layer, the HIT cell may perform better. However, microcrystallinity of a film is thickness dependant, so a relatively higher thickness (30nm) was used as emitter layer [14]. The HIT cell shows the Jsc of 29mA/cm2 [14]. In comparison to a cell with p-a-Si:H layer, without intrinsic a-Si:H buffer layer, the Jsc is similar but observed Voc for the cell with the microcrystalline p-layer was lower (0.3V) and FF was 0.4 [40], whereas, for the other cell the Voc was 0.57 V, FF more than 0.7 [1,2]. Without the intrinsic buffer layer, nearly 20% efficiency of HIT solar cell was also reported by Fuhs et al. in 2006 [21]. Various doping density of the p-type a-SiC:H emitter layer was also reported [5,6]. Highly doped p-layer gives normal I-V curve, whereas low or undoped p-layer give S shaped I-V. At a lower temperature the situation is even worse. It is thought that width of the depletion layer was about 5 nm in p-a-SiC:H side while it is 400nm in the n-c-Si side for highly doped p-layer. In case of low doping of the emitter, the depletion region exists only in the a-SiC:H region, by fully extending over this layer whereas in the c-Si layer it is negligible, that could be the reason of the S shape of the I-V curve. Some numerical simulation was used to investigate the conduction band offset of p-type emitter and n-type c-Si absorber [22]. It showed that with lower conduction band offset the S-shape of the I-V characteristic curve becomes more prominent. P-type a-SiC:H emitter was tested for various C incorporation and H dilution [23] and it was found that the presence of high C in the emitter layer degrades the cell characteristics that can be recovered by higher H dilution during its deposition. Cleef et al. investigated p-type a-SiC:H materials for the HIT structure that resulted in high FF [5,6].


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3.2 Intrinsic amorphous silicon layer

High p-layer and i-layer thickness leads to lower Jsc, may be because of optical absorption loss of light in these layers. While at a constant total amorphous layer thickness, if the i-type layer is inserted it gives better result [1,2]. It was found that insertion of the a-Si:H buffer layer between c-Si wafer and hydrogenated Si layer results in better surface passivation [6,7, 24-27] . The intrinsic a-Si:H film is mainly used for surface passivation in HIT cell structure. A poor HIT cell can be formed if defective intrinsic a-Si:H film is used [4]. A theoretical investigation showed that the defects at the i-a-Si/c-Si interface affects the cell performance [28]. It indicates that the valence band discontinuity in the interface between the p-type emitter and n-type c-Si leads to a significant loss in photo generated carriers. It has been found that, an optimized H dilution is necessary for optimized surface passivation, a H2/SiH4 flow rate ratio range between 2 to 4 is a good choice [29]. Below this limit the a-Si:H films may acquire more defects due to insufficient defect passivation of Si dangling bonds during its growth, and beyond this value the material may show epitaxial growth, which is again undesirable for the cell. Although microcrystalline or epitaxial layers have higher conductivity yet HIT solar cell containing such films may exhibit lower performance [30,31]. It was reported that with the epitaxial buffer layer, the observed Voc was lower than that without it, and a systematic investigation with different epitaxial i-layer thickness indicates that epitaxial layer is deteriorative for the surface passivation of c-Si [31]. It was found that an abrupt c-Si/a-Si interface indicates a better surface passivation, where the abruptness is reduced for epitaxial i-layer [32-34 ]. A further thermal annealing shows improvement in surface passivation if the buffer layer is amorphous as compared to the epitaxial layer. AZO layer was tested at a back surface of p-type c-Si wafer with p-a-Si:H back layer [35].

3.3 P-type c-Si absorber

About 525 μm thick p-type c-Si wafer was used to investigate HIT cell characteristics [6]. The p-type c-Si absorber usually gives relatively lower Voc (677 mV) and efficiency (15.2%) [10]. The n-type micro-crystalline silicon was tested with non-textured p-type c-Si absorber although it shows a relatively lower efficiency [19, 24, 36-41].

3.4 polycrystalline Si

p-type polycrystalline Si of thickness 200 μm was used for cell fabrication [6] however, the device characteristics remained lower than that observed with the c-Si.

3.5 N-type Silicon wafer

Most of the high efficiency HIT solar cells have been fabricated with n-type c-Si absorber [1,2]. Although p-type c-Si wafer can, in principle, be used in combination with n-type amorphous silicon emitter layer, yet there are some limitations in achieving high Voc [6]. Analysis shows a high recombination mechanism could be a dominant factor.

3.6 Effect of interface defects

It was suggested that a high (10-6 A/cm2) reverse saturation current observed at the c-Si/a-Si hetero interface in comparison to c-Si/c-Si homo junction, may be because of high interface defect density [1,2]. The same investigation showed that with texturization of the c-Si wafer, the Voc decreases, indicating a further increase in defect density. The HIT cells show lower Voc, FF efficiency if p-type emitter is directly deposited on the n-type absorber. This may be because a significant defect exists within the depletion region and recombination in the depletion region becomes primary factor for the lower performance of the device [7]. It is understood that high density of mid gap defect states near a hetero-interface leads to increased tunneling and leakage current. So, in order to keep the defect states away from the interface a thin intrinsic layer becomes useful [42]. However, later it was suggested that the recombination in the heterojunction interface is not very important, rather it is the recombination in the space charge region that is significant irrespective of the quality of the crystalline silicon absorber [6]. Surface passivation by doped layers can be effective because of field induced surface passivation mechanism, whereas the intrinsic amorphous silicon layer act to passivate the surface dangling bonds by forming Si-Si or Si-H bonds. Net recombination of electrons and holes due to the surface defects can be expressed similar to the Schockley Read Hall bulk recombination, as U = ( ) (2)

here n(p) are electron (hole) density, ni is intrinsic carrier density, Nst is surface defect density, νth is average thermal speed of minority carriers (charge particles), σs is electron or hole capture cross section for surface defects, Ei is Fermi energy of intrinsic material Est is energy level of surface traps, k is Boltzmann constant, T temperature. Under low level


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carrier injection (Δn) by incident light n=n0 +Δn and p= p0 +Δn, where n0, p0 are electron and hole equilibrium carrier densities, the effective carrier lifetime can be expressed as, τeff = Δn/U

3.7 Characterization of passivated surfaces

Carrier lifetime and surface recombination velocity can be measured by quasi steady state photo conductivity (QSSPC) decay in which a light pulse, generated in a flash lamp, illuminates the sample surface for a relatively short period of time so that quasi steady state is achieved. From this decay curve, the carrier lifetime and the surface recombination velocity can be estimated. Lower surface recombination velocity implies higher carrier lifetime and a better defect passivation. In order to measure carrier lifetime, temporal decay of surface photo voltage with a characteristic decay time τeff can

be used. Effective carrier lifetime from bulk and surface recombination can be expressed as = + , where τb, (τs)

are carrier lifetime due to bulk (surface) defects. Thus τeff is always smaller than the smallest of the lifetimes (τs or τb) of the recombination channels that constitute the electron-hole recombination. For symmetric wafers, where both sides of

the wafer was passivated equally, the surface lifetime can be expressed as, = + , where S is surface

recombination velocity, D is minority carrier diffusion length, W is thickness of the wafer. If average excess carriers generated by a pulse of light, is Δnav , in an open circuit condition, then the generated

photo-current (jph) can be expressed as, = . Implied-Voc is the estimated open circuit voltage from the

measure of average carrier concentration at the edge of depletion region. For low level injection it can be expressed as, = . Here ni is the intrinsic carrier concentration, which is 8.6×109 cm-3 at room

temperature (25oC). ND is the doping density of the c-Si absorber. The surface photovoltage (SPV) is a contactless measuring technique in which surface potential of a semiconductor junction is measured after a suitable light illumination. It is used to determine minority carrier diffusion length in a semiconductor. In a p/n junction a depletion region is created due to diffusion of excess carriers to other side of the junction, unless the diffusion is prevented by the electric field at the interface. This bends the semiconductor energy bands. When an incident light creates electron-hole pairs, these excess charge carriers diffuse towards the surface. They recombine with the majority carriers at the surface and hence its potential changes. The longer the minority carrier diffusion length the larger is the change in surface potential. The diffusion length L can be expressed as = , where D is diffusion coefficient. Figure 4 shows trend in interface trap densities (Dit) after wafer texturization and wet chemical polishing. With surface texturing, the interface trap density increases, as demonstrated by the trace at the tip of right hand arrow, in Fig 4. It can partly be reduced by smoothing the surface for example, by wet chemical etching, the outer trace of Fig 4. Thus, although front surface texture can improve light trapping, yet the additional electronic defect that gets incorporated becomes a concern.

Fig. 4. A schematic demonstration of variation of the interface trap density due to surface texturing and polishing.


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3.8 Transport mechanism

Solar cell LIV characteristics show there are three transport mechanisms, observed in three ranges of externally applied forward bias, one is 0 to 0.4 V range, the other is 0.4 to 0.6V range and the last one is above 0.6V [4], although the voltage ranges may vary depending on specifications and cell structure. Some investigations were carried out to analyze the role of carrier tunneling for higher efficiency of the cells [13]. It showed that with the n-type c-Si absorber, the tunneling is a necessary conduction mechanism in order to achieve cell efficiency higher than 20%, whereas for a p-type absorber the tunneling is necessary at the back contact of the cell [43]. It is suggested that the tunneling current may exist in a region where the diode ideality factor is 2 or where the current increases sharply with small increase in voltage, that is in the low potential region. Multitunneling capture-emission of charge carriers across a-Si:H/p-c-Si under forward bias condition, was studied and reported by Matsuura et al. in 1983 [44], while it was suggested that the carrier transport under reverse biased condition was mostly generation-recombination limited. A similar trend was observed with intrinsic a-Si:H/n-c-Si as well [45] A study on the a-SiC:H/p-c-Si heterostructure indicates that there can be three distinct region of carrier transport [46]. In the low forward bias voltage the transport is mainly dominated by variable range hopping (VRH) conductivity at the Fermi level, where the VRH conductivity was analyzed using the Mott and Davis Model [47] and the density of states at the Fermi level was estimated as 2×1017 cm-3 eV-1. The intermediate voltage range (that may range somewhere between 0.2 V to 0.6 V, and depends on operating temperature) the carrier transport takes place by multistep tunneling capture-emission process. The last regime falls under a further higher forward bias voltage, where the current seems to be limited partly by the a-SiC:H layer and the carrier transport is space charge limited. In the reverse biased condition, a band to band tunneling transport of the charge carriers were suggested.

3.9 Spectroscopic Ellipsometry

Spectroscopic ellipsometry (SE) can be of interesting use in analyzing changes in ITO and silicon hetero structures, like changes due to thermal annealing [48] etc. Phase sensitive detection of the laser beam, used in the SE due to reflection from surfaces of thin semi-transparent amorphous layers, carries wealth of information regarding real and imaginary part of dielectric constant. A suitable analysis can provide non-destructive contact-less analysis of interface states as well. The SE can also be used for real time thickness control of the amorphous silicon layer deposition [34]

SIMS analysis was also performed on the HIT solarcell, [49], although such an analysis is prone to have significant error in analyzing atomic distribution across different layers.

4. Effects on HIT cell parameters

The Voc can be simply expressed as ≈ . So, leakage current in the cell leads to reduced Voc [6]. Voc does

not depend on thickness of the p-type emitter [1,2] when the thickness is 5nm to 27 nm, however higher p-layer thickness leads to lower blue response of the QE and Jsc. For this reason thinner p-layer is preferable. It also reported a lower Voc for surface texturing the c-Si wafer. A high Voc can be obtained when a-Si/c-Si surface passivation is improved, [50]. Better surface passivation is one of the major factor to improve the Voc. For p-type c-Si absorber, the effect of recombination on the Voc was also reported [6] Jsc increases with reduced thickness of the top amorphous silicon layers emitter [1,2], Fig. 5(a). It can also increase with increased light trapping, BSF structure, better surface passivation etc.

(a) (b) Fig. 5. (a) Typical trend in change in decrease in current density with increase in amorphous emitter layer thickness. (b) Typical increase in blue response of the EQE with reduced emitter layer thickness. The red response can be enhanced by employing light trapping.


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Blue response of the EQE increases for thinner emitter and intrinsic layer emitter [1,2], Fig 5(b). With variation in top layer thickness the EQE changes, mostly because of the optical absorption of short wavelength light within short distance from the top surface of the cell. Thinner emitter-buffer layer gives better blue response of the EQE. Fig 5(b) shows a typical variation of the blue response of the EQE spectra with thinner amorphous layers at the front. The FF depend on several factors, few of which are, SRH recombionation, series & shunt resistance, built-in potential etc. Efficiency (η) of a cell is the product of FF, Jsc, Voc and can be expressed as, η = FF.Voc. Jsc. It is an overall indicator of the maximum electrical power the cell can generate under a certain condition.

5. Conclusions

The n-type c-Si absorber, in combination with p+ - type a-Si:H emitter and n+-type BSF, can lead to a very high efficiency HIT solar cell. The HIT solar cell is processed at a relatively lower temperature, with a shorter processing time, in comparison to the c-Si solar cells. A further improvement in defect passivation and understanding of the device operation may lead to further improvement of the device performance. This type of solar cell has already occupied a significant fraction of solar cell market, and is expected to grow in future.

Acknowledgements This work was supported by the Human Resources Development program (No. 20124010203280) of the Korea Institute of Energy Technology Evaluation and Planning (KETEP) grant funded by the Korea government Ministry of Trade, Industry and Energy.

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