Summer04 epitaxial depostion heterojunction

New Ideas for New Materials

Summer 2004 Yield Management Solutions64

S U B S T R A T E S

IntroductionThe implementation of Si1-xGex layers inactive device structures is nowadays recog-nized as an efficient way to improve devicecharacteristics. Currently, chip manufacturersfocus mainly on the integration of Si1-xGex

in heterojunction bipolar transistors (HBT)in Bi complementary metal oxide semicon-ductor (BiCMOS) technology1-15. In thenext phase, attention will go to the fabrica-tion of Si/Si1-xGex heterojunction CMOSdevices to improve the performance of thep-type MOS device16-24, and to elevated Si1-xGex source/drain contacts to reduce shortchannel effects in CMOS technology 25-29.For the first two applications, both selective

A successful selectiveepitaxial Si1-xGex deposition process forHBT-BiCMOS and high-mobilityheterojunction pMOS applications

R. Loo, M. Caymax, I. Peytier, S. Decoutere, N. Collaert, IMEC P. Verheyen, W. Vandervorst, and K. De Meyer, K.U. Leuven, ESAT-INSYS

Si1-xGex/Si heterostructures are useful for a wide variety of device applications where device performance is improved by bandoffsets and/or increased carrier mobility. The use of selective epitaxial growth for the implementation of Si1-xGex has someadvantages compared to a non-selective growth process. However, some issues such as thickness non-uniformity (micro-loadingon a µm scale and gas depletion on wafer scale) and facet formation have to be solved. In this paper, we give a detailedoverview of our selective Si1-xGex growth process in a standard production-oriented chemical vapor deposition system for Gecontents between 0 and 32%. Our process allows layer deposition with no pattern dependence of the growth rate and Gecontent (no micro-loading), and with a wafer scale layer non-uniformity better then the accuracy of the measurement techniques(~2%). Facet formation was avoided by choosing the correct growth conditions, and by preventing lateral growth over themask material. Selective epitaxial layers did not show a degradation of photoluminescence characteristics. The layer qualityis further demonstrated by the performance of Si1-xGex heterojunction bipolar transistors (0.35 µm and 0.25 µm technology),and p-type Si1-xGex heterojunction MOS devices (effective gate length down to 70 nm).

and non-selective epitaxial growth by means of chemicalvapor deposition (CVD) can be used. In the case ofnon-selective epitaxial growth on patterned wafers,deposition occurs simultaneously in the Si windows(epitaxial growth) and on the mask material (polycrys-talline growth)1,6,30. In the case of selective epitaxialgrowth (SEG), deposition on the mask material is pre-vented by adding HCl to the gas mixture in appropri-ate deposition conditions1,29-33. The top layer of themask material can be oxide or nitride. For BiCMOSapplications, SEG has the advantage of replacing theexisting implanted base by a grown, in-situ doped box-like boron profile, which avoids the generation of inter-stitials. In the case of heterojunction MOS devices, theSEG technique allows the deposition of the requiredchannel material for the active region of the pMOS

Summer 2004 www.kla-tencor.com/magazine 65

without negatively affecting the nMOS, which isespecially important for full CMOS integration.Elevated Si1-xGex source/drain contacts evidentlyrequire a selective growth process.

So, the importance of the availability of a Si1-xGex SEGprocess for the industrial market is evident. However,the applications mentioned above require good thicknessand composition control of the epitaxial layers. Despitethe fact that Si1-xGex has successfully been integrated indevice structures, there is still a need to improve thegrowth process. Several groups, who use epitaxial CVDsystems for production applications, reported the influ-ence of the mask layout on layer deposition (micro-loadingon a µm scale and macro loading (gas depletion) effectson wafer scale4,29-34. Pattern dependence of both growthrate and Ge incorporation are reduced by reducing thetotal pressure29,31, and by increasing the HCl flow inthe gas mixture31,32. Increase of the HCl flow is not anoptimal solution for the BiCMOS, because the link-upof the intrinsic epitaxial base with the extrinsic poly-crystalline base becomes troublesome2. Other issues,which have to be solved before SEG processes are usable,are facet growth, void formation and defect generationat the sidewalls of the epitaxial layer.

As we report in this paper, we succeeded in the devel-opment of Si1-xGex SEG processes which do not sufferfrom loading effects. The discussion is focused on Si1-xGex

layers, grown by reduced pressure (RP) CVD, with Gecontents up to 32%. These high Ge contents are neededfor the fabrication of Si/Si1-xGex heterojunction CMOSdevices. A change in the mask layout, or of the waferarchitecture, may lead to a change of the optical waferemissivity. This causes a change of the surface temperatureduring epitaxial growth and, as a result, a change ofthe growth rate and layer composition30. This thermalloading effect has to be taken into account for bothselective and non-selective growth processes at lowtemperatures and reduced pressures where the growthis kinetically controlled. However, non-selective growthprocesses on patterned wafers are the most sensitive forthose thermal loading effects.

After a short description of our growth and characteri-zation procedures we will first motivate our growthtemperature choice. Next, the influence of the growthconditions on loading effects will be discussed. In thesection “Avoiding facet growth”, we describe theobserved correlations between the facet generation onone hand, and the pattern geometry and different growthconditions on the other hand. Finally, the success of our

SEG process is demonstrated by the performance of Si1-xGex HBT (both 0.35 µm and 0.25 µm technology)and p-type Si1-xGex heterojunction MOS devices withan effective gate length down to 70 nm.

Growth and characterization proceduresThe reduced pressure chemical vapor deposition (RP-CVD)system used in this work is a standard ASM Epsilon 2000production epi reactor. This tool is a horizontal, coldwall, single wafer, load-locked reactor with a lamp-heatedgraphite susceptor in a quartz tube. Epitaxial layerswere deposited on blanket or patterned 200 mm (001)Si wafers. Before deposition, the wafers received anIMEC clean35,36. The native oxide was removed by a HFdip, followed by a DI rinse and Marangoni dry37. Thein-situ bake at 850-900ºC removes all traces of O. Theepitaxial layers are defect free with C and O contami-nation levels below the detection limits of secondaryion mass spectroscopy (SIMS)38.

Epitaxial growth was carried out at reduced pressure(between 10 and 80 Torr). A H2 gas flow in the range of30 to 40 standard liters per minute was used as carriergas. Dichlorosilane (SiH2Cl2) and germane (GeH4, 1%diluted in H2) were used as Si and Ge source gases,respectively. Diborane (B2H6, 50 ppm in H2) was usedas boron doping gas. Deposition on the mask materialhas been avoided by adding a carefully chosen amountof HCl to the SiH2Cl2/GeH4 gas mixture during thegrowth. As an example, Figure 1a shows the HCl flowensuring selectivity as function of GeH4-gas flow and fora constant SiH2Cl2-gas flow at a temperature of 750°Cand a pressure of 10 Torr. The resulting Ge incorporationand growth-rates are shown in Figure 1b.

The development of the SEG Si1-xGex process was focusedon 2 applications. The first one is deposition of the baselayer for BiCMOS applications where Ge contents between0 and 15% are required. The second application is theheterojunction pMOS device with Ge contents up to32%. Process tuning was done on patterned wafers withmask layouts as designed for each application. The waferarchitectures are the complicated full BiCMOS and CMOSarchitectures, respectively, including shallow trenchisolation. Their fabrication is described in Reference 2and 3 (BiCMOS) and in Reference 39 (CMOS).

Thickness and thickness uniformity of thicker epitaxiallayers, with a constant Ge concentration, were measuredby means of conventional step profilometry as well asby spectroscopic ellipsometry (SE). SE was also used to

S U B S T R A T E S


extract the Ge content. The technique allows a fast,accurate, inline and non-destructive analysis, includingfast wafer mapping facilities40,41. For the SE measurementswe used a commercial ASET-F5 (advanced spectroscopicellipsometry technology) system from KLA-Tencor,which is a production-oriented, completely automatedsystem. The small spot size (28x14 µm2) permits analysisof epitaxial Si1-xGex layers grown in isolated structureswith dimensions down to 50x50 µm2. Such window sizeprevents measurements by Rutherford backscatteringspectroscopy (RBS). SIMS was used to extract the Geprofile of more complicated layer stacks, as used in HBTand heterojunction-MOS devices. Scanning electronmicroscopy (SEM), Plan-view and cross-sectional trans-mission electron microscopy (TEM) were used to visu-alize the structural properties. Photoluminescence (PL)measurements were used to study the optical materialproperties. PL was carried out with a Fourier transformspectrometer equipped with an N2-cooled Ge detector.The samples were mounted in a continuous-flow Hecryostat and excited by an Ar ion laser with a wave-length of 488 nm.

Choice of the growth temperatureThe HBT base layer consists of an epitaxial layer stackwith a linearly graded Ge profile from 15% (substrate side)down to 0%, followed by a Si cap layer of 20-40 nm.“Standard” Si1-xGex process temperatures are in the600–650°C range. Our growth conditions include aHCl gas flow high enough to maintain selectivity butlow enough to guarantee a good linking between theepitaxial layer with the polycrystalline base (see section“Avoiding facet growth”). The addition of HCl toensure selectivity makes the growth rate decrease.However, because the epsilon is a single wafer reactor,high growth rates are mandatory to ensure sufficient

throughput in a manufacturing environment. So,we increased the deposition temperature to 750°Cfor Si1-xGex and to 750–810°C for Si. Thesetemperatures still are low enough to meet thespecifications for Ge and B depth profiles. SIMSprofiles of a full BiCMOS stack demonstrate theperfect control of Ge incorporation and growthrate are shown in Figure 2. The wafer-to-waferrepeatability of the epitaxial layer thickness, asobtained for the same growth recipe and identicalwafers, is better than 2.0% (Table I, series II).This is less than the thickness variations of thedifferent layers that build the wafer architecture.

Si/Si1-xGex heterojunction pMOS devices requiremuch higher Ge contents (25–32%) and thinner

layers. It is well known that the Ge incorporationincreases with decreasing process temperature. In orderto avoid layer relaxation, we took a growth temperatureof 650°C for the heterojunction pMOS device struc-ture. 650°C allows deposition of smooth, strained, anddefect-free 8 nm thick Si0.68Ge0.32 layers.

Loading effectsDefinition and causes The term “loading effect” refers to variable depositionrates and layer compositions over the wafer, whichare not seen during blanket layer growth, but whichare related to variations in the surface topology. Thesurface topology is composed of fields of Si and of othermaterials (oxide, nitride, and so on), which can bearranged in features with different sizes and density. Thearrangement of these features (form, size and area) iscalled mask layout. The composition of these features,which are typically made up of layers of different mate-rials (thermal oxide, TEOS oxide, nitride, polycrystalline

S U B S T R A T E S

80

60

40

20

0

30

25

20

15

10

5

00 50 100 150 200 250 0 50 100 150 200 250

GeH4-flow [sccm] GeH4-flow [sccm]

HCI

-flo

w [

sccm

]

Grow

th-R

ate

[nm

/min

]

30

25

20

15

10

5

0

Ge content [%]

a) b)

Si substrateSi substrate

Figure 1. a) Required HCl flow to ensure selectivity as function of GeH4 gas flow and

b) Ge incorporation and growth-rate as function of GeH4 gas flow. Growth-temperature:

750°C, pressure: 10 Torr, H2-gas flow: 40 slm, and SiCl2H2 gas flow: 100 sccm.

0 50 100 150 200Depth [nm]

Ge

B

Boro

n co

nc. [

cm-3]

20

15

10

5

0

1x1020

1x1019

1x1018

1x1017

1x1016

Ge content [%]

Figure 2. SIMS profile of an HBT base layer, grown at 750°C and 10 Torr.


Si, and so on) with different thicknesses is called thewafer architecture (Figure 3). Both mask layout andwafer architecture can influence the loading effect aswill be shown (see section “Study of the thermal andchemical loading effect”).

Two different types of loading effects are often definedin literature: micro-loading and macro-loading. Micro-loading takes place at the microscopic level of individualfeatures (islands, windows, and so on). The term refersto a local variation in layer thickness and compositionas function of the structure size and the structure

density29,31-34. Further-more, the growth rate ishigher at the edge ofopen Si windows. Macro-loading, on the otherhand, is a non-uniformityin growth rate and/orcomposition over largerdistances on wafer scale.This is caused by gasdepletion, which occursin a horizontal reactorchamber and is due toconsumption of the Siprecursor while the reac-tion mixture flows overthe wafer. Gas depletionhappens on both blanketand patterned wafers, andit leads to a decreasinggrowth rate along thereactor. Fortunately, theeffect can be compensat-ed in different ways: bytilting the susceptor,

applying temperature gradients, wafer rotation, opti-mizing the symmetry of the gas flow in the reactor or a combination of these42. In this work, we obtainedexcellent thickness uniformity by using wafer rotation(35 rpm) during processing, a careful fine-tuning of thegas flow distribution in the tube and of the tempera-ture profile. (see section “Avoiding microloading”.)

Several groups, using epi systems for large scale pro-duction applications, found a strong correlation betweenthe filling ratio (defined as the fraction of exposed Si areaon the mask) on one hand and the growth rate and Ge

incorporation on the other hand31-33.Depending on the growth conditions(especially the HCl flow), the Si1-xGex

growth rate can both increase anddecrease with increasing filling factor.In the section “Identical wafer archi-tecture and different mask layouts,”we will show that this phenomenonis related to gas depletion too. Wewill discuss the correlation betweentotal gas consumption over the waferand the fraction of exposed Si on thewafer. Because gas depletion happenson both blanket and patternedwafers, we prefer the term gas deple-tion rather than macro-loading.

S U B S T R A T E S

Series run-nr. Layer Stack MaskArchitecture

MaskThickness

(nm)

LayerThickness

(nm)

P[Torr]

I

II

III

IV

1/417/21/417/5

1/387/31/388/51/395/31/395/4

1/476/31/479/21/476/41/479/1

1/971/11/971/3

Fig 2bFig 2a

Fig 2bFig 2bFig 2bFig 2c

Fig 2aFig 2aFig 2bFig 2c

Fig 2cFig 2a

848.1±1.7287.5±1.0

845.9±3.6844.4±1.9846.1±1.7808.9±2.8

187.3±3.0289.2±1.3852.0±2.0834.7±1.2

756.3±1.7288.7±1.2

118.5±3.181.5±3.2

112.3±4.8113.3±3.1114.0±4.298.1±2.8

102.3±2.998.4±2.6143.3±3.0143.9±4.3

103.6±1.394.1±2.9

2020

20202020

10101010

1010

single Si0.92Ge0.08single Si0.92Ge0.08

full HBTfull HBTfull HBTfull HBT

full HBTfull HBTfull HBTfull HBT

full HBTfull HBT

Table I. Epitaxial layer thickness for different mask architectures, as schematically drawn in Figure 1. The epitaxial

layer thickness has been calculated from step height measurements over the Si surface in the open window and the

nitride surface of the mask (see Figure 2) before and after deposition. Within one series, identical growth recipes

were used for all experiments. The growth temperature was 750°C, except for series II, where we used 750°C for

the Si1-xGex layer and 810°C for the Si-cap layer. The agreement in layer thickness within series II, as observed

for samples with the same mask architecture and mask thickness, shows the reproducibility of the SEG process. P is

the growth pressure.

a)

Si3N4 200 nmSi3N4 20 nm

Si3N4 20 nm

Si3N4 200 nm

Si3N4 200 nm

Field SiO2 450 nm

Field SiO2 450 nm

Si substrate

Si substrate

Poly-Si 250 nm

Poly-Si 250 nm

TEOS 20 nm

TEOS 20 nm

TEOS 100 nm

TEOS 100 nm

TEOS 20 nm

TEOS 20 nm

Field SiO2 100 nm

Si substrate

b)

c)

Poly-Si250 nm

Si3N

4Si

3N4


Figure 3. Architecture of BiCMOS integration wafers. a) Simple test structure, b) and c) complete

architecture with small variations in the layout.


Avoiding micro-loading We studied the influence of the process pressure onmicro-loading by measuring the thickness uniformityof the epitaxial layer in isolated windows (Figure 4a). A reduction of the growth pressure leads to a strongimprovement of the thickness uniformity within a sin-gle window. For a growth pressure of 20 Torr or below,the local epitaxial layer thickness variation is reducedto zero (Figures 4b and 4c). This is easy to understand:lower pressures favor gas phase diffusion. This counteracts

There are two different causes for micro-loading,although they can interfere with each other. The firstcause is due to local variations in gas phase concentrationof the precursors for Si, Ge, or the dopants (“chemicalloading”). Chemical loading is due to desorption of Si-and Ge-bearing species from the mask surface. Thesespecies either diffuse away into the gas phase or re-adsorb on neighbouring Si surfaces. In this way, theygive rise to an additional flux of Si species, and thusto locally increased growth rate, depending on localstructure size and the structure density.

The second cause for loading is a temperature effect(“thermal loading”) due to variations in surface temper-ature. Thermal loading has been described by W. DeBoer et al.30,34. During epitaxial growth the wafer islocated on a SiC-coated graphite susceptor, which isheated by the radiation of two banks of tungsten-halogenlamps. The wafer is heated by the susceptor (thermalconduction) and by direct radiation from the upperlamps30. The process temperature is well controlled bythermocouples placed in the susceptor. However, lightabsorption and emission at the wafer surface are definedby the mask layout and the wafer architecture. A changein mask layout or wafer architecture leads to a change ofthe optical wafer properties and therefore to a changeof the surface temperature during epitaxial growth, inspite of careful temperature control. The consequenceis a change of the growth rate and layer composition asfunction of the wafer architecture and mask layout,because the growth rate is an exponential function of thegrowth temperature. This is the thermal loading effect.

Both causes for loading effects can be important, asdeposition rate is dependent on gas phase concentrationas well as on temperature43. Furthermore, the chemicaland thermal loading effects can interfere with eachother. Thermal loading, for example, leads to a modifi-cation of the growth temperature. This results in modi-fications of the reaction kinetics. These modifications ofthe reaction kinetics are different for each precursor inthe gas phase, because their activation energies are dif-ferent44. So, the thermal loading effect leads to precur-sor dependent variations in gas phase concentrationover the isolating surface, and therefore to a chemicalloading effect. In this view, it has to be taken intoaccount that during Si/Ge co-deposition the Si deposi-tion is enhanced by the deposition of Ge. The increaseof the Si deposition rate is expected, because the Ge-Hand Ge-Cl binding energies are lower compared to theSi-H and Si-Cl binding energies. Furthermore, an auto-catalytic growth effect occurs during the kineticallylimited Si1-xGex deposition44.

S U B S T R A T E S

d

b)

c)

epi layer

250 nm

nitridepoly Si

oxide

Si substrate

Pressure [Torr]

15

10

5

0

15

10

5

00 20 40 60 80 100

Stan

dard

dev

iati

on [

%]

thic

knes

s

d-D/aver [%]

a)D

Si substrateSi substrateSi substrate

d

Figure 4. a) Schematic view of the thickness non-uniformity within a

single window in case of micro-loading, b) SEM view graph of a full

HBT base layer. The perfect thickness uniformity shows the absence of

a micro-loading effect. c) Thickness non-uniformity in a single window

(right scale) and on the full wafer (left scale) as function of growth

pressure and for a deposition temperature of 750°C, as obtained

from step height measurements.

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the local increase in precursor concentration due to des-orption from the mask areas. Local layer thickness andcomposition variations as function of the structure sizeand the structure density are not observed for a growthpressure of 20 Torr or below. The reduction of thegrowth pressure also improves the layer uniformity onwafer scale (Figure 4c), because the concentration gra-dient along the reactor induced by gas depletion iscounteracted by the higher gas phase diffusion.

The uniformity on wafer scale has been further improvedby careful fine-tuning of the gas injectors and the temperature profile, as measured by the thermocouples.This results in excellent wafer uniformity in both thick-ness and Ge content over 200 mm patterned wafers asshown in Figure 5 for single Si1-xGex layers (Figures 5aand b) as well as for the more complicated full HBTstacks (Figure 5c). The wafer scale uniformity in layerthickness and in Ge content (the variation in Ge con-tent is less then 0.5 atomic percent Ge) is important,because non-uniformities are directly reflected in theelectrical device parameters4. W. De Boer et al. proposed

to improve the wafer scale uniformity issue by using asacrificial polycrystalline Si layer on top of the maskmaterial33. Apparently, this is not necessary. The thick-ness uniformities have been obtained on evenly pat-terned wafers, with mask layouts as defined by theBiCMOS and CMOS layout rules. It has to beremarked, however, that we use higher H2-gas flows (at least 30 slm) than commonly reported. The highercarrier gas flow increases the gas velocity in the reactortube, which further reduces the variation in gas con-centration for the different species.

Study of the thermal and chemical loading effectIdentical mask layout: thermal loading by variationsin wafer architecture. We tried to separate the influenceof the thermal and chemical parts of the loading effect.The influence of the wafer architecture on thermal loadinghas been studied by processing both single Si1-xGex layersand full HBT stacks on wafers with identical mask layout (i.e., same patterning and same filling ratios),but with different architectures (Figure 3). The firstarchitecture consists of a simple 100 nm oxide/200 nmnitride-cap stack (Figure 3a). The second architecturewas the complicated full BiCMOS architecture. Smallvariations in the architecture (Figures 3b and c) wereused to study the importance of the optical wafer prop-erties on thermal loading.

We observed a clear influence of the wafer architectureon the growth rate (Table I). On the other hand, thewafer-to-wafer repeatability in the epitaxial layer thick-ness, as obtained for the same growth recipe and iden-tical wafers-is better than 2.0% (first three runs of seriesII). The differences in layer thickness for identicalgrowth recipes processed on different wafer architecturesdemonstrate the presence of the thermal loading effect.The variation in growth rate can be explained by a vari-ation in surface temperature, caused by varying waferemissivity. Even for the simplest architecture, a changein thickness of the mask stack (± 100 nm), leads to ameasurable thickness variation of the epitaxial layer(#1/476/3 and #1/479/2). It is striking, however, thatwe did not observe a measurable correlation betweenthe measured Ge content and the wafer architecture.

Identical wafer architecture: limited thermal loadingfor different mask layouts. According to W. B. DeBoer et al., thermal loading does not only depend onwafer architecture but also on mask layout30,34. In orderto study the influence of the mask layout on thermalloading, we did two other series of experiments. Forthis purpose, we used wafers with different mask

Si substrateSi substrate90

88

86

84

82

80

78

48

46

44

42

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38

8.1

4.1

0.0

-4.1

-8.1

-12.2

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-2.5

-4.9

-7.4

3.6

1.8

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-1.8

-3.6

-5.4

108

106

104

102

100

98

Laye

r th

ickn

ess

[nm

]La

yer

thic

knes

s [n

m]

Deviation from average

thickness [%]


thickness [%]


thickness [%]

Laye

r th

ickn

ess

[nm

]

Position over the wafer [mm]

a)

b)

c)


Standard dev.: 1.4 nm (1.7%)




-100 -75 -50 -25 0 25 50 75 100

-100 -75 -50 -25 0 25 50 75 100

-100 -75 -50 -25 0 25 50 75 100

Figure 5. Layer thickness and deviation from the average value as mea-

sured on patterned 200 mm wafers. The window size is 200x200 µm2.

a) Si0.85Ge0.15 grown at 750°C and 10 Torr, b) Si0.72Ge028 grown

at 650°C and 20 Torr, and c) full Si/Si1-xGex base layer as used for

BiCMOS applications, grown at 750°C and 10 Torr.

S U B S T R A T E S

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geometries but with identical wafer architectures as drawnin Figure 3a (simple oxide/ nitride stack). Different masklevels of our HBT process flow were used for wafer patterning of these specific test wafers. In this way, thefilling ratio was varied between 0.2% and 7.35%.

In the first experiments patterned and blanket wafersreceived a BF2 implantation (dose: 5x1013 cm-2, energy:20 keV), which gives a gaussian doping profile with aboron peak 190 Å below the Si surface. Next, the waferswere annealed in the Epsilon 2000 system for 60 minutesVariations in light absorption and wafer emissivity willinfluence surface temperature and cause differences inthe boron profile, which are measured by high resolutionSIMS. Indeed, 60 minute anneals at 780°C and 800°Clead to differences in full width at half maximum(FWHM) of the boron profile, which are 250 Å and285 Å, respectively. However, the variations in surfacetemperature as function of mask layout and for blanketversus patterned wafers are much lower. After 60 minuteanneal at 800°C, no measurable differences in FWHMcan be seen by high-resolution SIMS on the differentwafers, indicating negligible temperature differences (orthermal loading effects) for this series of filling ratios.

The second series of experiments consists of the deposi-tion of a thin non-selective continuous Si film all overthe wafer surface, by using SiH4 as Si source gas. Next,a Si1-xGex layer with x ~ 0.14 was grown under selectiveconditions and at a growth temperature of 750°C. Thefilm grows epitaxially in the Si windows and, because ofthe presence of the Si nucleation layer, polycrystallineon the nitride. The growth rates for epitaxial and poly-crystalline deposition are similar for the given growthconditions, as confirmed by a combination of SE andstepheight measurements. In this way, we could mini-mize possible chemical loading effects. A possiblevariation in the optical wafer properties during growthdue to the growing polycrystalline layer is neglected.If it would appear, it would be similar for all wafers.

Figure 6 shows the correlation between the growth rateand the filling ratio of the mask, in case of epitaxialgrowth in the open Si windows and polycrystalline growthon the mask area. For higher filling ratios, we observeda slight increase in growth rate: from 16.3 nm/min fora filling ratio of 0.2% to 17.3 nm/min for a filling ratioof 7.35%. This corresponds to a temperature differenceof approximately 2°C, as estimated from a temperaturedependence study of the growth rate for the givengrowth conditions.

A comparison of those two results with the results ofthe previous section of this article shows that variationsof the wafer architecture (layer thickness, material)have a much more pronounced influence on the surfacetemperature than variations of the mask layout.

Identical wafer architecture and different mask layouts:Influence of gas depletion on growth rate. We studiedthe influence of the mask layout on the selective epitaxialgrowth kinetics for a deposition temperature of 750ºCand pressures of 20 Torr and 10 Torr. Again, wafers withidentical wafer architectures (simple oxide/nitride stack,see Figure 3a) but with different mask geometries wereused. It was our purpose to study the influence of thefilling ratios on the growth rate and Ge incorporationwhile maintaining patterning and pattern density overthe wafers. As shown, variations in mask layout haveonly a limited influence on thermal loading. Earlier, weexplained that for a pressure of 20 Torr or below, we donot suffer from local micro-loading (pattern dependencyon the growth conditions on the wafer), nor from waferscale non-uniformities in thickness or Ge content. So,with this experiment gas depletion effects can be studied.

For selective growth at 20 and 10 Torr, strong differencesbetween the correlation of the mask layout and thegrowth characteristics are observed (Figure 7). At 20 Torr,both growth rate and Ge incorporation show a strongdecrease if the total open Si area on a wafer is increased(Figure 7a). The trend is similar to the results publishedin References 31-33. The growth rate behavior is opposite

Si substrateSi substrate18.0

17.0

16.0

15.00 2 4 6 8

Total Si area [%]

Grow

th r

ate

[nm

/min

]Figure 6. Epitaxial growth rate as function of total open Si area in case

of polycrystalline growth on the mask material and epitaxial growth in

the windows (10 Torr, 750°C, H2 gas flow = 40 slm, SiCl2H2 gas

flow = 100 sccm, GeH4 gas flow = 200 sccm, HCl gas flow = 67.6 sccm).

S U B S T R A T E S

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to the behavior as expected from thermal loading(Figure 6). Furthermore, a temperature decrease(increase) would lead to a decreased (increased) growthrate together with an increased (decreased) Ge incorpo-ration. Because we do not suffer from micro-loadingeffects, we explain the obtained correlation between thefilling ratio on one hand and the growth rate and Geincorporation on the other hand by gas depletion. Gasconsumption of each component over the wafer isreduced for patterned wafers, and it scales with the filling ratio. This explains the increased growth rate forreduced filling ratio. A change in gas consumptionleads to higher partial pressures of all components.Because the incorporation of one component is influencedby all other components, a correlation between the Gecontent and the filling ratio might be expected. Thelocal thickness uniformity is not affected by the fillingfactor, and wafer scale uniformity can be maintainedby a slight modification of the temperature profile.

At 10 Torr, the influence of the filling ratio on growthrate and Ge incorporation is much less pronounced.An increase of the filling ratio from 0.2% to 7.35%leads to a small enhancement in growth rate. The Geincorporation goes down with increasing filling ratio.Apparently, the gas depletion effect is strongly reduced.As mentioned earlier, the concentration gradient inducedby gas depletion is counteracted by the higher gas phasediffusion for lower growth pressures. Further-more, gasvelocity is enhanced at reduced pressure and unchangedgas flows. In fact the growth rate enhancement (3.8%)is close to the value due to thermal loading (6%). Thesmall reduction in Ge incorporation (Figure 7b) can alsobe explained by a temperature enhancement. At 10 Torr,

the growth rate is strongly reduced onblanket layers (Figure 7b). In this case a strong temperature effect cannot beexcluded due to the absence of theoxide/nitride stack and also gas depletionmay become important again.

The influence of the filling ratio on thegrowth dependence is different for epi-taxial layers with a higher Ge content,which are grown at lower temperatures.At 650ºC the growth rate for selectivegrowth at 10 Torr (~25% Ge) and 20Torr (~32% Ge) is slightly higher onblanket wafers compared to patternedSTI wafers. This behavior is opposite tothe one observed at 750ºC. We did notyet study the loading effect in more

detail for these growth conditions, but it is evidentthat at 650ºC mass-transport in the gas phase is of lessimportance, because of the reduced absolute tempera-ture. As a result gas depletion will also be of lessimportance.

Solving the problems of micro-loading and gas depletionThe presence of thermal loading effects makes it neces-sary to do the fine-tuning of the SEG process on waferswith the same wafer architecture as used for the finaldevice structures. On the other hand, the influence of themask layout on growth conditions is limited and also ofless importance for device applications. This is becausethe mask layout is fixed for each specific application anddefined by the corresponding layout rules (contactingscheme, etc.). For a growth pressure of 20 Torr or below,the local epitaxial layer thickness variation (micro-loading)is reduced to zero as shown in Figures 4b and 4c. Thewafer scale uniformity can be improved by a carefulfine-tuning of the gas injectors and the temperatureprofile (Figure 5). For a growth pressure of 10 Torr, gasdepletion is not considered an issue.

Avoiding facet growthOnce the conditions for selective epitaxial growth aretuned, to prevent nucleation on the mask material andto obtain the required layer uniformities (in thicknessand in composition), the issue of layer morphologybecomes important. A well-known problem is facetgeneration29,45,46. Facets are slower growing planes,which cause a thinning of the epitaxial layer near thepattern edge area. In general, facets are undesirable for technological applications, because they result in


Grow

th R

ate

[nm

/min

]

Ge content [%]

15.0

10.0

5.0

0.0

Area Si [%]

a) 20 Torr15.0

10.0

5.0

0.00 25 50 75 100


Grow

th R

ate

[nm

/min

] Ge content [%]

35.0

30.0

25.0

20.0

Area Si [%]

b) 10 Torr15.0

10.0

5.0

0.00 25 50 75 100

Ge contentGrowth Rate

Figure 7. Growth rate and Ge incorporation as function of the total open Si area, as obtained

for selective Si1-xGex growth at 750 °C. a) 20 Torr (H2 gas flow = 30 slm, SiCl2H2 gas

flow = 100 sccm, GeH4 gas flow = 20 sccm, HCl gas flow = 49.5 sccm) and b) 10 Torr

(H2 gas flow = 40 slm, SiCl2H2 gas flow = 100 sccm, GeH4 gas flow = 200 sccm, HCl

gas flow = 67.6 sccm).

S U B S T R A T E S


insuperable issues during further device processing.Despite the fact that facet growth has been studied forquite some years, facet formation is still an importantissue for the complicated layer stacks (which are part ofthe devices) discussed in this paper.

We studied the facet formation on simple test waferswith oxide or nitride patterning and with sidewalls ori-ented along the <110> direction. Facet formation isrelated to both the pattern geometry and to the growthconditions. We observed two different types of facets.{111} facets are correlated with a lateral growth overthe mask material. This explains their existence in caseof epitaxial growth in windows with a sloping sidewallgeometry (Figure 8a). For sharp vertical sidewalls, no{111} facets appear as long as lateral growth over themask material is prevented (Figure 8b). In the case oflateral overgrowth, defects are observed at the Si/maskinterface, together with the {111} facets. {311} facetsare correlated to the epitaxial growth conditions, espe-cially the growth temperature, as long as the verticalsidewalls of the mask are sharp (Figure 8b and Figure 9).In this case, {311} facets are only seen for high deposi-tion temperatures (Figure 8b). They do not appear atlower temperatures, which allows facet-free epitaxialgrowth (Figure 9). The critical temperature for facet-freelayer growth (~825ºC in case of Si), depends only to asmall extent on the mask material.

The growth conditions as used for the full HBT baselayer allow a facet-free growth of the full layer stack(Figure 4b). Growth appears simultaneously on theopen Si surface and on the polycrystalline base contact.Facet formation is avoided by defining a negative slopein the lateral undercut of the TEOS layer, which avoidslateral growth over the TEOS sidewall. The use of anoptimized HCl flow permits a perfect linking to thebase contact2. No voids are seen between the base polycrystalline base contact and the monocrystallineSi/Si1-xGex base layer.

The situation is somewhat different for wafers withshallow trench isolation (STI), as used for Si/Si1-xGex

pMOS devices. Figure 10a shows a SEM cross-sectionmicrograph of a standard STI wafer. Epitaxial growthhappens on all open Si surfaces. It is clear that lateralgrowth over the SiO2 cannot be avoided for thissurface geometry. Furthermore, the Si surface has acorner at the edge. It is not a planar (001) surface.Epitaxial growth happens on all Si surfaces, whichcreates further distortions from the ideal planarsurface, with a multi-faceted epitaxial layer as a result(Figure 11a). Furthermore, defects are detected in thefaceted area, laterally grown over the oxide. To avoidlateral growth over the mask layer, we need a high-quality smooth Si surface with a well-defined and sharpvertical oxide or nitride sidewall at the edge of theopen window. On standard STI wafers, we can reachthis by uniform etch of the Si layer. A conventional dryetch is not an option, because this degrades the surfacequality. Figure 10b shows a STI wafer after an in-situetch back of the Si surface executed in the ASMEpsilon 2000 tool. Vapor HCl diluted in the H2 carriergas was used to etch the Si at a temperature of 850ºC.Again, good wafer-scale uniformity can be reached by a

Figure 8. Correlation between the mask geometry and facet formation.

a) A sloping mask geometry leads to lateral overgrowth over the mask

material. As a consequence, {111} facets are generated. b) The gener-

ation of {111} facets is avoided by the preparation of mask windows

with sharp sidewalls. (The deposition temperature of the Si layer was

850°C, the growth pressure 40 Torr.)

Figure 9. Cross-sectional SEM view graph, showing a facet-free epi-

taxial Si layer, grown at 700°C and 20 Torr.

S U B S T R A T E S


careful fine-tuning of the temperature profile. The mea-sured non-uniformity of the etch rate over the wafer iswithin the accuracy of the step height measurement.The etch rate is high enough for production applications(~15 nm/min) and permits nanometer control of theremoved Si. The etch uniformity within single windowsis also excellent. Therefore, lateral overgrowth can beavoided by using the developed in-situ vapor etchbefore the epitaxial growth. This allows deposition offacet-free and defect-free epitaxial layers, as shown inFigure 11b for the full Si/Si0.68Ge0.32/Si layer stack usedin heterojunction-MOS devices.

Successful SEG Si1-xGex

process implementation The integration of Si1-xGex SEG processes in productionlines requires the fabrication of high-quality material.TEM images of all epitaxial layers show a high degree ofperfection, characterized by smooth surfaces and planarinterfaces between the sublayers. Defects or dislocationswere not detected within the resolution limit of themeasurement. Another very sensitive technique to study

Figure 11. Influence

of mask geometry

on facet formation.

a) Cross-sectional

TEM micrograph of

a Si/Si0.68Ge0.32

layer stack, selectively

grown on standard

STI wafers (shown in

Figure 8a). Facets

are formed at the edges of the window. b) Cross-sectional TEM micro-

graph at the edge of a window of a facet-free Si/Si0.68Ge0.32/Si

layer. Facet formation on the STI wafer is avoided by an in-situ vapor

back etch of the Si surface.

Figure 10. Cross-sectional SEM view graphs of patterned STI wafers

without epitaxial layer. a) After standard processing, and b) after a

controlled Si etch back.Si substrateSi substrate

Si0.85Ge0.15

Si0.68Ge0.32

Si

Si

TO

TO

TO+O TAblanket

blanket

STI wafersingle window(230x230µm2)

STI waferarray of dotswith a Si areaof ~ 38%

NP

NPPL-I

nten

sity

[a.

u]

Energy [meV]700 800 900 1000 1100 1200

Figure 12. 10 K photoluminescence spectra of Si/Si1-xGex/Si layers

measured at a laser excitation power of 50 mW/mm2. The deposition

conditions are similar as for the active layers in HBT devices (15% Ge),

and heterojunction CMOS structures (32% Ge), respectively.

S U B S T R A T E S


the material quality is the measurement of photolumi-nescence (PL) characteristics. Si/Si1-xGex quantum wellstructures have been grown on both blanket and patternedwafers with STI isolation. Deposition conditions as usedfor the HBT and heterojunction CMOS structures weretested. The PL spectra as measured at 10 K (Figure 12)are typical for high-quality, two-dimensional Si/Si1-xGex/Siheterostructures47,48. High-intensity, well-resolved No-Phonon (NP) transitions and their phonon replicas(transversal acoustic TA, transversal optical TO andtwo phonon replica TO+OΓ with OΓ the optical zonecenter replica) arising from the two-dimensional Si1-xGex

layers were observed. The small differences in Ge incor-poration between the patterned and blanket wafers asobserved for a growth temperature of 750ºC is reflected

in the energetic position of the Si1-xGex luminescence.The position of the Si1-xGex NP-luminescence is inagreement with the bandgap as calculated for the mea-sured Ge contents. No degradation of the PL spectra isobserved for the epitaxial layers grown on the patternedstructures. The small peak around 820 meV is correlatedto the mask material and not to the epitaxial structure.

Nevertheless, the final argument to implement epitaxialSi/Si1-xGex layers in active device structures is given bythe device performance. As mentioned above, IMECdeveloped 0.35 µm and 0.25 µm Si1-xGex BiCMOStechnologies, including a selectively grown Si/Si1-xGex

base layer. Furthermore, Si/Si1-xGex layer stacks, withx up to 32%, have been implemented in our standardCMOS process (effective gate length down to 70 nm)to improve the p-channel MOS devices. Device fabrica-tion and a full overview of device characteristics aredescribed in References 2 and 3 (BiCMOS) and in 18-20(heterojunction pMOS), respectively.

HBT devices with an effective emitter area of 0.3 x 5.5 µm2 show maximum FT and Fmax valuesat VCE = 3V of 50 GHz and 80 GHz, respectively.Pattern dependence after full device processing hasbeen investigated by measuring HBT devices withdifferent emitter lengths (Figure 13). The current gainplots show that the peak current is unaffected by thereduction of the emitter length, down to device

wb=45 nmTSi =20 nmTbuf=35 nm

Leeff

:19.5, 5.5, 1.5, 1.1, 0.70, 0.35 µm

300

250

200

150

100

50

010-12 10-10 10-8 10-6 10-4 0.01

Ic [A]

Figure 13. HBT current gain as function of the collector current I C and

for different effective emitter lengths.

42 dies measured

Percent

Ic(isolated npn)Ic(array 1,000 npn)/1000

.01 .1 1 5 10 2030 50 7080 9095 99 99.999.99

1 10-8

8 10-9

6 10-9

4 10-9

2 10-9

0 10-0

Ic(a

t Vb

e=0.

55 V

olt)

[A]

Figure 14. Normalized collector current ( I C ) from an isolated npn HBT

device and arrays with 1000 npn devices.

Mob

ility

[cm

2 /Vs

]

160

140

120

100

80

60

40

20

0-1.5 -1 -0.5 0

VGS[V]

Si ref

15/30

30/15

2 nm Si Cap layer

Figure 15. Extracted hole mobilities for Si/Si1-xGex heterojunction pMOS

devices and a Si reference device as measured at VDS = 20 mV (top),

50 mV (middle), and 100 mV (bottom). 30/15: 2 nm Si-cap/8 nm

Si0.68Ge0.32/5 nm Si/8 nm Si0.85Ge0.15/5 nm Si, 15/30: 2 nm Si-cap/8 nm

Si0.85Ge0.15/5 nm Si/8 nm Si0.68Ge0.32/5 nm Si.

S U B S T R A T E S


geometries of 0.35 x 0.35 µm2. The absence of anymicro-loading effects during epitaxial growth is furtherconfirmed by the independence of the collector currentfrom the transistor density. This is shown in Figure 14,where the collector current of isolated devices and ofan array of 1000 devices are compared.

The long channel hole mobilities as extracted fromSi/Si1-xGex and Si reference pMOS devices are shown inFigure 15. Compared to Si-only devices the Si/Si1-xGex

devices exhibit strongly enhanced mobilities (up to afactor 2.5). The enhanced hole mobility is a directindication for the high material quality after full deviceprocessing. Any imperfections in the Si1-xGex layer orat the Si/Si1-xGex interfaces would lead to scatter center,and, as a consequence, to a reduced hole mobility. Theenhanced hole mobility results in a strong enhancementof the drive current of Si/Si1-xGex pMOS devices comparedto Si reference devices (Figure 16). The drive currentenhancement has been observed for the entire channellength range from 10 µm (55%) down to 70 nm (13%, at gate-source voltage minus threshold voltageVgs-VT = -1 V, and a drain-source voltage of -1.5 V).The improved on-state characteristics have been obtained

without degrading leakage current, short channel anddrain induced barrier lowering behavior18-20. The drivecurrent enhancement is less pronounced for shorterchannel lengths, which is due to velocity saturation.According to literature, a higher current enhancementis expected for ultra-short channel lengths, which hasbeen correlated to velocity overshoot22.

ConclusionsWe reported a selective epitaxial Si1-xGex growth processwith controllable and reproducible Ge incorporationand growth rates. The epitaxial layers show a highdegree of perfection, characterized by smooth surfaces,planar interfaces between the sublayers, and the absenceof defects, which has been verified by PL measurements.Local pattern dependency of the growth rate and Gecontent (micro-loading) has been avoided by reducingthe growth pressure to 20 Torr or below. Furthermore,a wafer scale layer non-uniformity within the accuracyof the measurement techniques has been reached afterfine-tuning of the temperature uniformity and the gasflows. On the other hand, thermal loading cannot beexcluded and makes it necessary to perform the finalfine-tuning of the deposition process on integration waferswith the exact device architecture. The discussed influ-ence of the mask layout on the growth conditions is ofless importance for device applications. This is becausethe feature size is fixed and defined by the layout rulesof the specific application (contacting scheme, etc.)

Facet formation is related to both pattern geometryand growth conditions. {311} facets appear only athigh deposition temperatures (above ~ 825ºC in case ofSi deposition), while the generation of {111} facets iscorrelated with a lateral growth of the growing surfaceover the mask material. A controllable in-situ HClchemical vapor-etch has been developed in order tomodify the height of the Si surface relative to the maskmaterial. This pre-epi surface modification has beenapplied on wafers with STI isolation to deposit facet-free Si/Si1-xGex layer stack as used in p-type hetero-junction MOS devices. The avoidance of facet growth,together with the obtained layer uniformities permita successful implementation of Si1-xGex in devicetechnologies. This is demonstrated by the excellentperformance of Si1-xGex BiCMOS and p-type hetero-junction MOS devices. Electrical test results of finishedBiCMOS transistors do not only express the layer qualitybut also confirm the layer uniformity. The epitaxial layerquality is further expressed by the hole mobility asextracted from p-type Si/Si1-xGex heterojunction-MOS,

-1.5 -1 -0.5 0 0.5

-1.5 -1 -0.5 0 0.5

Vgs [V]

Vgs-VT [V]

ref. AStruct. CStruct. BStruct. A

10-4

10-6

10-8

10-10

10-12

600

500

400

300

200

100

0

Increase ofabout 25%

Increase ofabout 10%

ref. AStruct. CStruct. BStruct. A

I ds[

A/µm

]

I ds[

A/µm

]

Figure 16. Drain current-gate voltage characteristics of Si1-xGex het-

erojunction pMOS devices and a conventional pMOS as measured at

two dif ferent drain-source voltages (VDS = -0.1 V and VDS = -1.2 V).

The channel length Lmask is 70 nm. Structure A: 3 nm Si-cap/8 nm

Si0.85Ge0.15/5 nm Si/8 nm Si0.68Ge0.32/5 nm Si, structure B: 3 nm

Si-cap/8 nm Si0.68Ge0.32/5 nm Si/8 nm Si0.85Ge0.15/5 nm Si, and

structure C: 3 nm Si-cap/8 nm Si0.68Ge0.32/15 nm Si. IDS: drain-source

current, VGS: gate-source voltage, VT: threshold voltage.

S U B S T R A T E S


which is clearly higher compared to the universalmobility curve of Si pMOS devices. The up to 2.5times higher hole mobility results in a 55% and 13%higher on-state current for long and short channeldevices, respectively.

AcknowledgementThe authors wish to thank Dirk Rondas for technicalassistance and Frank Vleugels (SEM), Luc Geenen (SIMS),and Olivier Richard (TEM) for analytical measurements.Furthermore, we wish to thank the Institut für Schichtenund Grenzflächen, Forschungszentrum Jülich for theuse of their PL set-up. Parts of this work have beenfinanced by the EU SIGMUND Project nr. IST-1999-10444, and by the EU Medea T555 Project.

This paper first appeared in similar form in the Journalof the Electrochemical Society Vol 4 150 (no 10), pp.638-647 (2003).

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