High Efﬁciency Power Ampliﬁers for 77GHz Automotive RADARs

High Efficiency Power Amplifiers

for 77GHz Automotive RADARs

Thesis submitted in partial fulfillment of the degree of

Master of Sciencein

Electrical Engineering(Microelectronics)

By

Anand Ramesh4519671

Friday 17th November 2017

Electronic Research LaboratoryElectrical Engineering, Mathematics and Computer Science

Delft University of TechnologyThe Netherlands

Copyright © 2017 by A. Ramesh

In cooperation with

Prof. dr. L.C.N de Vreede M. LontDr. M. Babaie A.J.M de Graauw

ABSTRACT

Automotive RADARs have gained popularity recently as a means to sense obstacles andavoid collisions, thus preventing loss of life related to vehicular incidence. Research inobject detection is increasingly tending towards the 77G H z automotive RADAR band,owing to the availability of larger bandwidths, resulting in high range resolution. An-other advantage of the frequency band comes from the absorption properties of theatmosphere, which limits the range and allows multiple vehicles to use RADARs withminimum interference [1].

A Power Amplifier is the most power hungry block in a transmitter-receiver chainand must be designed for high power efficiency, in order to mitigate radiative and moreimportantly heat losses. However, achieving high efficiency within the target automotiveRADAR band proves to be challenging, specifically in case of integrated CMOS PAs. Thisthesis presents a study of Injection Locked Power Amplifiers (ILPA) in detail and proposesan architecture to meet the RADAR specification. The thesis also highlights passive lossmodels and provides a theoretical analysis of multi-stage power amplifiers by derivingan expression for the total efficiency of such a PA.

Furthermore, this thesis proposes a design procedure and highlights the design pro-cess in 40nm CMOS technology. Emphasis is also placed on the study of the active deviceavailable in the PDK. The designed integrable PA shows a peak output power of 13dBmwith a PAE = 17% and gain= 16dB within a 5G H z band centered around 78.5G H z.

iii

CONTENTS

Abstract iii

1 Introduction 11.1 Review of Existing Literature . . . . . . . . . . . . . . . . . . . . . . . . 2

1.1.1 Injection locked PA Designs . . . . . . . . . . . . . . . . . . . . . 61.2 Comparison of existing literature . . . . . . . . . . . . . . . . . . . . . . 61.3 Thesis Goals and Contribution . . . . . . . . . . . . . . . . . . . . . . . 71.4 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Analysis of Injection Locked Power Amplifiers 92.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2 Tank Loss Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.1 Power Loss Estimation in a Loaded Tank . . . . . . . . . . . . . . . 112.3 NMOS only Power Oscillator Model . . . . . . . . . . . . . . . . . . . . . 12

2.3.1 Ideal switch Model . . . . . . . . . . . . . . . . . . . . . . . . . . 122.4 Injection Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4.1 Output Power and Efficiency within the Locking Range . . . . . . . 152.5 System Architecture Proposal . . . . . . . . . . . . . . . . . . . . . . . . 17

2.5.1 mm-Wave Power Oscillator Structure . . . . . . . . . . . . . . . . 172.5.2 Multi-stage Injection Locked Power Amplifier . . . . . . . . . . . . 182.5.3 Input Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Design of the Power Amplifier 233.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.2 Study of RF transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2.1 Optimum bias point . . . . . . . . . . . . . . . . . . . . . . . . . 243.2.2 RF transistor layout structure . . . . . . . . . . . . . . . . . . . . 253.2.3 Gate Quality factor . . . . . . . . . . . . . . . . . . . . . . . . . . 273.2.4 Unilateral Figure of Merit . . . . . . . . . . . . . . . . . . . . . . 283.2.5 Reliability of RF Transistor . . . . . . . . . . . . . . . . . . . . . . 293.2.6 Electromigration . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3 Design of Class-A Power Amplifier . . . . . . . . . . . . . . . . . . . . . 313.3.1 Classical Class-A PA Design Procedure . . . . . . . . . . . . . . . . 313.3.2 Load-Pull Technique . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.4 Design of Output Stage PA . . . . . . . . . . . . . . . . . . . . . . . . . 343.4.1 Output transistor sizing and impedances . . . . . . . . . . . . . . 353.4.2 Output PADs study. . . . . . . . . . . . . . . . . . . . . . . . . . 363.4.3 Design of Output Matching network . . . . . . . . . . . . . . . . . 373.4.4 Layout of the Output Stage. . . . . . . . . . . . . . . . . . . . . . 38

v

vi CONTENTS

3.5 Design of Injection Locked Power Amplifier Stage . . . . . . . . . . . . . 403.5.1 Unwrapped View of the Power Oscillator. . . . . . . . . . . . . . . 403.5.2 Power Oscillator Biasing . . . . . . . . . . . . . . . . . . . . . . . 413.5.3 Design of the Injectors . . . . . . . . . . . . . . . . . . . . . . . . 443.5.4 Design of Interstage Matching Network . . . . . . . . . . . . . . . 483.5.5 Layout of ILPA Predriver . . . . . . . . . . . . . . . . . . . . . . . 48

3.6 Design of Common-Gate Input Match . . . . . . . . . . . . . . . . . . . 503.6.1 CG stage sizing and biasing . . . . . . . . . . . . . . . . . . . . . 503.6.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.7 Full Chip Integration and placement . . . . . . . . . . . . . . . . . . . . 543.7.1 Pad planning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.7.2 Design of Biasing block . . . . . . . . . . . . . . . . . . . . . . . 543.7.3 Decap Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553.7.4 Full Chip layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4 Simulation Results 594.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594.2 System Startup Simulations . . . . . . . . . . . . . . . . . . . . . . . . . 604.3 Stage wise Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.3.1 Output Stage Simulations . . . . . . . . . . . . . . . . . . . . . . 614.3.2 ILPA and Matching Network Simulations . . . . . . . . . . . . . . 634.3.3 Common Gate Input Stage Simulations . . . . . . . . . . . . . . . 68

4.4 Full-Chip Simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 694.5 Lifetime Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704.6 Comparison With Other PAs In Literature . . . . . . . . . . . . . . . . . . 70

5 Conclusion 735.1 Thesis Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.2 Future Developments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

1INTRODUCTION

RAdio Detection And Ranging systems (RADARs) have been used to detect and estimatethe range and velocity of various objects since late 1930s. A RADAR system may be clas-sified based on the type of output signal used. Popular classifications include the Pulsedand Frequency Modulated Continuous Wave (FMCW) RADARs that differ is output wave-form shape and signal processing chain. While Pulsed modulated RADARs have provedto be better for automotive applications [1], the recent trend of using FMCW modulationis gaining popularity owing to lower bandwidth requirements, strong IC integration andlower power consumption [1]. The 77GHz RADAR band (76GHz to 81GHz ISM band)has been gaining attention as the future of vehicle mounted RADARs as it offers a higherrange resolution (owing to available bandwidth) [1]. Further, attenuation at higher fre-quencies limits sensing distances, thereby limiting interference between multiple auto-mobiles that simultaneously use their RADARs [1].

DAC

ADC

DSP

PA

LNA

Tx

Rx

Rx Chain

Tx signal

Echo signal

Digitalmodulation

Tx Chain

Figure 1.1: Basic block diagram of a RADAR system

Fig. 1.1 shows a basic block diagram of a RADAR system comprising of a transmit(TX) chain and an receive (RX) chain. A synthesizer is used to generate appropriate sig-

1

1

2 1. INTRODUCTION

nals (in this case FMCW signals) at the required frequency that is fed to both chains. TheRX chain receives an echo of the transmitted signal and down converts it to base-bandfor further digital processing. The TX chain primarily comprises of a Power Amplifier(PA) that is responsible for delivering power to the antenna in accordance with the syn-thesized RADAR signal. The amount of power delivered to the antenna directly relatesto the distance detectable by the system for a given medium of propagation. Thus, dur-ing operation, the PA is by far the most power consuming component of the system. M.Babaie from the Delft University of Technology [2] provides a breakdown on the amountof power utilized by the PA and synthesizer is most communication systems, which holdstrue even for the RADAR.

Owing to the amount of power consumed, PAs are generally designed for high ef-ficiencies, which significantly reduces radiative and (perhaps more importantly) heatlosses. From a system perspective, improving PA efficiencies, in general, reduces bothsupply power consumption and eases the design of heat sinks, thus reducing systemcomplexity and costs. Power amplifiers targeted towards automotive RADAR applica-tions are therefore, required to operate within the 77GHz automotive ISM band with ad-equate output power, while demonstrating high efficiency. Furthermore, given a tech-nology, the gain of an amplifying device rolls-off as the operating frequency approachesthe device speed limit (close to ft / fmax ). Reduction in gain directly implies greater inputpower for a given output power. It is therefore, appropriate to consider the Power AddedEfficiency (PAE) instead for PAs working close to their device limits.

The available literature is quite extensive on power amplifier designs at relativelylower frequencies (800MHz-20GHz) that demonstrate high efficiency with considerableoutput power levels. A key trade-off often made within this band is between efficiencyand PA linearity. mm-Wave PAs generally operate quite close to device limits and there-fore, don’t typically achieve high efficiency numbers as their low frequency counter parts.Thus, mm-Wave PAs are still being designed using technologies that allow better deviceperformance such as SiGe BiCMOS, CMOS SOI, etc., while suffering from higher man-ufacturing and integration cost compared to bulk CMOS technology (which finds ubiq-uitous use in digital circuits) [3]. Difference in design techniques at mm-Wave frequen-cies, motivates a study on existing state-of-the-art RF power amplifier designs that maybe used in high frequency RADAR applications.

1.1. REVIEW OF EXISTING LITERATUREThis section explores the literature on PA designs above 40G H z currently published. Im-portant performance parameters of the PA, identified as Maximum Output Power, Over-all PAE, Gain and Relative Bandwidth have been analyzed and compared in Fig. 1.2 forvarious technology nodes. Fig. 1.3 shows supply voltages used in designs across varioustechnology nodes. As seen, there appears to be a typical trend in performance, specifi-cally the average PAE < 20% and average Gain < 20dB with very few designs above thismark, even when designed using technologies other than bulk CMOS. The trend evenholds true over time and within bulk CMOS only nodes, as shown in Fig. 1.4. Few no-table designs have been detailed below:

1. A. Agah, et al., [6] from the University of California, have shown the effectiveness

1.1. REVIEW OF EXISTING LITERATURE

1

3

ST Microelectronics2009 [4]

NTU2013[5]

University of California2012 [6] Hitachi Ltd.

2009 [7]

University ofLeuven

2013 [8]University of

California 2016[9] University of

Melbourne2008 [10]

ETRI, Korea2012 [11]

University ofCalifornia2013 [12]

NationalTaiwan

University2010 [13]

UniBwmM,Infeneon2016 [14]

TU DelftMasoud Babaie

2015 [15] NTU2014 [16]

NTU2015 [17] Lund

University2011 [18]

Figure 1.2: PA designs above 40G H z designed using different technologies

of stacked-FET single ended architecture in 45nm SOI CMOS technology. Shuntinterstage matching is used and proven to improve PAE by an additional 6dB. Atwo stage stacked NMOS structure is used. Interstage matching using CPW andcapacitor is designed to improve the efficiency. A slow wave CPW using floatingmetal lines under the signal line is used to bias the drain. The slow-wave CPWshows greater delay per unit length, thus, helps reduce the physical length of thetransmission line (≈ 20% reduction) required to achieve the same delay.

2. D. Zhao, et al., [8] from Katholieke Universiteit Leuven, have demonstrated a differ-ential input-differential output 2-stage PA. The 2-stage PA is replicated and finallyused to power combine using a series combiner at the output. Input common-gatestage has been designed to match each of the parallel amplifiers to a differentialinput for the purposes of matching with an external equipment that eases test-ing. Each PA stage itself has been designed as a differential amplifier using NMOStransistor devices, and have been neutralized using Metal-Oxide-Metal capacitors.Neutralization acts to effectively eliminate Cd s , thereby boosting high-frequencygain. The two PA stages have been coupled using transformers.

3. B. Wicks, et al., [10] from the University of Melbourne, proposes the use of a five-stage single-ended Class-A amplifier each with a cascode to enhance the gain andmake the design more unilateral by increasing isolation. Each stage is matchedusing transmission lines and capacitors. NMOS transistor are chosen for higherspeed of operation (higher mobility) and thus, lower power can be consumed forthe same frequency of operation. The PA stage proposed is biased in strong in-version region to attain high bandwidth. The transmission lines are shorter than

1

4 1. INTRODUCTION

ST Microelectronics2009 [4]

NTU2013[5]

University of California2012 [6]

Hitachi Ltd.2009 [7]

Universityof

Leuven 2013 [8]

University ofCalifornia 2016

[9]

University ofMelbourne2008 [10]



NationalTaiwan

University2010 [13]

UniBwmM,Infeneon2016 [14]


2015 [15]

NTU2014 [16]

NTU2015 [17]

LundUniversity2011 [18]

Figure 1.3: Supply voltage used in published literature over Technology

λ/4(< 80µm). MIM caps are used to AC couple each stage and the PA is optimizedfor 50Ω output load. This work is targeted specifically towards vehicular RADARapplications.

4. F. Shirinfar, et al., [12], from the University of California, demonstrate a high out-put power, fully integrated PA in 40nm CMOS for 60GHz band. The design focuseson power split and combination techniques. A pre-driver is used to split the inputdifferentially, which is fed to four rows of 4-stage PAs with a total of 8 PAs com-bining power into an 8-way(differential) power combiner(3dB loss) at a 50Ω singleended load. Each PA stage consists of CS differential pairs cascaded using trans-formers along with RC stabilizing circuit. The 2nd and 3r d stage use transformersto divide the output voltage between 4 sets of transistors to reduces voltage swingon the drains/gates, thus, enhancing reliability.

5. T.Y Chang, et al., [13] from National Taiwan University, demonstrates the use ofpseudo differential 3-stage CS amplifier topology with short-stub interstage match-ing, with a transformer based output power combiner. The 1st two stages behaveas pre-drives and are thus, optimized for signal gain and the last stage behaves asa power amplifier. Short-stub matching was chosen to reduce signal degradationcompared to series-stub matching. A balun is used at the input to feed the pseudodifferential structure with a single ended RF input. Input and output is matchedusing transmission lines.

6. J. Wursthron, et al., [14], from Universitaet der Bundeswehr, Muenchen, in collab-oration with Infineon Technologies, propose a differential cascode PA in 130nm

1.1. REVIEW OF EXISTING LITERATURE

1

5

NTU2013[5]

University of California2012 [6]

Hitachi Ltd.2009 [7]

University ofLeuven

2013 [8]

University ofMelbourne2008 [10]



NationalTaiwan

University2010 [13]


2015 [15]

NTU2014 [16]

NTU2015 [17]

LundUniversity2011 [18]

Figure 1.4: PA designs above 40G H z designed using bulk CMOS technology

SiGe Technology, targeted towards the 77G H z automotive RADAR band. The PAdisplays a peak PAE of 16% and peak output power of 17dBm at 77G H z

7. M. Babaie, et al., [15], from the Delft University of Technology, demonstrates aClass-E/F2 power amplifier in 40nm CMOS technology. The completely integrablePA, power combines 2 chains of differential input-differential output, 3-stage poweramplifier, consisting of a pre-driver, driver and output stage. Both the pre-driverand the driver stages are implemented using NMOS devices neutralized by MOMcapacitors. Power out of a driver stage, in each chain is again split between 2 par-allel Class-E/F2 output stages and is recombined in series with the other chain.

A number of observations can be made from the discussion above and Figs. 1.2 to 1.4:

1. Most designs employ a CS stage NMOS device amplifier alongside it’s differentialvariant, with the source terminal tied directly to ground.

2. Gain enhancement in CMOS processes is achieved using neutralizing capacitors.

3. Power combining is quite popular for PA designs at these frequencies that enhanceoutput power while maintaining sufficient efficiencies.

4. Technologies such as SiGe, greatly allow a reduction in the number of stages forsimilar output power compared to bulk CMOS, as seen from [14]. Use of suchtechnologies also follows an increase in supply voltage above 1V which may provebeneficial.

1

6 1. INTRODUCTION

5. Most bulk CMOS technology designs utilize a supply voltage of ≈ 1V with veryfew exceptions. CMOS SOI technology to be quite effective in its RF performance,evidenced by [6], with a supply voltage of > 2.5V .

1.1.1. INJECTION LOCKED PA DESIGNS

Figs. 1.2 to 1.4 also show performance parameters for a different type of PA, commonlyreferred to as Injection Locked Power Amplifiers or ILPAs. This section highlights theperformance of ILPAs without diving into their working and design.

1. J. Lin et al., [16] from Nanyang Technological University, demonstrates the effec-tiveness of an injection-locked CMOS power amplifier for mm-Wave applicationsin 2014. The PA consists of a cross coupled oscillator tank as the power amplifiercore. A single ended RF input is transformer coupled and matched differentially,using transmission lines to the input injection drivers. The single ended RF outputis transformer coupled with the oscillating tank. Lin’s further analysis on improv-ing the PA also lead to another notable publication [17], where the author proposesto buffer the input and output to improve the operating bandwidth of the ILPA,that will consists of a NMOS cross-coupled differential pair. The output bufferamplifier is neutralized with capacitors whereas, the input buffer is designed as acascode amplifier.

2. M. Törmänen et al., [18], from Lund University, have also demonstrated the effec-tiveness of ILPAs, particularly for the 60GHz band. The PA core consists of cross-coupled NMOS pair biased by a current source. A single ended input is differen-tially coupled via injection drivers devices. A 1:2 transformer, behaving as a balunis been used to resonate device capacitance and couple to a single ended output.

1.2. COMPARISON OF EXISTING LITERATURE

As seen from Fig. 1.4, ILPAs have shown higher "gain" and relatively high PAE when com-pared to conventional power amplifiers. They do however, tend to operate with lowerrelative bandwidth. As noted in before, designs at higher frequencies usually exhibitreduced efficiency compared to their low frequency counterparts. This can partly be at-tributed to technology limits as frequencies approach fT of the amplifying element. PAsin the RADAR band have shown a maximum of 15% efficiency. For a 12dBm output, aminimum of about 106mW would be drawn from the supply which would severely heatup the chip. This may also damage the chip along with other components on board overtime and requires extensive design effort to distribute heat and ensure reliability. Hence,there is need to improve the efficiency of PAs subject to technology constraints and out-put power levels. Owing to the modulation scheme employed by RADARs (FMCW),power amplifiers are expected to maintain a fixed amplitude. Injection locked poweramplifiers typically are designed for either phase or frequency modulation schemes andmay therefore, be considered for RADAR applications.

1.3. THESIS GOALS AND CONTRIBUTION

1

7

1.3. THESIS GOALS AND CONTRIBUTIONThis thesis aims to study the phenomenon of injection locking as applicable to poweramplifier designs at mm-Wave frequencies. Theoretical modeling and analysis of anoscillator’s power efficiency aims to provide deeper insight and guide design choices.During analysis, an expression for power efficiency, applicable to a general multi-stagecascade of power amplifier stages has been derived. The expression aids designers inunderstanding the impact of each stage to the overall PA efficiency. Further, the thesisaims to derive a structured procedure to design an Injection Locked Power Amplifier us-ing industry leading 40nm-CMOS technology, given a baseline specification detailed inChapter 2. This work also shows that the design of an ILPA maybe compared with that ofa conventional power amplifier. Finally, a complete test chip layout including relevantmatching and bias circuits has also been presented.

1.4. THESIS OUTLINEThis thesis is organized primarily into three parts, highlighting the analysis, design andsimulation results of the proposed architecture.

Chapter 2 details the loss model of passive circuit elements followed by an analysis ofthe power and efficiency capabilities of oscillators. The chapter also gives a theoreticalanalysis on injection locked power amplifiers. Finally, the chapter concludes by detail-ing the proposed mm-Wave Injection Locked Power Amplifier structure for the 77G H zautomotive RADAR band.

Chapter 3 attempts to develop a structured approach to designing the power am-plifier by first studying important properties of the RF transistor. The chapter contin-ues to develop a simple class-A design procedure based on optimum bias points that isobtained by studying the device. Each amplifier stage in the proposed structure is de-signed in detail wherein, the it proven that the injection locked power amplifier may bedesigned using the same approach used to design a convention power amplifier. Thechapter further highlights design of the common-gate matching stage as per the pro-posed architecture. Finally, axillary circuits such as a simple bias block, decoupling ca-pacitors and PAD ring is presented along with the final schematic and layout of the testchip.

Chapter 4 shows simulation results obtained by testing the proposed test chip. Startupsimulations show the variation of important bias nodes during power on, along with thestartup behavior of the oscillator. Simulation results highlighting the performance ofeach stage is also shown, followed by full-chip simulations showing power, efficiencyand bandwidth achieved. Finally, the chapter concludes by presenting the results of re-liability simulations.

This thesis concludes with Chapter 5, which summarizes the work and highlightsimportant achievements while proposing improvements that may aid in enhancing theperformance of the proposed structure.

2ANALYSIS OF INJECTION LOCKED

POWER AMPLIFIERS

2.1. INTRODUCTIONHarmonic oscillators resonate at a single frequency termed a resonant frequency and are,therefore, widely used to produce timing reference signals [19]. From a general study ofoscillators, one understands that a positive feedback system may potentially oscillate atits resonant frequency, wherein the system meets Barkausen’s criteria for oscillations. Atthis frequency, noise available at the system’s input is amplified and fed back to add-up constructively, therefore depicting infinite gain from any reference external to thesystem. Oscillators can also be viewed as a system with a resonator along with its losses,and an active circuit that sufficiently compensate them, thereby enabling the resonatorto oscillate at its resonant or fundamental frequency [19]. The active circuit compensatesfor the losses by delivering additional power to the resonator. This chapter explores ideathe using oscillators to deliver power to an external load connected to the resonatingtank. First, Section 2.2 describes loss models of capacitors and inductors, followed bySection 2.3 that presents a theoretical analysis of output power and efficiency of a freerunning oscillator. Section 2.4 introduces the concept of injection locking and finally,Section 2.5 describes the architecture of the proposed power amplifier.

2.2. TANK LOSS MODELThis section describes a tank model representing the resonating tank and its losses. Fig. 2.1shows a lossy inductor and a lossy capacitor modeled with an equivalent series resistor,rs,l and rs,c . The losses are described by the device quality factor QL and QC given by:

QL = ωLs

rs,l= Rp,l

ωLp(2.1)

QC = 1

ωCs rs,c=ωRp,cCp (2.2)

9

2

10 2. ANALYSIS OF INJECTION LOCKED POWER AMPLIFIERS

Ls

rs,lZind Zind

Lp

Rp,l

(a) Lossy inductor

rs,cZcap Zcap

Rp,c

Cs

Cp

(b) Lossy capacitor

Figure 2.1: Lossy series and parallel equivalent models of inductors and capacitors

Where, Rp,l and Rp,c are parallel equivalent representations of losses in these elements.High values QL or QC imply lower power dissipation within the element and therefore,lower loss introduced by these elements in the overall circuit. A conversion betweenseries and parallel equivalent resistances may be obtained by enforcing the impedancebetween representations to be equal. In case of the inductor in Fig. 2.1a:

Zi nd = rs,l + jωLs =jωLp Rp,l

Rp,l + jωLp

Or, rs,l + jωLs =(ωLp )2Rp,l

R2p,l + (ωLp )2

+ jωLp R2

p,l

R2p,l + (ωLp )2

∴Rp,l = rs,l (1+Q2L) (2.3)

And, Lp = Ls(1+1/Q2

L

) (2.4)

A similar analysis for Zcap in Fig. 2.1b shows:

Zcap = rs,c − j1

ωCs= Rp,c

1+ jωCp Rp,c

Or, rs,c − j1

ωCs= Rp,c

1+ (ωCp Rpc )2 − jωCp Rp,c

1+ (ωCp Rpc )2

∴Rp,c = rs,c (1+Q2C ) (2.5)

And, Cp = Cs(1+1/Q2

C

) (2.6)

When QL and QC is sufficiently large, such that 1/Q2L → 0 and 1/Q2

C → 0, Eq. (2.4) andEq. (2.6) maybe approximated such that Lp ≈ Ls and Cp ≈Cs . It is, therefore, concludedthat the series-parallel loss representation does not alter the original value of the ele-ment for small losses. A resonant tank obtained by connecting lossy L and C in paral-lel may be described by an equivalent parallel resistor Rp as shown in Fig. 2.2. WhereRp = Rp,l ||Rp,c . It is evident from Eq. (2.3) and Eq. (2.5) that Rp,l and Rp,c are frequencydependent transformations and are therefore valid at a particular frequency of interest.

2.2. TANK LOSS MODEL

2

11

Ls

Rs,l

Cs

Rs,c

Ztank

LpCp

Rp

Ztank

Figure 2.2: LC Tank with a parallel equivalent parallel resistor

This extends to Rp as well, which is typically modeled as Rp = Zt ank (ω0), whereω0 is thenatural frequency of the tank.

2.2.1. POWER LOSS ESTIMATION IN A LOADED TANK

Consider a simple circuit as shown in Fig. 2.3, where an ideal-current source drives It ank

into a lossy LC-tank, loaded by RL . Power delivered to RL is then given by:

PRL = I 2RL ,r ms RL

∴ PRL = 1

8I 2

RL ,p-p RL = 1

8

V 2RL ,p-p

RL(2.7)

Now at resonance:

RL

RpCLItank

vtank IRL

Lossy tank

Figure 2.3: Loaded lossy tank excited by a current source

2


IRL ,p-p = It ank

(Rp

Rp +RL

)

Hence, PRL = 1

8I 2

t ank RL

(Rp

Rp +RL

)2

Now, when Rp →∞Ω

PRL → PRL ,max = 1

8I 2

t ank RL

∴PRL

PRL ,max=

(Rp

Rp +RL

)2

(2.8)

Eq. (2.8) shows the relative power into RL as a simple ratio between Rp and RL . Dissipa-tive tank losses (in dB), arising from Rp can be conveniently estimated using Eq. (2.8) atresonance. Further, to minimize losses, it is desirable to have Rp >> RL which directlytranslates to high QL and QC from Eq. (2.3) and Eq. (2.5).

2.3. NMOS ONLY POWER OSCILLATOR MODEL

An NMOS only oscillator has the capability to deliver power an externally connected loadRL at its resonant frequency. This section explores the power capability and efficiency ofan ideal NMOS only oscillator.

2.3.1. IDEAL SWITCH MODEL

Consider the circuit shown in Fig. 2.4 wherein, an NMOS only oscillator is loaded with aresistance RL across an ideal LC tank. During steady state, NMOS devices are as assumedto behave as perfect switches that commute bias current (I0) alternatively at the resonantfrequency of the tank( f0), as shown in Fig. 2.5.

The Fourier series expansion of im1 is given below [20]:

im1(t ) = I0

2+ 2

π

∞∑n=1

I0 sin(2nπ f0t

)(2.9)

Where, n ∈ Odd Natural Numbers

The fundamental of im1 and im2 flow through RL (as Zt ank ( f0) →∞), which develops avoltage across the tank (vt ank ). Power delivered to RL at f0 is therefore,

PRL ( f0) = 1

8I 2

RL( f0)m1,p-p RL

From Eq. (2.9) IRL ( f0)m1,p-p = 4

πI0

Hence, PRL ( f0) = 2

π2 I 20 RL

2.4. INJECTION LOCKING

2

13

VddLosc

RL

Losc

Cosc Cosc

I0

M1 M2

im1 im2

Vtank

Losc Losc

Cosc Cosc

Losc Losc

Cosc Cosc

Losc Losc

Cosc Cosc

RL

I0

Vtank

im1 im2

vm1 vm2

Figure 2.4: Switch Model of NMOS only Oscillator

The efficiency of the oscillator can now be obtained as:

η= PRL ( f0)

PDC×100

Now, PDC =VDD I0

∴ η= 2

π2

I0RL

VDD×100 (2.10)

Now, the maximum fundamental voltage developed across the tank is given by:

Vt ank,p-p∣∣max = 4

πI0RL

∣∣∣∣max

= 4VDD

Hence, from Eq. (2.10) ηmax = 2

π×100 ≈ 63.66%

Therefore, the maximum efficiency of a harmonic oscillator delivering power to a load is≈ 63.66%. The above analysis reveals that efficiency is limited as the ratio of IRL /I0 = 2/πeven when active devices are considered as ideal switches. This ratio is maintained bythe current source, used to DC bias the oscillator. Efficiency of an oscillator, consideringreal devices is only expected to be lower.

2.4. INJECTION LOCKINGInjection locking is a phenomenon wherein the oscillating frequency, fop of a free run-ning oscillator at f0, is shifted to a frequency equal to that of an external input signal

2


im2I0

I0/2

T

2I0

-2I0

t

im1

0

(a) Current waveforms

t

2VDD

-2VDD

vm2vm1

vtank

0

VDD

(b) Voltage waveforms

Figure 2.5: Currents and Voltages in the oscillators

fi n j , provided fi n j is close to f0. Mathematically, the requirements on fi n j in relation tof0, under low-level injection, is best described by Adler’s famous equation, presented inthe year 1946 [21]. A current domain variant of Adler’s equation is particularly useful instudying cross-coupled oscillators is reproduced below:

∆ fL,s = f0

2Qosc

Ii n j

Iosc(2.11)

Where, ∆ fL,s = Single sided locking range of the oscillator

Qosc = Overall quality factor of the oscillating system

Ii n j = Injected current

Iosc = Current through the free running oscillator

Low-level injection assumes Ii n j to be small compared to Iosc such that:

tan(Φpd ) ≈ sin(Φpd ) (2.12)

Where,Φpd = |ΦIi n j −ΦIosc |

The linear relation between ∆ fL,s and Ii n j in Eq. (2.11) is attributed to the approxima-tion in Eq. (2.12) as detailed by B.Razavi in [22]. As Ii n j increases close to Iosc , Φpd →90, causing the oscillator to move from a locked state to an unlocked state. Physically,f0/2Qosc in Eq. (2.11), represents the single-sided bandwidth of the oscillator due it’sfinite Qosc . Adler’s equation, therefore, describes a fundamental limit to ∆ fL,s as thesingle-sided bandwidth of the oscillator itself, typically obtained when Ii n j ≈ Iosc . It di-rectly follows that in-order to achieve high ∆ fL,s , a low-Q oscillator is desirable.

2.4. INJECTION LOCKING

2

15

Within the context of a power amplifier, the phenomenon of injection locking isleveraged to frequency modulate the output of the mm-Wave power oscillator presentedin Section 2.5.1. The free-running power oscillator generates the required power at asingle frequency, within the desired band with infinite gain. An input signal (withinthe locking range) is injected into the power oscillator that forces the frequency of thefree-running oscillator to locked to the input frequency. The operating frequency of thepower oscillator can therefore be modulated as desired. However, the gain of such a PAwould no longer by infinity, as some amount of power would have be injected into thepower oscillator. Such a power amplifier is called an injection locked power amplifier(ILPA). Current gain of the ILPA can be defined as:

gi = Iosc

Ii n j(2.13)

And therefore, From Eq. (2.11)

∆ fL,s = f0

2Qosc×

(1

gi

)Or, gi∆ fL,s = f0

2Qosc(2.14)

Considering, ∆ fL = 2∆ fL,s , as the total bandwidth of the ILPA and f0/Qosc as the tankbandwidth, independent of active circuit parameters, Eq. (2.14) may be interpreted asthe gain-bandwidth product of the ILPA written simply as:

Cur r ent Gai n ×B and wi d th =Const ant

Similar to a traditional current amplifier, Eq. (2.14) represents a trade-off between cur-rent gain and bandwidth. Evident in both Eq. (2.11) and Eq. (2.14), ∆ fL ∝ Ii n j , given allother variables remain constant.

2.4.1. OUTPUT POWER AND EFFICIENCY WITHIN THE LOCKING RANGEFundamentally, the phenomenon of injection locking is possible only when the oscillat-ing system has a finite Q. Theoretically, a system with infinite Q would continue to main-tain its oscillating state (frequency and phase of both voltage and current), irrespective ofthe external energy injected into the system. This is clearly visible from Eq. (2.11) whenQ →∞ and ∆ fL,s → 0H z.

L C RL-gm

Ytank

Figure 2.6: General negative-gm oscillating system

2


For a general negative-gm oscillating system shown in Fig. 2.6, the voltage (current)waveforms across(in) the tank is a function of the tank impedance at any frequency andtherefore, related to the tank’s Q. Consider ωop = ω0 + δω, such that |δω| < ∆ωL,s (=2π∆ fL,s ),

Yt ank (ω0 +δω) =Gp + j (ω0 +δω)C − j

(ω0 +δω)L

=Gp + j

((ω0 +δω)2LC −1

(ω0 +δω)L

)Considering, ω2

0LC = 1

Yt ank (ω0 +δω) =Gp + jC

(2ω0δω+ (δω)2

(ω0 +δω)

)Defining k(ω0 +δω) = 2ω0δω+ (δω)2

(ω0 +δω)

Yt ank (ω0 +δω) =Gp + jC k(ω0 +δω)

Hence, Zt ank (ω0 +δω) = Gp − jC k(ω0 +δω)

G2p +C 2k2(ω0 +δω)

(2.15)

Now, Vt ank,p−p (ω0 +δω) = 4

πIcs ×Zt ank (ω0 +δω) (2.16)

Clearly, Vt ank varies as Zt ank and Vt ank,max is observed at ωop = ω0, i.e, δω = 0 rad/s .The power delivered to Zt ank at (ω0 +δω) can now be obtained as:

PRp (ω0 +δω) = 1

8

(4

πIcs

)2

ReZt ank (ω0 +δω)

= 1

8

(4

πIcs

)2

×(

Gp

G2p +C 2k2(ω0 +δω)

)(2.17)

Or,PRp (ω0 +δω)

PRp ,max= pr = 1

1+R2pC 2k2(ω0 +δω)

From Eq. (2.2) QC =ω0RpC

∴ pr = 1

1+ (QC /ω0)2k2(ω0 +δω)(2.18)

Also, ηI LPA(ω0 +δω) =PRp (ω0 +δω)

PDC×100

∴ηI LPA(ω0 +δω)

ηI LPA,max= pr (2.19)

Where, PRp ,max = 1

8

(4

πIcs

)2

Rp when δω= 0 rad/s

And, ηI LPA,max =PRp ,max

PDC×100

2.5. SYSTEM ARCHITECTURE PROPOSAL

2

17

pr in Eq. (2.18) represents the relative power delivered to the load across the lockingrange compared to the maximum power delivered at the resonant frequency of the os-cillator, which is as shown in Fig. 2.7 for various values of QC . A symmetric reduction inpr is observed owing to variation in Zt ank wherein smaller values in QC lead to a flatterresponse.

74 75 76 77 78 79 80 81 82 83Frequency(GHz)

4

3

2

1

0

1

Rela

tive

outp

ut p

ower

(dB)

78.5G

QC = 1QC = 3

QC = 5QC = 7

QC = 9QC = 11

Figure 2.7: Variation of pr with δω for various values of Q

2.5. SYSTEM ARCHITECTURE PROPOSALTable 2.1 highlights the baseline target specification for the automotive integrated poweramplifier (provided by NXP Semiconductors). This section proposes an ILPA architectureto meet these specifications, in detail.

2.5.1. MM-WAVE POWER OSCILLATOR STRUCTUREThe tail current source used in the NMOS-only oscillator structure, requires a finite VDS

to keep the transistor in saturation, and therefore, dissipates power. Furthermore, thetail current source restricts the drain voltage swing of the switching core, thereby reduc-ing voltage efficiency of the oscillator [2].

To alleviate power dissipation, the tail current source may be completely removedwith the active oscillating core connected directly to ground. Such an implementationfixes gate voltage of the pair to ≈VDD . However, the ILPA must be turned on only duringtransmit time and turned off once after each complete chirp. To obtain this control over

2


Table 2.1: Baseline target specification for the PA

Parameter Target SpecificationOutput Power (dBm) > 13

PAE (%) > 20Gain (dB) > 15

PA reliability measured at 0.5dB loweroutput power (hours)

> 12000

3rd Harmonic Level (dB) <−30Noise Floor (dB) <−140

VDD

VG,Osc

Rb Rb

CcCc

Figure 2.8: Injection locked power amplifier structure without tail current source and gate voltage bias

biasing, the oscillating core is AC coupled and biased as shown in Fig. 2.8. The biasvoltage VG is fixed as the gate voltage of a diode connected device, behaving as a currentmirror, which allows for control over VG .

2.5.2. MULTI-STAGE INJECTION LOCKED POWER AMPLIFIERFMCW modulation in the ILPA is achieved by appropriate signals at the gate of injec-tor devices that steer current through the oscillator core. Usage of the ILPA as an out-put stage to drive the antenna may potentially result in unintentional frequency shifts,arising from energy coupled into the tank via the antenna irrespective of the input. De-pending on the amount and frequency of the signal coupled through, the ILPA may berendered incapable of transmitting reliably. Direct coupling of large blocker signals forinstance, would prove disastrous for the ILPA. Moreover, the locking range of the ILPAdepends on the Q of the tank and therefore, sensitive to external loads. In order to over-come these issues, the ILPA may be used as a pre-driver stage instead, driving a conven-tional power amplifier as the output stage. This two stage design is expected to delivergreater output power compared to a single ILPA stage while allowing better control overthe tank Q and therefore, the locking range.

EFFICIENCY ANALYSIS OF MULTI-STAGE PAS

Given a certain required output power Pout , it is intuitive that a multi-stage power ampli-fier would exhibit lower efficiency compared to a single stage PA. However, owing to the


2

19

limited gain of a single stage, pre-driver amplifiers may be required to boost up signalsand therefore may be necessary to achieve Pout . A theoretical analysis on the variationof PA efficiency in a multi-stage system may shed light into appropriate architecture andsteer better design choices.

Consider an n-stage power amplifier with its i th-stage (where i ∈ [1,n]) stage ampli-fier operated at an input power level Pi n,i , gain Gi and output power Pout ,i , as shown inFig. 2.9. The output power of i th stage may be expressed as:

Pout,nPout,n-1Pout,1 Pout,2

GnGn-1GiGi-1

Pout,iPout,i-1

G2G1

nn-1ii-121

Pin

SourcePA Load

Figure 2.9: Block diagram of a multistage cascade power amplifier

Pout ,i =Gi ×Pi n,i (2.20)

The total DC power drawn by this n-stage power amplifier is:

PDC ,tot al =n∑

i=1PDC ,i

Or, PDC ,tot al = PDC ,n

(1+ 1

PDC ,n

n−1∑i=1

PDC ,i

)(2.21)

Now, ηn-st ag e =Pout ,n

PDC ,tot al(2.22)

Wherein, ηi =Pout ,i

PDC ,i

∴ From Eq. (2.22) PDC ,tot al = PDC ,n

(1+ ηn

Pout ,n

n−1∑i=1

Pout ,i

ηi

)(2.23)

Now, within the cascade amplifier structure, the output of a stage behaves as the inputto the next.

∴ Pout ,n−1 =Pout ,n

Gn, Pout ,n−2 =

Pout ,n

GnGn−1and Pout ,1 =

Pout ,n∏ni=2 Gi

Substituting Eq. (2.23) in Eq. (2.22) and re-arranging terms, we have:

1

ηn-st ag e= PDC ,n

Pout ,n×

(1+ ηn

Gnηn−1+ ηn

GnGn−1ηn−2+ . . .+ ηn

GnGn−1Gn−2 . . .G2η1

)Or,

1

ηn-st ag e= 1

ηn+ 1

Gnηn−1+ 1

GnGn−1ηn−2+ . . .+ 1

GnGn−1Gn−2 . . .G2η1(2.24)

2


Eq. (2.24) gives the total system efficiency of a multi-stage power amplifier given theoperating gain and efficiency of individual stage in the cascade chain. It is interestingto note that if Gn → ∞, then the efficiencies of all stages prior, would not contributeto ηn-st ag e . Also, from Eq. (2.24) it is clear that ηn dominates over-all efficiency of themulti-stage PA. Further, efficiency of the previous stage is suppressed by the gain of thefollowing stage. Such a relation is reminiscent of the Friis noise figure equation for acascade of amplifiers [23], reproduced below:

Fs y stem = F1 + F2 −1

G1+ F3 −1

G1G2+ . . .+ Fn −1

G1G2G3 . . .Gn(2.25)

Wherein, F1 and G1 represents the noise figure and gain of the 1st amplifier stage, whileF2,F3, . . . ,Fn and G2,G3, . . . ,Gn represent the noise figure and gain of succeeding stages.Here too, F1 dominates the system noise figure and the noise figure of succeeding stagesare progressively suppressed by the gain observed up to that particular stage.

For the proposed two stage system architecture wherein the ILPA is intended as apre-driver stage:

1

ηs y stem= 1

ηOP+ 1

GOPηI LPA(2.26)

Where, ηI LPA = Efficiency of the ILPA stage

ηOP = Efficiency of the output driver

GOP = Power gain of the output driver

In order to achieve high system efficiency, Eq. (2.26) clearly requires that, ηOP , ηI LPA andGOP are all as high as possible and also that ηs y stem ≤ ηOP . Design of the output stagethen also becomes critically important in such a scenario.

Few other general observations may be made using Eq. (2.24), in that efficiency dom-inance of a stage reduces away from the output stage. Focusing effort in designing highefficiency PAs for stages far from the output may not add significant value to the overallsystem efficiency. Specifically for a two-stage PA, both the efficiency and the gain of theoutput stage significantly influence the overall system efficiency.

The power-added-efficiency of the overall system may be obtained using Eq. (2.24)as below:

PAEs y stem = ηs y stem

(1− 1

Gs y stem

)Where, Gs y stem =

n∏i=1

Gi

∴ PAEs y stem = ηs y stem

(1− 1

GnGn−1Gn−2 . . .G1

)(2.27)

It is to be noted that PAEs y stem depends on G1 coming from the overall gain of the sys-tem, whereas, ηs y stem does not. For a two-stage ILPA particularly,

PAEs y stem = ηs y stem

(1− 1

GOP G I LPA

)(2.28)


2

21

Where, G I LPA is the power gain of the ILPA computed between the input of the injectorsto its output, which is expected to be quite high. Therefore, PAEs y stem ≈ ηs y stem , evenin case of a two-stage power amplifier.

2.5.3. INPUT MATCHINGIn order to prove the proposed architecture, a test-chip has been presented in this work.The ILPA as designed, is intended to be integrated along with the transmitter chain andtherefore, expected to be driven by a source 6= 50Ω (typically). However, for the purposesof a test-chip, it is required to match the ILPA to a 100Ω (differential) source, in order todirectly feed from a mm-Wave generator/VNA. The input impedance looking-into the in-jecting device is typically high as shown in Section 3.6. Transforming such an impedancerequires a turn ratio of ≈ 1 : 10 which is impractical.

A common-gate input stage is used in this work as it provides high output impedancewhile its input impedance may be designed to match with a 100Ω source. The common-gate input stage is only designed for purposes of this test chip and is typically unneces-sary when the ILPA is integrated. Further, the CG stage is an active matching system, inthat it requires, a constant DC current for actively matching the chip input to the ILPA.

Fig. 2.10 shows a block-representation of the proposed PA, wherein a differential sourceis fed into a differential CG input stage for matching stage. The output of the CG stage isfed differentially to a cascade of the ILPA pre-driver and the conventional output driverthat delivers power to a differential 100Ω load at output of the test chip.

PA outputboundary

PA Load

100Differential

Output MatchingNetwork

Output StageInterstage MatchingNetworkILPA

Power Osc + Injectors

CG to ILPAMatching

Input CGStage

Input MatchinNetwork

PA inputboundary

PA test-chipboundary

Common Gate Input Match Proposed Power Amplifier Core

100

Differential

Figure 2.10: Proposed block diagram of the Injection Locked Power Amplifier including a CG input matchingstage

3DESIGN OF THE POWER AMPLIFIER

3.1. INTRODUCTIONThis chapter describes the procedure followed to design the PA using Global Foundries40nm bulk CMOS process. During design, single device test benches have been createdto understand the behavior and characteristics of the different devices within the PDK.Each stage has been designed using transistor models available at schematic level fol-lowed by layout and extraction. Owing to layout capacitances (mostly metal overlap),design parameters have been modified in comparison to the schematic in an iterativemanner. The design procedure depicts on final device parameters and impedances.This chapter is outlined to introduce the RF active device by studying its behavior overthe required range of voltages and frequencies in Section 3.2. Section 3.3 then describes asimple structured class-A design procedure to obtain the required performance. Build-ing on this procedure, Section 3.4, Section 3.5 and Section 3.6 highlight the design ofindividual stages. Finally, Section 3.7 describes the test-chip integration and placementof individual blocks.

3.2. STUDY OF RF TRANSISTORThe RF MOS transistor is studied in detail to gain insight about the device in a giventechnology. Outcomes of this study guide design procedures and are expected to revealimportant parameters, such as fmax , maximum available gain etc. The study is also ex-pected to reveal performance limits of the device which aids the designer, find optimumdesign points under given constraints.

Fig. 3.1 shows a schematic of a test bench which is used throughout this study. Nec-essary voltage/current biases and MOSFET device sizes are all variables under the con-trol of the test bench allowing quick changes and parameter sweeps. Ideal inductorswith a value of 1mH are used to dc-feed the active device, while ideal capacitors with avalue of 1mF are used to AC couple the input. Usage of input/output ports allows bothS-parameter and Harmonic Balance(HB) simulations without any modification in theschematic.

23

3

24 3. DESIGN OF THE POWER AMPLIFIER

50

50

IbiasVDD,bias

VDDWTLch

1mH

1mF

1mF

1mH

Figure 3.1: Simple single MOSFET transistor test bench

3.2.1. OPTIMUM BIAS POINTActive devices that are used to amplify signals, work appropriately only under certainvoltage/current biases. It is useful to study the required amplifying qualities of the de-vice under various bias conditions and eventually bias the device close to its optimumpoint. A key parameter in determining the amplifying properties of an active device isfmax , defined as a maximum frequency of oscillation, also called unity power gain fre-quency of the device. At fmax , the small-signal power gain of the device is 0dB . Activedevices have a power-gain greater than 0dB at an operating frequency fop < fmax andtend to attenuate the input at operating frequencies fop > fmax . It is therefore, desirableto maximize fmax of the device. For MOSFET devices, fmax may be simplified as [24]:

fmax ≈√

fT

8πRg Cg d(3.1)

where Rg is the gate resistance and Cg d is the gate-drain capacitance. fT is the frequencyat which |h21| (current amplification factor) falls to unity and is given by:

fT ≈ gm

2πCg s≈

[µ(VGS −VT )

2πL2

](3.2)

Eq. (3.1) and Eq. (3.2) indicate a strong dependence of fmax and fT on gate-source biasvoltage VGS . Additionally, fmax reduces with the product Rg Cg d . To obtain high fT , thedesign parameter VGS must be increased. Now, VGS ∝ Jd , where Jd is the device currentdensity defined as:

Jd = IDS

WT(3.3)

The above discussion follows that fmax strongly depends on Jd .With this definition, the variation of fmax with Jd for various Lch and constant WT /Lch

can be studied as seen in Fig. 3.2.

3.2. STUDY OF RF TRANSISTOR

3

25

10−2 10−1 100

Jd(mA/µm)

60

80

100

120

140

160

180

200

220

240

f max(GHz)

0.315

0.312 Lch=40nmLch=50nmLch=65nmLch=90nmLch=100nmLch=120nm

Figure 3.2: fmax vs Jd for varying Lch and WT /Lch = 600

As seen, fmax increases with increasing Jd and reaches a peak at ≈ 0.3m A/µm. Fur-ther increase in Jd causes the device to be biased close to the triode region which causesa drop in fmax . An optimum Jd ,opt ≈ 0.3m A/µm where fmax reaches its highest valueis therefore, chosen as the biasing point. It is further seen that peak fmax reduces withincrease in Lch . However, as an observation, for these RF transistors, peak fmax slightlyincrease from Lch = 40nm to Lch = 50nm. This variation maybe attributed to mobilityreduction for small channel length devices [25] that ultimately leads to a slightly lowerfmax . A greater value of Lch is preferred to aid in improving the reliability of the cir-cuit (explained in Section.3.2.5). Therefore, all core transistors are designed with a gatechannel length(Lch) = 50nm and are biased close to Jd ≈ 0.3m A/µm.

3.2.2. RF TRANSISTOR LAYOUT STRUCTURE

MOSFETs used in the design of power amplifiers, typically tend to have large WT /Lch

ratio in order to deliver high output power. These devices tend to exhibit relatively lowerbreakdown voltages (as seen later in Section 3.2.5) but have the ability to source/sinklarge currents when dimensioned appropriately. A single device with high WT /Lch ratiois difficult to layout as it occupies area in a single dimension(i.e., horizontal). Transistorswith large WT may be dimensioned into an integral number of parallel devices, calledfingers, each with a unit width W f i ng er << WT such that the number of fingers(N f )≈WT /W f i g ur e . Transistors constructed from fingers connected in parallel occupy a smallerphysical area as layout involves overlap of individual source/drain regions. Perhaps amore significant advantage of multi-fingered transistors is the reduction in gate resis-tance. As seen from Eq. (3.1), fmax improves with a reduction in the product Rg Cg s , thatis obtained from multi-fingered devices. For large N f however, the improvement in Rg

may no longer be visible. On the contrary, resistance from the interconnects used toconnect multiple fingers may dominate. To further increase the width, transistors may

3


again be divided into multiple identical devices (denoted by the variable Mul t ), eachwith a fixed number of fingers and unit finger width. These multiple transistors can thenbe connected in parallel as before, hence, the total transistor width (WT ) may be dividedas:

WT =W f i ng er ×N f ×Mul t

It must however, be noted that using a large number of multiple identical devices wouldalso require long paths for interconnections to a common node. This would translate toresistive/inductive source degeneration thus, reduced gain.

C40 METAL STACK

The CMOS 40nm (C40) technology used in this thesis consists of a single polysilicon layer(PC), seven metal layers (M1-M5 are thin metals while M6-M7 are thick metals) and oneultra thick metal layer(LB) as shown in Fig. 3.3. M6 and M7 are also referred to as FA andFB that are used mostly as the top metal layers for individual circuit blocks in the IC. TheLB metal layer is used to interface with various bias and ground PADs owing to its lowsheet resistance. It is noted that while LB offers the least sheet resistance, the EM boundfor the metal is significantly lower compared to FA and FB. The difference stems from thefact that LB is made from Aluminum, while other metals are made from Copper. Trackscarrying high bias currents are therefore, drawn using combinations of FA, FB and LB.Inductors available in the PDK are designed using FB. High-Q inductors (also availablein the PDK) have been designed by stacking both FA and FB.

PCM1-M5FA (M6)

FB (M7)

LB

(a) Side View (b) Isometric View

Figure 3.3: Global Foundry C40 Metal Stack

RFNMOS DEVICE LAYOUT

The multi-finger layout of the RFNMOS transistor can be understood through the figureshown in Fig. 3.4. The device chosen in the example has WT = 30µm = 1µm × 30× 1.The source and drain opposite to each other where fingers are connected using a stackof M1-M5 for current density. The terminals are finally connected to FB via FA. The gateterminal has been connected using PC-M2 on either side (below the source and drain).The two gate tracks are then connected at one end using M1-FB. M1 is also used to drawof the substrate as a ring around the device.


3

27

Gate Drain/Source

Sub

(a) Side View

Gate Drain

Sub

Source

(b) Back View

Gate

Drain

Sub

Source

(c) Top View

GateDrain

Sub

Source

(d) Isometric View

Figure 3.4: Layout of RFNMOS device with WT = 1µm ×30×1 = 30µm

3.2.3. GATE QUALITY FACTOR

MOSFETs are voltage controlled devices that modulate their output current (typicallydefined as id s ) with respect to gate voltage variation vg s . It follows that, ideally, the in-put power consumption of MOSFETs is 0W . However, at RF and mm-Wave frequencies,the gate power consumption becomes significant. This phenomenon is understood myobserving the simple RC model of the MOSFET’s input shown in Fig. 3.5.

iin

vin (t)

(t) iin

vin (t)

(t)

Rgin

Cgin

Figure 3.5: Lumped RC high frequency gate model of the RF transistor

Rgi n may include the gate wiring resistance that exists as a consequence of the tran-sistor’s layout. Gate power is dissipated in Rgi n as the reactance (Xcgi n ) of the gate-capacitance comparatively reduces with increase in frequency. It is therefore, neces-

3


sary to study the variation of gate quality factor (Qg ) to estimate these losses. Fig. 3.6ashows a typical behavior of Qg . The curve is obtained by biasing the RF transistor closeto Jd = 0.3m A/µm and performing S-parameter simulations, with the input and outputterminated by a 50Ω port. As seen, Qg reduces with frequency and is about 7-10 for theRF transistors in the 76G H z-81G H z band. Low Qg indicate greater power requirementsto drive the device for a given vi n(t ). The increase is drive power requirements, directlycause a reduction in the power gain of RF transistors at these frequencies. Fig. 3.6b showsthe variation of Maximum Gain, Maximum Stable Gain and Maximum Unilateral Gain.A gain of 3dB - 8dB is expected from the RF transistor in frequency band of interest,while a gain > 35dB maybe achieved at lower frequencies.

108 109 1010 1011 1012

Frequency(Hz)10−1

100

101

102

103

104

Qg

100.0M,3778.0

78.5G,7.876

Lch = 50nm

WT = 180µmWT = 72µmWT = 16µm

(a) Variation of Qg at constant Lch

108 109 1010 1011 1012

Frequency(Hz)10

0

10

20

30

40

50

60

Powe

r gain

(dB)

7.942

4.343

78.5G

WT = 180µm and Lch = 50nm

Maximum GainMaximum Stable GainMaximum Unilateral Gain

(b) Variation of small-signal Power Gain withfrequency

Figure 3.6: Variation of Quality factor and Power Gain for the RF NMOS device

3.2.4. UNILATERAL FIGURE OF MERITMOSFET’s have finite input-output isolation in any configuration. Specifically, in theCommon-Source (CS) configuration, the input-output isolation is dominated by the ca-pacitor Cg d . At lower frequencies, Cg d is greatly responsible for the reduction in theforward gain. However, at RF and mm-Wave frequencies, this feedback capacitor maycreate instabilities by introducing the phase-shifts depending on the load and sourceterminations. Even when the device is not operated at this drastic frequencies, the finiteisolation co-relates the input and output device impedances. It is necessary to study theisolation properties of the RF MOSFET in order to understand the degree of dependencebetween these impedances.The RF device maybe modeled by a 2-port representation and characterized by scatter-ing or S-parameters [26]. The input and output reflection coefficients of such a model isobtained as:

Γi n = S11 − S12S21

1−S22ΓL

Γout = S22 − S12S21

1−S11ΓS


3

29

Where ΓL and ΓS represent the load and source terminations respectively. A non-zerovalue of |S12| represents finite isolation between the load and source. The UnilateralFigure of Merit may then be defined as [26]:

Um = |S21|2|S12|2|S11|2|S22|2(1−|S11|2)(1−|S22|2)

(3.4)

Where,1

(1+U 2m)

< GT

GTU< 1

(1−U 2m)

Here, GT is the transducer power gain of the MOSFET with finite isolation (under giventerminations), and GTU is the gain of the MOSFET assuming infinite isolation under thesame loading conditions. It is desirable to have Um ≈ 0, and practically, the unilateralassumption maybe valid for Um < −15dB . From Eq. (3.4), it is clear that Um does notdepend on the terminating impedances and can be defined using only the S-parametersof the device. The variation of Um with frequency for different sizes of the RF MOSFETis depicted in Fig. 3.7a. As seen, Um is quite high at low frequencies and reduces close

100 101 102 103

Frequency(GHz)

30

25

20

15

10

5

0

Um

(dB

)

78.5G

Lch=50nm

Nf=16,Mult=1

Nf=18,Mult=4

Nf=30,Mult=6

(a) Variation of Um with frequency

0 5 10 15 20 25 30 35 40

Nf

18

17

16

15

14

13

12

11

10

9

Um

(dB

)

Wfinger=1µm, Lch=50nm

(b) Variation of Um with N f

Figure 3.7: Variation of Um with frequency for difference transistor configurations and variation on Um withN f at 78.5G H z

to the operating frequency. Higher value of Um may lead to instability that is observedat lower frequencies in mm-Wave PAs. It can be concluded that the RF MOSFET is moreor less unilateral at the frequency of operation. However, designers should be cautiousof using transistor sizes with smaller geometry (10µm~20µm), as Um is quite high forthese sizes even at high frequencies, seen in Fig. 3.7b. The increase may be explainedas a non-linear scaling of Cg d compared to Cg s that causes smaller device geometry toshow relatively higher Um . While Um for these size is relatively low when compared to itsvalue below 10G H z, it is shown later that even such numbers, still do cause issues withmatching for smaller device sizes.

3.2.5. RELIABILITY OF RF TRANSISTORMOSFETs are subject to several kinds of reliability issues that degrade their performanceover time. A complete analysis of various failure mechanisms is beyond the scope of this

3


thesis and readers are encouraged to refer [27] for more information on the subject. TheGlobal Foundry CMOS 40nm transistors, used in this work, have been known to sufferfrom Hot Carrier Injection (HCI) and Drain Avalanche Hot Carrier (DAHC) Generation,similar to other bulk CMOS technologies. Power amplifiers are designed for high drainvoltage swings to increase output power and efficiency, which may directly impact theirlifetime. For this technology, high drain voltage leads to transistor lifetime degradationdue to DAHC generation. As observed in [27], DAHC is typically caused due to increaseddrain electric fields that may be mitigated by either lowering the drain voltage swing orby increasing the gate channel length.

1.0 1.2 1.4 1.6 1.8 2.0 2.2

Drain Voltage(VDS)

10-1

100

101

102

103

104

105

106

Life

tim

e(h

ours

) 12000.0

VGS=1.1V

Lch=40nm

Lch=50nm

Lch=65nm

Lch=90nm

Lch=100nm

Lch=180nm

Figure 3.8: Lifetime vs VDS for varying Lch

It is important here to define lifetime as the time taken (in hours) for the drain cur-rent (Id ) of the RF MOSFET to drop below 10% of its value measured after 1 hour, whenoperated continuously under constant gate bias of 1.1V .Fig. 3.8 shows the variation of device lifetime under varying drain bias voltage for differ-ent Lch . During lifetime simulation, VDS was held constant using a voltage source andthe results are expected to be different for an alternating output waveform. However, thissimulation still gives an indication regarding the range of drain voltages that may lead tohigher lifetimes. As seen, for Lch = 50nm, the device lifetime dropped below 12,000hours for a VDS ≈ 1.3V . There appears to be a drastic reduction in the device lifetimefor VDS > 1.5V ~2V . As mentioned before, PA designs typically tend to increase the drainvoltage swing to improve efficiency, however, as a general guideline this thesis attemptsto restrict the peak-voltage of a pure output sine wave to ≈ 1.5V . From Fig. 3.2, it is clearthat higher values Lch degrade the transistor’s performance though it helps in improvingreliability. There exist a trade-off while deciding the best option between performanceand reliability, analysis of which may be iterative during design. In order to achieve highgain and simultaneously meet the lifetime specification, this thesis uses Lch = 50nm forcore active transistors used in the power amplifier.

3.3. DESIGN OF CLASS-A POWER AMPLIFIER

3

31

3.2.6. ELECTROMIGRATION

Metal tracks used in IC technology are subject to reliability issues owing to the phe-nomenon of Electromigration(EM). Fundamentally, EM is caused due to the exchangeof excess momentum between electrons and stationary kernels that cause a change intheir position, leading to physical damage of the metal lattice. Severe EM can even breakmetal tracks leaving nodes in an IC unconnected. From [27], it is observed that EM pri-marily depends on the current density of the metal track at any given point of time. PAsare the most power hungry blocks in any transceiver (while in operation). Hence theymust be designed considering the effects of EM. For large currents, metal tracks mustbe made sufficiently wide to effectively keep current density at a safe operating value.Therefore, in this work, the EM bound is considered to determine the absolute minimumtrack width for the given a current. Specific interconnects are made wider compared totheir EM bound to combat resistance in some parts of the design. EM bound for themetal stack is available from the Global Foundry Design Rule Manual (DRM), as closedform equations dependent on their respective track widths.


Conventionally, high efficiency in power Amplifiers is achieved by waveform shaping ofthe voltage(current) across(through) the active device [28]. Waveform shaping reducesthe overlap of voltage and current in the transistor resulting in reduced power dissipationin the device, thereby, increasing the operating efficiency. It is typically the goal of con-ventional high-efficiency PA designs to achieve such non-overlapping current/voltageswaveforms. Any wave-shaping technique inherently involves the use of higher order fre-quency harmonics to prevent the overlap of voltage and current. Observing Fig. 3.2, itis evident that fmax of the transistor is ≈ 225G H z. Considering the operating band of76G H z − 81G H z, generation of higher order frequency harmonics becomes expensivein terms of the input power drive. The transistor’s power gain at higher harmonics isexpected to be lower than 1dB evidenced by Fig. 3.6b. This physical reason, restrictswave-shaping options (if any) in the frequency band, motivating the design of saturatedClass-A power amplifiers instead.

3.3.1. CLASSICAL CLASS-A PA DESIGN PROCEDURE

PAs designed in the class-A mode of operation are characterized by a conduction angleof 360 at the device plane. These PA may, therefore, achieve a maximum drain efficiencyof 50% (as demonstrated below). To derive insight, consider the ideal output character-istics of MOSFET shown in Fig. 3.9a, with knee voltage Vk .For high output power, it is desirable to maximize both the drain voltage and drain cur-rent swing of the MOSFET. RF PAs are typically biased using an DC-block to minimize(ideally eliminate) any DC power consumed by the load, as shown in Fig. 3.9b. The RF-choke increases the drain voltage swing beyond VDD . In order to achieve a symmetricswing, the peak drain voltage is restricted from Vk (≈ 0V ) to 2VDD , as the device is DCbiased at VDD . If the peak drain current is Id ,peak (at vd s (t ) =Vk ) for a given output load

3


(RL), then:

Pd =Vd ,r ms Id ,r ms =1

8(2VDD −Vk )Id ,peak (3.5)

From load line analysis:

Id ,peak = 2VDD −Vk

RL(3.6)

∴ Pd = 1

8

(2VDD −Vk )2

RL(3.7)

2VDDVDD Vds

Id

Id,peak

0 VK

Id,peak/2 Slope=-1/RL

(a) Output Characteristics

vds(t)

VDD

DC Block

RF-Choke

RL

id(t)(t)vin

(b) Class-A circuit

Figure 3.9: Ideal Device Output Characteristics of a MOSFET and Typical Class-A topology

When biased at Vd s,DC =VDD and Id ,DC = Id ,peak /2, the drain efficiency may be com-puted as:

ηd = Pd

PDC×100

ηd = 1

8

(2VDD −Vk )Id ,peak

VDD Id ,peak /2×100

∴ ηd = 1

4

(2− Vk

VDD

)×100 (3.8)

It is evident from Eq. (3.8) that, if Vk → 0V , ηd → ηd ,max = 50%. It is noted that thechosen biasing point allows a non-zero voltage across the device and a non-zero currentthrough it, even when there is no input signal. Lower frequency, high efficiency PAs aredesigned by choosing different biasing points such that little to no voltage and currentoverlap exists when the amplifier is inactive (no input signal) [28].

3.3.2. LOAD-PULL TECHNIQUEThe optimum load RL,op for the single-ended transistor stage is highly optimistic formm-Wave designs. As observed in [28], at mm-Wave frequencies, the required load is


3

33

shifted owing to the capacitance at the drain. This shift is observed as the capacitive re-actance reduces when compared with the load resistance (device Q) at high frequencies.A load inductor, used to DC bias the drain maybe designed to tune out the dominantcapacitance. An accurate direct computation of the capacitance tends to become signif-icantly difficult. Microwave designers resort to simulations instead, by varying the loadimpedance at the drain (output) of the device and measuring desired parameters. Such asimulation is termed Load-Pull and has an equivalent in Source-Pull, wherein the sourceimpedance is varied [28]. A simple load-pull simulation may be performed in moderncircuit simulators by:

• using an ideal input voltage source. This avoids the need to tune the source impedancein accordance with the load.

• using a variable load impedance, preferably having the capability to recognize po-lar representation. This allows a scan of the passive quadrant of the Smith Chartusing only two variables.

Fig. 3.10 shows a load-pull setup used throughout this work in Cadence IC simulator thatincludes the RFPort adapator block which transforms a fixed 50Ω port to ΓL based ontwo parameters: mag and θ. Such an arrangement, then allows a scan of the passivequadrant of the Smith Chart with its origin at ZL,or i g i n = 50Ωwhen mag = 0.

50

L

Figure 3.10: Load-Pull simulation setup in Cadence IC design environment

VG is fixed using a MOSFET similar to the device under test (DUT), that is connectedas a diode to mirror the required current into the DUT. Ideal DC-Blocks and RF-Chokes(DC-feeds) are used to appropriately bias the device. Output power is measured at theΓL

plane, while the input power is measured as the power out of the voltage source. Devicepower gain at a given frequency and biasing condition is computed as:

Device Gain = Output Power at ΓL

Input Power from vi n(t )

3


8 18

31

50

80

140

300

-150j

-80j-50j

-31j

-16j

0

16j

31j50j

80j

150j

8 18

31

50

80

140

300

Constant Power contours (dBm)

1011.5

Figure 3.11: Example of Constant Power contours plotted on a Smith Chart

Contours of Constant Power, Constant PAE and Constant Device Gain are then plot-ted on a Smith Chart. The contours tend to be concentric in nature; decreasing radiuswith an increase in the value of the parameter. Fig. 3.11 shows few Constant Power con-tours as an example in the range [10dBm,12dBm] with 0.5dBm increments, for a devicesize of 180µm/50nm. An ideal impedance is a point where the maximum (smallest ra-dius) Power, PAE and Gain contours intersect, which is typically not observed. Rather,an optimum impedance that simultaneously maximizes the three contours may be ob-tained. This load-pull setup has the capability to scan the entire passive quadrant of theSmith Chart which tends to take quite a lot of time. Eq (3.7) may aid in simplifying theendeavor by giving the designer insight on the value of the optimum impedance whichrestricts the range of points required to perform the simulation.

Based on the above sections, a formal design procedure may be obtained, shownin Fig. 3.12. The procedure enables computation of the biasing current and transistorsize using Eq. (3.7), Eq. (3.6) and Eq. (3.3) given the output power, VDD and Jd ,opt areknown. Load-pull simulation can then aid in determining the exact impedance as perrequirements.

3.4. DESIGN OF OUTPUT STAGE PAThe design of the power amplifier begins with its output stage that has an ideal targetPout of 13dBm. However owing to passive losses at these frequencies force the consid-eration of higher output power. Therefore, a better approach would be to target 15dBm

3.4. DESIGN OF OUTPUT STAGE PA

3

35

Optimium RL

≈ 8Pr equi r ed

(2VDD )2

VDD

From Reliability and ηRequired Power

Required biasing current

Ibi as =Id ,peak

2

Id ,peak ≈ 2VDD

RL

Sizing

WT = Ibi as

Jd ,opt

Perform Load-pullFind Optimium bias point

RequirementsMet?

Find better pointRecalculate RL , Ibi as ,WT

assuming finiteVk to reduce error

noCompleted PA stage

yes

Figure 3.12: Flow-chart depicting the design procedure used for the design of class-A amplifier

at the transistor plane of the output stage.Noting that the stage is differential in nature, a single ended design targeting 12dBmoutput should be sufficient to meet the power specifications. With the required powerand VDD known, Fig. 3.12 is used to obtain the required current and size of the transistor,as shown in Fig. 3.13.

Input requirements

Pout = 12dBm

VDD = 750mV

Optimium RL

≈ 8Pr equi r ed

(2VDD −Vk )2 ≈ 18Ω

Bias Current

≈ 12

2VDD−VkRL

≈ 42m A

Sizing

≈ Ibi asJd ,opt

≈ 180µm = 1µm ×30×6

Load pull simulations

Figure 3.13: Output stage optimal resistance and bias current

3.4.1. OUTPUT TRANSISTOR SIZING AND IMPEDANCESThe ideal calculations (Vk = 0V ) indicate a minimum WT ≈ 141µm when biased at Jopt =0.3m A/µm. However, owing to non-idealities of the MOSFET, WT is increased to 180µmwith a DC biasing current close to 54m A. A load-pull simulation is performed with thisconfiguration to find an optimum impedance targeting 12dBm output power, highestpossible PAE and gain. The result of the load-pull simulation is show in Fig. 3.14. An

3


optimum load ZL,opt−si ng le ≈ 6 + j 6.5Ω is chosen wherein Pout ,expected ≈ 12.08dBm,Gexpected ≈ 6dB , PAEexpected ≈ 33%. It is interesting to see that

ZL,opt−si ng le ≈ 6+ j 6.5Ω

YL,opt−si ng le ≈ 76.677− j 83.067mS

At 78.5GHz, YL,opt−si ng le may be modeled as a parallel combination of 13.04Ω and 24.25pH .The real part YL,opt is close to the load obtained from the simplified model of the MOS-FET. ZL,opt−si ng le represents the optimum impedance for a single-ended configuration.The equivalent differential load is expected to be

ZL,opt−di f f ≈ 2×ZL,opt−si ng le ≈ 12+ j 13Ω

Both Gexpected and PAEexpected remain unchanged compared to the single-ended con-figuration, while the output power is expected to be 3dB higher.

8 18

31

50

80

14

0

30

0

-150j

-80j-50j

-31j

-16j

0

16j

31j50j

80j

150j

8 18

31

50

80

14

0

30

0

Const power contours (dBm)

Const PAE contours (%)

Const Gain contours (dB)

Pout ≈12.08dBmPAE≈33%Gain≈6dBZin ≈1.39-7.67jΩ

(6.02+6.49j)

Figure 3.14: Load-pull contours for single ended transistor (180µm/40nm) used in the output stage at78.5G H z

3.4.2. OUTPUT PADS STUDYThe output stage is connected to the 100Ω load via chip PADs. The complete PAD ringhas been designed internally by NXP Semiconductors and is proven to work on earliertest chip tape outs. It is therefore considered as a component that may not be changedfor the purpose of this work.


3

37

8 18

31

50

80

14

0

30

0

-150j

-80j-50j

-31j

-16j

0

16j

31j50j

80j

150j8 18

31

50

80

14

0

30

0

PAD impedance in 1GHz to 100GHz

PAD impedance inband

(100+0j)@1GHz

(52-9.65j)@78.5GHz

(a) PAD impedance on Smith Chart

100 101 102

Frequency(GHz)

9.0

9.2

9.4

9.6

9.8

10.0

10.2

10.4

Pow

er

at

Chip

Sid

e a

nd into

Load (

dB

m)

78.5G

Power at Chip SidePower into 100Ω

Power Loss

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

Pow

er

Loss

(dB

)

0.595dB

9.4dbm

(b) PAD loss

Figure 3.15: Variation of PAD impedance and losses with frequency

At high frequencies, the impedance seen by the output stage is expected to be shiftedby these PADs and must be taken into account while designing the matching network.Typically at lower frequencies, chip PADs add capacitance and the interconnects leadingto the PADs generally do not contribute to phase shifts. However, at RF and mm-Wavefrequencies, both the structure of the PAD and the interconnect must be studied andpreferably modeled. A simplified model of the PAD is used in this work to gain insight onthe expected impedance levels and phase shifts which are important before proceedingtowards the design of the output matching network.The results of the S-parameter simulation, as shown in Fig. 3.15a, reveal the variation ofimpedance seen at the chip side of the PAD (ZPADs ) when a constant 100Ω (differential)port is connected externally. As seen, the 100Ω is transformed to an impedance of ≈52− j 9.65Ω at 78.5G H z. The structure scales down an externally connected impedance,which allows the possibility to deliver higher power to the load. ZPADs turns inductiveabove 100G H z owing to the dominance of the interconnect inductance compared to thecapacitance of the pad.Fig. 3.15b shows the losses inherent to the PAD in the band of interest. PAD losses aresimulated by computing the power into the external 100Ω port when compared with thepower out at ZPADs reference plane, while ensuring a conjugate match at each frequencypoint. As observed, about 0.58dB~0.62dB of loss is expected in the frequency band.

3.4.3. DESIGN OF OUTPUT MATCHING NETWORK

The output matching network transforms ZPADs (and not 100Ω) to the optimum impedancerequired at the transistor plane in order to derive the performance simulated by load-pull. From Section 3.2.4, the output and input matching networks may be designed in-dependently with respect to each other as the unilateral figure-of-merit for the device isexpected to be quite low. As the output stage of a PA typically produces maximum power,any loss while matching substantially degrades performance. Therefore the primary aim

3


of this design is to reduce components losses.A structure of the matching network may be obtained by noting that a load inductoris required for both matching and biasing at the drain. Given ZPADs and the optimumimpedance from load-pull in Fig. 3.14, the matching network may be derived using asmith-chart shown in Fig. 3.16a. The resulting π-network is as shown in Fig. 3.16b.Lumped components used in the matching network are considered along with their ex-pected finite Q’s as it allows for an accurate estimate of component parameters.

Diff. Tline

Zop-stage opt≈51.8-j9.3

ZPADs≈51.8-j9.34

Shunt Cap

Load Ind

(a) Smith Chart

≈55.8pH

Z0≈79.6, =18.8°

VDD

Zop-input ≈51.8-j9.34Zop-stage, opt ≈12.185+j8.63

≈43.8fF

To Drainof Output Stage To PADs

(b) Schematic

Figure 3.16: Output matching on Smith Chart along with the schematic of output matching network

3.4.4. LAYOUT OF THE OUTPUT STAGE

Inpu

t Mat

ch

ch

TL

W = 1m×30×6=50nm

100

Chi

p O

utpu

t PA

Ds

ZPADsWT = 1m×3×1

Lch = 50nm

Ibias≈1mA

RC bias filter

VG

IVDD≈108mA

VDD

Z0≈79.6, =18.8°

≈55.8pH≈43.8fF

Figure 3.17: Schematic of the Output Stage including biasing circuit

Fig. 3.17 shows the final schematic of the output stage including the device con-


3

39

nected as a diode, used for biasing. To begin layout, minimum metal track widths arecomputed to satisfy EM bounds. The transistor source terminals for the differential pairare connected together and drawn out from the geometric center to maintain symmetryas shown in Fig. 3.18. The ground metal track carries the total DC current from VDD andis therefore, made as wide as possible. To further increase the ground’s current carryingcapability and to reduce ground resistance, metal M2 to FA are stacked. Bottom metallayers (M2 to M5) may be drawn (without slotting) with a maximum width of 4.5µm, en-forced by process DRC. FA is drawn with a width of 8.5µm symmetric to lower metals, asshown in Fig. 3.19. VDD and ground are de-coupled locally while M1 is used a groundplane to prevent long inductive loops that are apparent at RF and mm-Wave designs(Section 3.7.3).

Figure 3.18: Layout of output devices

Figure 3.19: Layout of the output stage

3


3.5. DESIGN OF INJECTION LOCKED POWER AMPLIFIER STAGE

Design of the injection locked power amplifier(ILPA) begins by noting the input powerrequirements of the output stage. The output stage has a gain of ≈ 5dB~6dB with atarget output power of 15dBm. Therefore, the ILPA must have the capability to deliverat least ≈ 10dBm. It is required to develop a design procedure to arrive at the transistorsizes and impedances that would achieve this performance.

3.5.1. UNWRAPPED VIEW OF THE POWER OSCILLATOR

The NMOS only cross-coupled power oscillator in Fig. 2.8, may be re-drawn as shown inFig. 3.20. The unwrapped representation is helpful when considering the cross-coupledpair as individual, single device power amplifiers feeding the load. Voltage swing acrossthe load then behaves as an input to the next stage.

VDDVg,osc

RL,single

CC

VDDVg,osc

RL,single

CC Pd,singlePg,singlePg,single Pd,single

PRL,singlePRL,single

Figure 3.20: "Unwrapped" NMOS oscillator

When steady state is achieved, considering ideal passive components (without loss),power out from the drain reference plane of each PA, flows into the load with someamount of power going into the gate, which may be considered as a measure of the finiteoscillator’s intrinsic Quality factor. This statement is mathematically expressed as:

Pd ,si ng le = PRL,si ng le +Pg ,si ng le (3.9)

Now, let G = Pd ,si ng le

Pg ,si ng le(3.10)

Then, Pd ,si ng le =(

G

G −1

)×PRL,si ng le (3.11)

Or, PRL,si ng le =(

G −1

G

)Pd ,si ng le (3.12)

G in Eq. (3.10) represents the power gain of the single device power amplifier. Eq. (3.12)indicates that Pd ,si ng le must be designed larger than the load power requirements, bya fraction determined by the power gain of the device. The power efficiency of each


3

41

individual stage is then given by:

ηd ,si ng le =PRL,si ng le

PDC ,si ng le×100

=(1− 1

G

)(Pd ,si ng le

PDC ,si ng le×100

)(3.13)

∴ ηd ,si ng le = ηd

(1− 1

G

)(3.14)

Where ηd ,si ng le =Pd ,si ng le

PDC ,si ng le×100

Eq. (3.14) resembles the PAE equation of a power amplifier, which is expected fromthe premise of this view. It is interesting to note that ηd ,si ng le is expected to be nu-merically equivalent to the overall efficiency of the Power Oscillator. Eqs. (3.10), (3.11)and (3.14) can now be used to determine transistor sizing and bias currents as describedby Fig. 3.12. However, a target Pd ,si ng le has not yet been derived as Pd ,si ng le dependson G and PRL,si ng le (Eq. (3.11)). In this case G is estimated in the best possible scenarioconsidering Fig. 3.6b, starting at 5dB .Design process is represented in the form of a flow chart in Fig. 3.21

Input requirements

Pout = 10dBm

VDD = 750mV

Estimate Gdev

CalculatePd ,si ng le → Pr equi r ed

Optimium RL

≈ 8Pr equi r ed

(2VDD −Vk )2 ≈ 40Ω

Bias Current

≈ 12

2VDD−VkRL

≈ 24m A

Sizing

≈ Ibi asJd ,opt

≈ 72µm = 1µm ×18×4

Load pull simulations

Figure 3.21: Flowchart depicting the power oscillator design procedure

Load-pull simulations results for a single device PA sized and biased as per Fig. 3.21is shown in Fig. 3.22. An optimum impedance of ZL,osc−opt = 12.12+ j 14.62Ω (which isrepresented by ≈ 29.7Ω||50pH @78.5G H z) is chosen with the indicated performance.

3.5.2. POWER OSCILLATOR BIASING

The capacitor coupled, NMOS-only oscillator is typically biased with a voltage (may befixed with a diode-connected device) at the gate using resistors and coupling capacitors.Such a bias scheme may cause issues as explained below.

Fig. 3.23 shows the gate of NMOS device under such a bias wherein the drain voltagefrom previous device behaves a voltage source. With this simplified model, vg is given

3


Figure 3.22: Load-pull contours for single ended transistor (72µm/50nm) used in the oscillator core,simulated at 78.5G H z

by:

vg = vs

sCc

s(Cc +Cg )+ 1Rb

+ 1Rg

(3.15)

Let, β= vg

vs(3.16)

Then, β= sCc

s(Cc +Cg )+ 1Rb

+ 1Rg

(3.17)

|β| = ωCc(ω2(Cc +Cg )2 +

(1

Rb+ 1

Rg

)2)1/2

(3.18)

Here β is the voltage feedback factor from drain to gate of the NMOS which must besuch that the small signal loop gain → 1. As the voltage gain at mm-Wave frequencies islow, it is required that β≈ 1. From Eq. (3.18):

ω2C 2c

(|β|)2 =ω2(Cc +Cg )2 +(

1

Rb+ 1

Rg

)2


3

43

Cc

Load+Drain ofprevious NMOS

Load+Gate

Rb

Cc Cc

Rb CgRg

Vs

Vg

Gate Model

Figure 3.23: Resistor bias schematic at the gate

Mathematically, for Rb and Rg > 0 (1

Rb+ 1

Rg

)2

> 0 (3.19)

∴ω2(Cc +Cg )2 < ω2C 2c

(|β|)2

Or, |β| < Cc

Cc +Cg(3.20)

Eq. (3.20) simply represents the voltage division between Cc and Cg that limit the feed-back factor. Owing to the device size of 72µm, Cg ≈ 96 f F , Cc → 1pF for high β. Self-resonance in comparison to the operating frequency for large Cc then becomes an issueand forces consideration of alternative topologies.

It is required that the impedance presented at the drain be ≈ ZL,osc−opt in order toachieve the desired performance. To transform the gate impedance, it is desirable totune-out Cg , which would deliver the following advantages:

• Feedback factor not restricted due to voltage division between Cc and Cg

• Capacitance seen by the load inductor (oscillator inductor) is reduced, thus allow-ing the use of larger inductors with lower losses

• Gate impedance can be transformed using a shunt inductor and series capacitorto achieve optimum performance.

Fig. 3.24 shows the circuit biased using a shunt inductor. Voltage transfer can thus,be analyzed as before to yield:

vg = vs

sCc

s(Cc +Cg )+ 1sLb

+ 1Rg

|β| = ωCc√(

ω(Cc +Cg )− 1ωLb

)2 +(

1Rg

)2

Or,

(ωCc

|β|)2

=(ω(Cc +Cg )− 1

ωLb

)2

+(

1

Rg

)2

(3.21)

3


Cc

Load+Drain ofprevious NMOS

Load+Gate

Lb

Cc Cc

Lb CgRg

Vs

Vg

Gate Model

Figure 3.24: Inductor bias schematic at the gate

Desired values of Cc and Lb may now be obtained from Eq. (3.21), by noticing that math-ematically, for any Lb , Cg , Cc and ω in a set of real-positive numbers,(

ωCc

|β|)2

>(

1

Rg

)2

For a target |β|,

Cc > |β|ωRg

(3.22)

Eq. (3.22) hints at the minimum value of Cc required to satisfy the transfer for a given|β|. It is interesting to note that Eq. (3.22) relates to the cut-off frequency of the high-passfilter formed by Cc and Rg . With a large Cc this cut-off is expected to be low, therebyincreasing the voltage across Rg and |β|. Furthermore, it is to be noted that by biasingthe device with Lb , the minimum value of Cc no longer depends on Cg as was the casewhen biased with Rb . To compute the value of Cg consider the cut-off frequency of theHPF ωHPF ≈ 0.1ωoper ati ng . Lower the value of ωHPF chosen, greater is the value of Cc

required for a given Rg . The value of Lb may now be determined as:

Lb,mi n = 1

ω2Cg(3.23)

From Fig. 3.20 it is clear that each NMOS device, along with PRL,si ng le behaves as a loadto the other device. With the required load power and maximum voltage swing known,RL,si ng le is determined using Eq. (3.12). With the approximate values of Cc and Lb,mi n

computed above, a π-matching network can now be designed as shown in Fig. 3.25b.Power out from the drain reference plane is then expected to be distributed appropri-ately, between PRL,si ng le and gate of the following NMOS device.

Impedances are expected to be symmetric thereby allowing the cross-coupled NMOS-only oscillator to be represented as shown in Fig. 3.26.

3.5.3. DESIGN OF THE INJECTORSDesign of injector device can begin once appropriate impedance levels and output powerare known. The injector devices are necessary to source/sink appropriate amount ofcurrent to/from the tank, for locking the oscillator at the frequency of injection. Adler’s


3

45

ZCG-source≈3.076-j20.74

Gate Bias Inductor

Coupling Capacitor

Load Inductor

Load Resistor

Zpads≈12.12+j14.62

(a) Smith Chart

Cc≈107fF

Lbosc,s≈35.6pH

Losc,s≈65pH

RL,s≈45

Ztran,gate≈3.076-j20.74Ztran,drain≈12.12+j14.62

From DrainTo Gate

Optimum resistive loadobtained from Smith Chart

(b) Schematic

Figure 3.25: Design of matching network between gate and drain of the cross-coupled pair. The Smith Chartand corresponding the schematic is shown

equation given by Eq. (2.11) is used to determine the amount of current through the in-jectors that is needed for the required bandwidth, given a f0 and QL . To estimate QL ,consider a loss-less tank where,

QL,max = RL

√Ct ank

Lt ank(3.24)

RL and Lt ank are obtained from Fig. 3.25b where the equivalent tank capacitance of thetank, Ct ank may be computed as:

Ct ank = 1

ω2oper ati ng Lt ank

For this thesis QL,max ≈ 2.05~2.5 which is attributed to relatively lower value of RL . Incontrast to oscillator designs, the low value of QL proves beneficial since Ii n j may belowered for a given ∆ fL . Once Ii n j is determined, injector devices are designed usingFig. 3.12 as shown in Fig. 3.28. Injector bias currents in this work are kept as low aspossible for efficiency considerations. Injectors are biased at Ji n j ≈ 0.17m A/µm insteadof Jopt from Fig. 3.2. This is acceptable since gain is primarily provided by the poweroscillator.As seen in Fig. 3.28, Iosc /Ii n j = somethi ng . Ii n j is obtained by amplifying the voltage atgates of the injector. As Ii n j is small compared to Iosc , the size of the injectors can alsobe designed significantly small, which reduces power dissipation by the injector devicesthemselves. In contrast to traditional PAs, the power gain obtained by using a single ILPAstage can be as high as 10dB to 13dB .

Injector are the inputs of the PA and therefore must be matched to a driver stage oran external source. Fig. 3.29b shows the impedance looking into the PA from 70G H z

3


1m⨯18⨯450nm

1m⨯18⨯450nm

Cc≈107fF

Losc≈130pH

Lbosc≈71.2pH

VDD

VG,Osc

Cc≈107fF

To Inter-MatchingStage

Figure 3.26: Schematic of Power Oscillator

Cc

VG,Osc

Cc

ZL

Injector Devices

Figure 3.27: Common ZL between injector devices and power oscillator

to 90G H z. In-band (76G H z - 81G H z) it is observed that the input impedance changesdrastically due to finite isolation offered by the MOSFET. Fig. 3.7b confirms that Um ≈−10dB owing to the chosen device size. To improve isolation, RF designers prefer theuse of cascode devices, however, utilization of reduced voltage for reliability does notpermit the use of cascode structures. In order to mitigate the effects of poor isolation,neutralizing capacitors (neu-caps), forming a feedback between the gate and drain areused in this work. The value of the neu-caps are estimated by extracting Cg d in a DCsimulation while varying N f as shown in Fig. 3.29a. The required value can then be read-off as Cg d =Cneu ≈ 5.4 f F for the required transistor configuration. Fig. 3.29b shows thevariation of input impedance across frequency for the neutralized injector stage.


3

47

Estimate QL of thetank using Eq. (3.24)

QL ≈ 2~2.5

Calculate Ii n j

For the requiredbandwidth Eq. (2.11)

Ii n j ≈ 8m A

VDD of oscillator

Calculate

WT = Ii n j ,dc

Ji n j≈ 16µm

Circuit Re-TuneReduce size of power

oscillator load inductor tore-tune center frequency

Tune for performance

Figure 3.28: Flowchart showing design of injector devices

0 5 10 15 20 25Nf

0

2

4

6

8

10

12

Capa

cita

nce(

fF)

Wfinger=1µm Lch=50nm

16.0

16.0,5.38fF

Cgd

Cgs

(a) Cg d vs N f

0 50 100 150 200 250 300Frequqncy(GHz)

700

600

500

400

300

200

100

0

100

Re(Z

in),I

m(Z

in)

Re(Zin) without neutralizing capIm(Zin) without neutralizing capRe(Zin) with neutralizing capIm(Zin) with neutralizing cap

(b) Zi n vs frequency

Figure 3.29: Variation of Cg d and Cg s with N f and variation of Zi n with frequency, with and withoutneutralizing capacitors

Zop-input≈2.8-j15.3

Zosc-opt≈30.77+j41.96

Gate Bias Inductor

Diff. Tline

Coupling Cap

Osc Load Inductor

(a) Smith Chart

Vop,bias

≈77fF

≈77fF

≈55.4pH

Z0≈103, =5.870°

≈31pH

VDD

Osc loadInductor

Output StageBiasing Inductor

Zop-input ≈2.18-j15.3Zosc-opt ≈30.77+j41.96

(b) Schematic

Figure 3.30: Interstage matching using Smith Chart that shows impedance transformation and thecorresponding schematic of π-matching network

3


3.5.4. DESIGN OF INTERSTAGE MATCHING NETWORK

The optimum output impedance of the ILPA pre-driver and the input impedance of out-put stage are at drastically different levels, where, Zi n,op−st ag e is highly capacitive whileZout ,I LPA is purely real. Moreover, the output stage is biased with its own diode con-nected device, which fixes an optimum gate bias voltage based at Jopt . Therefore, it isrequired to isolate DC bias voltages while AC coupling the output stage requiring theuse of either a transformer or coupling capacitors. Non-availability of transformers inthe Global Foundry PDK encourages the use of coupling capacitors instead, which isadopted by in this thesis. The output stage is DC biased using a center-tapped inductorthat is designed to tune-out any input capacitance.

A π-matching network is now designed by using coupling capacitors and DC biasinductors as shown in Fig. 3.30b. A differential transmission line of length ≈ 34µm andZ0 ≈ 80Ω is used to avoid coupling between the two inductors by introducing physicaldistance.

3.5.5. LAYOUT OF ILPA PREDRIVER

To Output Stage

Vosc,bias

Vinj,bias VDD Vop,bias

Interstage MatchOscillator CoreInjectors

From Input Stage

≈77fF

≈77fF

Z0≈103 =5.87°

≈31pH

≈55.4pH

≈107fF

≈107fF

≈71.2pH≈25k

≈25k

≈5fF

≈5fF

Injectors=1m×16×1 Injectors=1m×18×4

WT = 1m×6×1Lch = 50nm

Ibias≈1mA

RC bias filter

Vinj,bias

WT = 1m×3×1Lch = 50nm

Ibias≈1mA

RC bias filter

Vosc,bias

Figure 3.31: Schematic of the ILPA predriver stage

Fig. 3.31 shows the complete schematic of the power oscillator and injectors includ-ing diode-connected biasing NMOS devices. The layout of the ILPA begins with an anal-ysis of the required track width for the current drawn.

As shown in Fig. 3.32, the core oscillator transistors are placed symmetrically withcoupling capacitors between them similar to the PA layout in [2]. Injector devices areplaced to maintain a straight signal path to the output stage. As the oscillator and injec-tor devices, do not necessarily require to be matched, the oscillator core is placed orthog-onal to the signal path. Ground being the most important net in this layout, comprisesof M2-FA stack, each with a width of 4.5µm in order to minimize ground resistance. The


3

49

Figure 3.32: Oscillator and injector layout

net is placed symmetrically in-between differential outputs that are carried on FB. VDD

and ground are de-coupled locally and M1 is used as a ground plane similar to the outputstage. Fig. 3.33 shows the ILPA along with the interstage matching network.

Figure 3.33: ILPA with interstage matching

3


3.6. DESIGN OF COMMON-GATE INPUT MATCHAs seen from Fig. 3.29b, the input impedance Zi n,In j ≈ 26.8− j 170.6Ω, which at 78.5G H zmay be modeled as a parallel combination of Ri n,i n j ≈ 1.1kΩ and Ci n,i n j ≈ 11.5 f F . Ow-ing to high-input impedance, there is a need to use a Common-Gate (CG) matching stage,as explained in Section 2.5.3, to match with an external 100Ω source for the purposes ofa test chip.

3.6.1. CG STAGE SIZING AND BIASINGThe common-gate stage must be designed to match with an external differential 100Ωsource or equivalently, 50Ω single-ended. The input impedance at low frequencies for acommon-gate NMOS device can be approximated as 1/gm . Therefore, it is required that,

1

gm≈ 50Ω

Or, gm ≈ 20mS

The device is biased in saturation to ensure high voltage gain by fixing VGS =VDD . With

0 200 400 600 800 1000

WT/Lch ratio

5

10

15

20

25

30

35

40

gm,CG(m

S)

20.0mS Lch=40nm

Lch=50nm

Lch=60nm

Lch=90nm

Lch=100nm

Lch=140nm

Figure 3.34: gm vs WT /Lch for varying Lch

this biasing scheme, the device may be approximated by the square law model such thatgm ∝WT /Lch . Fig. 3.34 shows the variation of gm with WT /Lch .

As Re(Zi n,i n j ) ≈ 1.1kΩ, a high output impedance for the CG input stage is desirable.With this in mind, a channel length of 100nm is chosen. With Lch,CG = 100nm, WT /Lch ≈300 for gm ≈ 20mS from Fig. 3.34 and therefore, WT = 30µm = 1µ×30×1.

A load inductor is required to bias at the drain while AC coupling capacitors areneeded to isolate DC voltages between the CG input stage and the ILPA. The optimumimpedance is obtained using a simple load-pull simulation that focuses on maximiz-ing the power gain of the stage as shown in Fig. 3.35. A simple L-matching network isnow designed as shown in Fig. 3.36a. As seen, the optimum impedance is significantlyinductive and therefore does not permit a perfect match at these frequencies. Further,comparing Zi n,i n j and Zopt ,CG , losses of the load inductor are expected to dominate.

3.6. DESIGN OF COMMON-GATE INPUT MATCH

3

51

8 18 31 50 80 140

300

-150j

-80j-50j

-31j

-16j

0

16j

31j50j

80j

150j

8 18 31 50 80 140

300

Const power contours (dBm)Const PAE contours (%)Const Gain contours (dB)

Pout >5dBmPAE≈8%Gain≈0.5dB

(36.8+68.35j)

Figure 3.35: Results of load-pull simulation on CG-stage devices

ZL,inj≈26.8-j171

Zs,drain≈73.6+j136.7

Diff. Tline

AC coupling Caps

Load Inductor

(a) Smith Chart

≈202fF

≈202fF,

≈94.2pH

Drain of

To injectors

CG Stage

VDD

ZL,inj≈26.8-j171

Zs,drain≈73.6+j136.7

(b) Schematic

Figure 3.36: CG output matching on Smith Chart that shows impedance transformation and thecorresponding schematic of the output matching network

An input matching network is designed using the impedance level of the PAD fromFig. 3.15a. An inductor is used to bias at the source, while AC coupling capacitors isolateany external DC. The L-matching network is design as shown in Fig. 3.37a along with aschematic in Fig. 3.37b.

3


ZCG-source≈99.62-j36

Load Inductor

Diff. Tline

AC coupling Caps

Zpads≈51.8-j9.3

(a) Smith Chart

≈59.2fF

≈59.2fF

≈228pH

To Input PADs

Source ofCG StageZCG-source≈99.62-j36

Zpads≈51.8-j9.3

(b) Schematic

Figure 3.37: CG input matching on Smith Chart that shows impedance transformation and the correspondingschematic of the input matching network

3.6.2. LAYOUTThe complete schematic of the CG input matching network is shown in Fig. 3.38 whileFig. 3.40 shows the associated layout.

VDD

≈202fF

≈202fF

≈94.2pH

To injectors

WT=30m=1m×30×1Lch=100nm

WT=30m=1m×30×1Lch=100nm

Idc ≈ 5mA

Idc ≈ 5mA

≈300

≈59.2fF

≈59.2fF

≈228pH

To Input PADs

Idc ≈ 5mA

Idc ≈ 5mA

ZL≈51.8-j9.3 ZL≈26.8-j171

Figure 3.38: Complete schematic of the CG input matching network

Addition of small capacitance at the input aids in matching with the shunt inductorand therefore, the gates of the CG devices are connected via FA, which increase inputcapacitance, even though no DC current flows through this route. Up to this point inlayout, M2 carries VDD through a resistor and diode (shows in Fig. 3.40) that are placedas a precautionary measure to protect gates directly connected supply. A high resistance,unsilicaded resistor has been used as no DC current is expected in this path. Ground isdrawn from the center-tap of the input matching inductor and is decoupled to VDD viaM1. The total resistance in the decoupling path is expected to be around 300mΩ as

3.6. DESIGN OF COMMON-GATE INPUT MATCH

3

53

multiple M1 lines have been used.

Figure 3.39: Layout of CG input stage devices

Figure 3.40: Layout of CG input stage

3


3.7. FULL CHIP INTEGRATION AND PLACEMENT

3.7.1. PAD PLANNINGThe pad ring is completely developed and provided by NXP Semiconductors and hasbeen proven on multiple test chips before this thesis work. Fig. 3.41 shows the pad ringwith a differential input and different output RF pads on the left and right respectively.Top and bottom of the ring consist of 6 pads each out of which, 2 are ground pads. Theothers may be used for supply or biasing. Each of the top and bottom pads also has ESDprotection that requires a bias.

In this work, all top pads have been used as core supply, while bottom pads are usedfor bias. All PA stages require a single VDD = 0.75V , however, in order to measure indi-vidual currents and maintain finer control over individual supplies, each stage has beenassigned a VDD pad as shown in Fig. 3.41. VDD,1p8 is used to bias ESD diodes on the top.Pads at the bottom are used to supply bias currents and voltage to individual currentmirrors for the output, oscillator and injectors that allow fine control during testing.

GNDVDD,opVDD,osc

Sin+

VDD,1p8

Ibias,opIbias,opIbias,opVDD,1p8

GND

GND

GND

GND

GND

GND

GND

GNDGND

Sin-

Sout+

Sout-

VDD,CG

1000m

850m

804.98m

763.98m

659.96m

599.2m

Figure 3.41: PAD ring used for the test chip provided by NXP Semiconductors

3.7.2. DESIGN OF BIASING BLOCKConstant current biasing has been adopted for all core transistors and therefore, requirean external current source. In order to match core transistors, thin gate-oxide SLVTNMOS devices are used as diode connected components in the mirror with a potentialrisk of breakdown as their gate would directly be connected to a bias pad. To mitigatethis possible risk, a simple current mirror block using thick gate-oxide devices has beendesigned. Independent current mirrors, each with a mirroring ratio of 1:2, allow fine con-trol over the gate bias voltage of the output stage, power oscillator and injectors as seen


3

55

Iinj,ext ≈ 500A

VDD,bias = 1.8V

WT = 40mLch = 500nm

WT = 52m

Lch = 500nm

WT = 104m

270

External PAD

Iinj≈1mA

Iosc,ext ≈ 500A

VDD,bias = 1.8V

WT = 40mLch = 500nm

WT = 52m

Lch = 500nm

WT = 104m

270

External PAD

Iosc≈1mA

Iop,ext ≈ 500A

VDD,bias = 1.8V

WT = 40mLch = 500nm

WT = 52m

Lch = 500nm

WT = 104m

270

External PAD

Iop≈1mA

Figure 3.42: Schematic of the bias block with independent output currents of 1m A each

in Fig. 3.42. The bias block uses a VDD,bi as = 1.8V , each with an input of ≈ 500µA. Fur-thermore, a poly-resistor of ≈ 300Ω in series with the input is used to limit the amount ofcurrent in case of an ESD event. Output currents ≈ 1m A are independent of each otherand feed into thin gate-oxide SLVT devices.

3.7.3. DECAP DESIGN

Decoupling Capacitors (decaps), placed between supply and ground, provide a low impedancepath to high frequency signals and therefore, aid in maintaining a constant DC supplyvoltage. Decoupling is preferably done close to high-frequency circuits, using capaci-tors with a high-quality factor, in order to avoid any AC losses due to long current returnpaths. However, high-quality factor capacitors typically offer lower capacitance for thearea that they occupy. Chip real estate is better utilized when large, low-quality factor ca-pacitors are included in the design. The large capacitance damps low frequency signalsmore effectively and aids in better circuit stability. Therefore, in this thesis, a combina-tion of both high-Q and low-Q capacitors has been used. High-Q decaps are placed closeto high-frequency circuits while low-Q decaps are placed further away towards the pads.

HIGH Q DECAPS

High-Q decaps are designed as metal-fringe capacitors. A 10 f F all metal-fringe cap isused as a base that is connected in a regular arrangement to obtain higher capacitance asshown in Fig. 3.43. Unit decaps are designed such their regular interconnection behavesas a plane for both VDD and ground. Metal added around the decaps is intended to carryVDD on FB and ground on a M2-FA stack.

LOW Q DECAPS

Low-Q decaps are designed using a unit 2pF , 2.5V thick gate-oxide ncap available inthe design library, with metal-interconnect on top. The grid structure of the metal in-terconnect, shown in Fig. 3.44, behaves as a voltage plane with reduced resistance whenconnected in a regular structure. The low-Q decaps are intended to seamlessly connectwith the high-Q decaps such that ground is carried on M2-FA stack while VDD is carriedon FA-LB stack.

3


(a) Top view. Total capacitance ≈ 40 f F (b) Isometric view

Figure 3.43: Layout of high-Q decaps

(a) Core poly-capacitor≈ 2pF (b) Metal stack added on top of poly-capacitor

Figure 3.44: Layout of Low-Q decaps

3.7.4. FULL CHIP LAYOUTFig. 3.45 shows the full-chip schematic, while Fig. 3.46 shows the corresponding layout.Output stage is placed close to the output pads followed by the ILPA stage and the CGinput matching stage. Long differential transmission lines are used to interconnect eachstage and the input and output pads. Biasing block is placed at the bottom to feed in-dividual appropriately. RC circuits are placed at the gates of diode-connected NMOSdevices to filter any noise that may couple to supply. Regular decap placement createsnearly constant voltage planes with minimal resistance to pads. A dummy metal filling isperformed on this layout by NXP Semiconductors, in order to meet density design rulesrequirements, prior to tape-out.


3

57

V osc

,bia

s

V inj

,bia

sV D

DV o

p,bi

as

Inte

rsta

ge M

atch

Osc

illato

r Cor

eIn

ject

ors

≈77

fF

≈77

fF

Z 0≈

103

=

5.87

°

≈31

pH

≈55

.4pH

≈10

7fF ≈

107f

F

≈71

.2pH

≈25

k

≈25

k

≈5f

F

≈5f

F

Inje

ctor

s=1

m×

16×

1 / 5

0nm

Osc

illat

or c

ore=

1m

×18

×4

/ 50n

m

V DD

Z 0≈

79.6,

=18

.8°

≈55

.8pH

≈43

.8fF

Out

put D

evic

es=

1m

×30

×6

/ 50n

m

Out

put S

tage

and

Mat

ch

V DD

≈202

fF

≈202

fF

≈94.

2pH

≈300

≈59.

2fF

≈59.

2fF

≈228

pH

To In

put P

ADs

Z PAD

s≈51

.8-j9

.3

Inje

ctor

s=1

m×

30×

1 / 1

00nm

CG

Inpu

t Mat

chin

g St

age

To O

utpu

t PAD

s

Z PAD

s≈51

.8-j9

.3

WT =

1m

×6×1

L ch =

50n

m

RC

bia

s fil

ter

V inj,b

ias

I inj,e

xt ≈

500A

V DD

,bia

s = 1

.8V

WT =

40

mL c

h = 5

00nm

WT =

52

m

L ch =

500n

m

WT =

104m

270Ex

tern

al P

AD

WT =

1m

×3×1

L ch =

50n

m

RC

bia

s fil

ter

V osc,

bias

I osc,

ext ≈

500A

V DD

,bia

s = 1

.8V

WT =

40

mL c

h = 5

00nm

WT =

52

m

L ch =

500

nm

WT =

104m

270Ex

tern

al P

AD

WT =

1m

×3×1

L ch =

50n

m

RC

bia

s fil

ter

V op,b

ias

I op,e

xt ≈

500A

V DD

,bia

s = 1

.8V

WT =

40

mL c

h = 5

00nm

WT

= 52m

L ch =

500

nm

WT =

104m

270Ex

tern

al P

AD

Bias

ing

Bloc

k

Figure 3.45: Full-chip Schematic of the Power Amplifier

3


Figure 3.46: Complete layout of test chip post fill

4SIMULATION RESULTS

4.1. INTRODUCTIONThis chapter depicts simulations results for the PA shown in Fig. 3.46, using CadenceADE-XL. Device models (both active and passive) have been provided by NXP Semicon-ductors, as programmable cells (PCELLs), that aid in improving simulation time. Lay-out parasitics have been analyzed by extracting parasitic resistors and capacitors (RC).Supply line inductances have been simulated by adding ideal inductances on the test-bench. This chapter is outlined as Section 4.2 shows the chip startup simulations thatis followed by Section 4.3, which depicts simulation results corresponding to individ-ual stages in the PA. Section 4.4 shows full-chip simulations including the PAD ring, andfinally, Section 4.5 shows lifetime simulations.

100100

500A 500A 500A

1.8V

1.8V

0.75V

100pH

100pH

vdd

_750

m_C

G

vdd

_1p8

_ES

D_t

op

vdd

_750

m_O

SC

vdd

_750

m_O

P

SIPLUS

SIMINUS

SOPLUS

SOMINUS

vdd

_1p8

IInjM

ain

IOsc

Mai

n

IOpM

ain

vss

ILPA

VDDcore

VDD1p8

VDD,bias

Diff. Load

Diff. Source

Figure 4.1: Generic full-chip testbench

59

4

60 4. SIMULATION RESULTS

4.2. SYSTEM STARTUP SIMULATIONSThis section depicts the startup behavior of the PA. Fig. 4.1 shows a generic testbenchused to collect results. The gate voltage of the diode-connected device may be stuckto ground potential at startup. It is, therefore, required to ensure appropriate bias volt-ages at these nodes. Fig. 4.2 shows the transient variation of bias voltages and currentat startup. VDD of every stage is turned on, followed by the bias voltage, VDD,1p8. Exter-nal bias currents are then individually forced to toggle between 0A and 500µA. As seenVop,bi as , Vosc,bi as and Vi n j ,bi as all follow this variation. Fig. 4.2, hence, confirms thatbias voltages may be set appropriately using external references.

Figure 4.2: Time domain waveforms of showing bias voltages and currents

The oscillation control of the PA is now tested by varying Iosc,bi as while maintainingIi n j ,bi as and Iop,bi as at 500µA. The oscillation build-up is as shown in Fig. 4.3. As seen,oscillation startup is requires < 0.75ns from when Vosc,bi as raises to ≈ 800mV . Duringsimulation, Iosc,bi as is ramped up with a slope ≈ 2ns. Vosc,bi as has a long settling timeowing the large amount of decap placed at the gate of the diode-connected device.

4.3. STAGE WISE SIMULATIONSThis section shows stage-wise simulation results starting from the output stage. Eachstage has been studied for its power capability, gain, efficiency and passive matching

4.3. STAGE WISE SIMULATIONS

4

61

Figure 4.3: Time domain waveforms of the oscillator during startup

losses, mainly using a harmonic-balance simulator. Individual test schematics similarto Fig. 4.1 have been developed to aid in studying each stage. A primary problem whiledeveloping such schematics is the accuracy of modeling the right impedance levels ateach interface. During design, similar schematics were developed wherein, impedanceswere modeled as simple lumped RLC circuits. However, during verification, an appro-priate impedance level has been maintained by using succeeding stages as a load.

4.3.1. OUTPUT STAGE SIMULATIONS

The output stage has been designed for Pout ≈ 15dBm with a Gai n ≈ 5dB and therefore,Pi n ≈ 10dBm. Fig. 4.4 shows the variation of output power with frequency at:

• the drain reference plane

• input plane of the output PADs (output of the matching network)

• load reference plane

As seen, the power output at the drain reference plane is ≈ 14.6dBm while the outputof the matching network is ≈ 13.6dBm. Unfortunately, with the PAD losses as seen inFig. 3.15b, the output power into the load is ≈ 13dBm. It should be noted that Fig. 4.4shows Pi n,op ≈ 10dBm, which is highly idealistic as this drive power must be providedby the power oscillator and the interstage match.

4


70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90Frequency(GHz)

9

10

11

12

13

14

15

16

Powe

r(dBm

)

Drain referenceOutput Matching

Load referencePower Input

Figure 4.4: Output power at various reference planes

70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90Frequency(GHz)

10

20

30

40

50

60

Effic

ienc

y(%

)

ηd-Drainηd-Output matchηd-Load

PAE-DrainPAE-Output matchPAE-Load

Figure 4.5: Efficiency and Power-Added Efficiency at various reference planes

Fig. 4.5 shows the variation of efficiency and PAE measured at the drain plane andthe load-plane. As seen ηdr ai n > 40% while PAEdr ai n > 25%. Owing to matching andPAD losses, the maximum efficiency of ηmax,load ≈ 30%. The passive matching networkhas a total loss of ≈ 0.9dB that reduces the output power and PAE significantly, whencompared to ideal passives. Fig. 4.6 shows power gain simulated at various reference


4

63

planes. As seen, the output devices have a gain ≈ 4.5dB in frequency band of interest.The gain simulated at the load however, drops significantly to (4.5−0.9−0.6) ≈ 3dB .

70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90Frequency(GHz)

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5Po

wer G

ain(

dB)

G-DrainG-Output MatchG-Load

Figure 4.6: Power gain simulated at various reference planes

4.3.2. ILPA AND MATCHING NETWORK SIMULATIONSFig. 4.7a shows the waveform for the free running power oscillator at start-up. This wave-form has been simulated by disconnecting injector inputs and applying appropriate bi-ases. As seen from Fig. 4.7b (harmonic-balance simulation), the power oscillator has a

1.000 1.025 1.050 1.075 1.100 1.125 1.150 1.175 1.200Time(ns)

1.5

1.0

0.5

0.0

0.5

1.0

1.5

Volta

ge(V

)

Diff. Oscillator outputDiff. Input to output stage

(a) Time domain waveforms

0 200 400 600 800 1000Frequency(GHz)

160

140

120

100

80

60

40

20

0

20

Powe

r(dBm

)

78.34G

(b) Frequency domain spectrum

Figure 4.7: Time domain and corresponding frequency domain spectrum of the free running oscillator

center frequency ≈ 78.34G H z considering layout parasitics. The matching network con-nected to the output stage behaves as the load to ILPA that includes the oscillator’s load

4


inductor. Therefore, the following reference planes have been used to analyze propertiesof the ILPA, which have been visually represented in Fig. 4.8

• Drain reference of the ILPA core.

• Load inductor reference plan making up the oscillator tank.

• Gate input reference plan of the output stage.

To Output Stage

Vosc,bias

VDD Vop,bias

Interstage MatchOscillator Core

Injectors

Osc Drain Osc Out Interstage Matching Out

Figure 4.8: Reference planes used to study the oscillator

Fig. 4.9a shows the spectrum of the ILPA at each of these reference planes along with theDC power consumed. As seen from these spectra, output power is significantly lowerthan expected as the injector devices offer an impedance to ground and act to absorbsignificant amount of power while there is no injected signal at their gates.

0 200 400 600 800 1000Frequency(GHz)

150

125

100

75

50

25

0

25

Powe

r(dBm

)

8.3dBm Pout-Osc drainPout-Osc (including osc ind)Pout-inter-matching network

(a) Free running oscillator

0 200 400 600 800 1000Frequency(GHz)

175

150

125

100

75

50

25

0

25

Powe

r(dBm

)

78.5GHz,9.62dBmPout-Osc drainPout-Osc (including osc ind)Pout-inter-matching network

(b) ILPA under fundamental injection

Figure 4.9: Spectrum of free running oscillator and spectrum of ILPA under injection at fundamental atvarious reference planes


4

65

In contrast to Fig. 4.9a, Fig. 4.9b shows higher output power when an input powerof ≈ −2.5dBm is applied to the gate of injector devices. As can be seen from Fig. 4.10,injection at the natural oscillating frequency produces high output power, owing to thein-phase addition of Posc and Pi n j . Fig. 3.31 has been designed with a target output of

70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90Frequency(GHz)

6

4

2

0

2

4

6

8

10

Powe

r at r

efer

ence

pla

nes(

dBm

)

PDrainPOscPinterstageMatchPinj

Figure 4.10: Variation of oscillator power at various reference planes

10dBm. Fig. 4.10 shows the variation of output power of the oscillator stage with fre-quency, which is obtained by sweeping the input signal at the injectors gate. HarmonicBalance simulation results for every input frequency point is collected and processed toobtain the variation in Fig. 4.10. As seen, the power simulated at the oscillator’s outputreference plane is ≈ 8.5dBm peak and > 8dBm across the band, while the power outof the drain reference plane is ≈ 10.3dBm peak and > 9.5dBm across the band. Fur-ther, it is also observed that the interstage matching network has a loss ≈ 1.5dB~1.7dB .The bias inductor at the gate of the output stage, predominantly contributes to this loss.The quality factor of the gate inductor used in inter-stage matching is ≈ 18.8, and fromEq. (2.3), Rp,L ≈ 290Ω. Since the gate impedance, Rp,g ate ≈ 82Ω, relatively higher lossis expected due to the insertion of this inductor (as detailed in Fig. 2.3). Fig. 4.11 showsthe variation of locking range with Pi n that obtained by simulating output power at thedrain reference plane using harmonic balance. The fundamental of harmonic balancesimulator is set to the input frequency and therefore, Fig. 4.11 shows a steep drop in out-put power outside the band of interest. This indicates that the ILPA is out of its lockingrange and hence, only contains low power frequency components contributed by the in-jectors. Fig. 4.12a shows time domain waveforms outside the PA locking range, wherein,the amplitude of output voltage waveform is modulated with a modulating frequency offm = | fosc, f und − fi nput |. Additional frequency tones around fosc, f und can even be seen

4


Increasing Pinj

Figure 4.11: Power at the drain reference with varying Pi n j

in the DFT spectrum shown in Fig. 4.12b.

5.0 5.2 5.4 5.6 5.8 6.0Time(ns)

1.5

1.0

0.5

0.0

0.5

1.0

1.5

V osc

(V)

(a) Time domain waveforms

0 50 100 150 200 250 300 350Frequency(GHz)

140

120

100

80

60

40

20

0

20

V osc

(dB)

(b) DFT spectrum

Figure 4.12: Time domain waveforms and DFT spectrum of the oscillator output voltage under fi n j = 84G H z

In contrast to Fig. 4.12, Fig. 4.13 represents the time domain voltage waveform andthe corresponding DFT spectrum when the ILPA is locked. Under a locked state, theamplitude of vosc remains constant and the oscillator produces a close-to-perfect sinu-soid (considering high-order harmonic components). As seen from Figs. 4.13b, 4.13dand 4.13f, the 3r d-harmonic of vout under lock is < −30dB across the locking range.Furthermore, Fig. 4.14 shows the time domain voltage waveforms and spectrum when


4

67

the ILPA is just at the edge of the locking range that resembles observations by in [22].

5.0 5.2 5.4 5.6 5.8 6.0Time(ns)

1.5

1.0

0.5

0.0

0.5

1.0

1.5

V osc

(V)

(a) Time domain waveforms under 78G H zinjection

0 50 100 150 200 250 300 350Frequency(GHz)

140

120

100

80

60

40

20

0

20

V osc

(dB)

(b) DFT spectrum under 78G H z injection

5.0 5.2 5.4 5.6 5.8 6.0Time(ns)

1.5

1.0

0.5

0.0

0.5

1.0

1.5

V osc

(V)

(c) Time domain waveforms under 76G H zinjection

0 50 100 150 200 250 300 350Frequency(GHz)

140

120

100

80

60

40

20

0

20V o

sc(d

B)

(d) DFT spectrum under 76G H z injection

5.0 5.2 5.4 5.6 5.8 6.0Time(ns)

1.00

0.75

0.50

0.25

0.00

0.25

0.50

0.75

1.00

V osc

(V)

(e) Time domain waveforms under 81G H zinjection

0 50 100 150 200 250 300 350Frequency(GHz)

140

120

100

80

60

40

20

0

20

V osc

(dB)

(f) DFT spectrum under 81G H z injection

Figure 4.13: Time domain waveforms and corresponding DFT spectrum showing locked nature of voscinband at 76G H z, 78G H z and 81G H z

4


5.0 5.2 5.4 5.6 5.8 6.0Time(ns)

1.5

1.0

0.5

0.0

0.5

1.0

1.5

V osc

(V)

(a) Time domain waveforms under 82G H zinjection

0 50 100 150 200 250 300 350Frequency(GHz)

120

100

80

60

40

20

0

20

V osc

(dB)

(b) DFT spectrum under 82G H z injection

Figure 4.14: Time domain waveforms and corresponding DFT spectrum showing the ILPA at the edge of itslocking range

4.3.3. COMMON GATE INPUT STAGE SIMULATIONSThe input common gate stage has been designed to match the high impedance of theinjectors to a 100Ω input source for purposes of the test-chip. As discussed in Section 3.6,the 100Ω input source is transformed to an impedance Zcg ,i nput ≈ 51.8− j 9.3Ω, owingto input PADs. A single-port S-parameter simulation is performed to study this match asshown in Fig. 4.15a where, S11 is simulated at the input reference plane and the insertionloss is simulated between chip-input and input of the injectors. Fig. 4.15b shows thevariation of power at:

• input reference plane (expected to be 0dBm)

• power available at input of the CG stage

• power into the source of the CG devices

70 72 74 76 78 80 82 84 86 88 90Frequency(GHz)

20

15

10

5

0

5

10

15

|S11

|(dB)

and

Inse

rtion

Los

s(dB

)

78.5G,3.077dB

|S11| IL

(a) S11 and Insertion Loss of input stage CGstage

70 72 74 76 78 80 82 84 86 88 90Frequency(GHz)

2.5

2.0

1.5

1.0

0.5

0.0

0.5

Powe

r at v

ario

us re

fere

nce

plan

es(d

Bm) Pin - Pads

Pin - CG StagePin - Source of NMOS

(b) CG input power at various referenceplanes

4.4. FULL-CHIP SIMULATIONS

4

69

70 72 74 76 78 80 82 84 86 88 90Frequency(GHz)

16

14

12

10

8

6

4

2

0

2Po

wer a

t var

ious

refe

renc

e pl

anes

(dBm

)

Pout - DrainPout - Load InductorPout - CG stage

(c) CG output power at various referenceplanes

70 72 74 76 78 80 82 84 86 88 90Frequency(GHz)

10

5

0

5

10

Powe

r(dBm

)

Pout - CG OutputPDC - CG DC Power

CG Efficiency

0

2

4

6

8

10

12

14

Effic

ienc

y(%

)

(d) DC power and efficiency of CG stage

Figure 4.15: Common Gate input match simulation results

PADs and Inductor losses may be clearly observed in Fig. 4.15b as Fig. 4.15a shows a re-flection S11 < −10dB with S11,max ≈ −12dB at 81G H z. Similar to the interstage match,the shunt inductor at the source contributes significantly to losses of ≈ 1.5dB . At an in-put power level of 0dBm, the source of the CG stage receives ≈−1.6dBm to −2.25dBm,owing to losses from the PADs and the passive matching network.

Fig. 4.15c shows the variation of power at the drain reference plane and the inputof the injectors. While the output power at the drain is ≈ 1.2dBm the power into theinjectors is only −3.35dBm at 78.5G H z and therefore, the insertion loss of this matchingnetwork is > 4.4dB . The losses are attributed to the load inductors which has a QL ≈ 26.6and Rp ≈ 1.23kΩ. As mentioned in [2], the CG stage is expected to provide output powerequivalent to its own insertion loss.

4.4. FULL-CHIP SIMULATIONS

70 72 74 76 78 80 82 84 86 88 90Frequency(GHz)

15

10

5

0

5

10

15

20

25

Powe

r(dBm

)

Pout at Output MatchPinj Injector power

ηd at Output MatchPAE

0.0

2.5

5.0

7.5

10.0

12.5

15.0

17.5

20.0

22.5

Effic

ienc

y(%

)

(a) Power and efficiency variation

70 72 74 76 78 80 82 84 86 88 90Frequency(GHz)

2

4

6

8

10

12

14

16

18

Powe

r Gai

n(dB

) P

out,match/P

inj

(b) Power gain variation

Figure 4.16: Variation of performance parameters simulated between output matching network and input toinjectors

4


Full-chip simulation of the circuit shown in Fig. 3.45 have been performed, primarilyusing Cadence ADE-XL’s harmonic-balance simulator with a frequency sweep. Fig. 4.16

70 72 74 76 78 80 82 84 86 88 90Frequency(GHz)

10

5

0

5

10

15

20

Powe

r(dBm

)

Pout-Chip OutPin-Chip In

ηd-Chip OutPAE-Chip Out

0.0

2.5

5.0

7.5

10.0

12.5

15.0

17.5

20.0

Effic

ienc

y(%

)

(a) Power and efficiency variation

70 72 74 76 78 80 82 84 86 88 90Frequency(GHz)

10

5

0

5

10

15

PAD-

PAD

powe

r gai

n (d

B)

(b) Power gain variation

Figure 4.17: Variation of performance parameters when simulated between the PADs

shows the variation of output power, efficiency and PAE which frequency simulated be-tween the input of the injectors and the output matching network. As seen, output powerat the output of the matching network is ≈ 13dBm with an input power of −2dBm,therefore, displaying a gain of > 16dB , system efficiency ≈ 17.5% and system PAE ≈ 17%.

Fig. 4.17 shows the same performance parameters when simulated from pad-to-padincluding the CG input stage. As seen, output power is now reduced to ≈ 12.5dBm withan input power of ≈ 0dBm, therefore, displaying a gain of ≈ 12.5dB , system efficiency≈ 14% and system PAE ≈ 13.2%.

4.5. LIFETIME SIMULATIONSReliable working of the ILPA is verified by performing a full-chip life-time simulationfor varying VDD . A VDD ≈ 750mV is chosen to ensure a peak voltage ≤ 1.5V , detailedin Section 3.2.5. As seen in Fig. 4.18, increasing VDD improves the output power dueto increased voltage swing, but is detrimental to the ILPA’s lifetime. It is interesting tocompare the curves simulated for VDD = 1V and VDD = 1.1V , wherein, the output powerdegrades rapidly in the latter case for the technology used. The ILPA was designed tomaximize lifetime such that the output power drop after 12k hours of continuous workis < 0.5dB . Fig. 4.18 reveals that the system output power can be improved by increasingVDD to ≈ 0.85V while still meeting the required specification. Fig. 4.20 shows improve-ments in performance parameters for increasing VDD .

4.6. COMPARISON WITH OTHER PAS IN LITERATURETable 4.1 shows the performance of the designed ILPA with state-of-the-art PAs currentlypublished in literature. As seen, this work shows quite high PAE and gain for the auto-motive band along with sufficient output power with only 2-stages.

4.6. COMPARISON WITH OTHER PAS IN LITERATURE

4

71

100 101 102 103 104 105

Aged time(Hours)12.0

12.5

13.0

13.5

14.0

14.5

15.0

15.5

16.0

16.5

17.0

Oupu

t Pow

er (d

Bm)

12000.0Vdd = 0.75Vdd = 0.8Vdd = 0.85Vdd = 0.9Vdd = 0.95Vdd = 1.0Vdd = 1.1

Figure 4.18: Variation of output power (pad-to-pad) over time and VDD

70 72 74 76 78 80 82 84 86 88 90Input Frequency(GHz)

10

5

0

5

10

15

20

Outp

ut P

ower

(dBm

)

Vdd=0.75VVdd=0.9VVdd=1.0VVdd=1.1V

(a) Output Power Variation


14

12

10

8

6

4

2

Inje

cted

Pow

er(d

Bm)


(b) Injected Power Variation


0

2

4

6

8

10

12

14

16

18

Syst

em E

fficie

ncy(

%)


(a) Efficiency Variation


2

0

2

4

6

8

10

12

14

16

Syst

em P

AE(%

)


(b) PAE variation

Figure 4.20: Variation of performance parameters across frequency for various core VDD

4


Table 4.1: Comparison between various CMOS PA designs found in literature

Literature

PeakOutputPower(dBm)

PAE(%)

Gain(dB)

RelativeBW (%)

CenterFrequency

(GHz)Vdd(V) Technology

[6] 19.4 34.4 7.5 7.05 42.5 2.7CMOS SOI

45nm

[16] 9.6 13.6 29 3.72 53.7 1.2CMOS65nm

[17] 10.5 16.1 37.8 16.36 55 1CMOS65nm

[18] 13 36 25 8.62 58 1.2CMOS65nm

[7] 12.6 6.9 10 30 60 1CMOS90nm

[12] 22.6 6.3 22 11.66 60 1.2CMOS40nm

[8] 17 30.3 17 8.73 60 1CMOS40nm

[15] 17.9 20.5 21.5 17.2 60 1CMOS40nm

[5] 13.4 8.7 13.2 31.7 63 1CMOS65nm

[10] 8.1 0.5 6 25.9 77 2.5CMOS130nm

[11] 10 7 14.3 14.8 77 2CMOS65nm

[13] 14.6 10.1 10.2 12.98 77 1.2CMOS90nm

[7] 10.3 4.5 12 36.25 80 1CMOS90nm

Thiswork

(withoutPADs

and CG)

13 17 16 6.3 78.5 0.75CMOS40nm

Thiswork(withPADs

and CG)

12 13 12 6.3 78.5 0.75CMOS40nm

5CONCLUSION

This thesis focused on design and implementation of Injection Locked Power Amplifiersfor the 77GHz automotive RADAR band. A detailed and systematic approach to de-sign the PA has been presented which shows improvements in gain and PAE over priorrecorded designs. Section 5.1 summarizes the thesis while highlighting important designapproaches and trade-offs. Section 5.1, finally lists some suggestions and recommenda-tions for future improvements in this area of research.

5.1. THESIS CONCLUSIONThe thesis is concluded by summarizing main ideas detailed throughout this work. Chap-ter 1 described a basic RADAR architecture and motivates the need for high efficiencypower amplifiers. A literature review revealed the range of output power, PAE, gain andrelative bandwidth achieved by state of the art power amplifiers.

Chapter 2 gives theoretical insight to inductive and capacitive losses followed by ananalysis to show power and efficiency limits to an power oscillator working at its naturalfrequency. The theory of injection locking was presented along with the expected vari-ation of power and efficiency within the locking range of an ILPA. The fundamental re-lation between the locking range (or operating bandwidth) and gain was also explainedin detail. Further, the chapter also proposes a 2-stage PA architecture for automotiveRADARs along with a common-gate matching stage for the purposes of testing. A gen-eral expression for system efficiency in multi-stage PA is also derived in terms of gain andefficiency of individual stages, which is comparable to Frii’s Noise Figure equation forLNAs. An important recommendation specifically for 2-stage PA designs is highlightedin the importance of both efficiency of the pre-driver and gain of the final stage.

Chapter 3 discusses the systematic design procedure, that has been followed through-out this work in detail. Useful information about the active device is derived to under-stand device performance limits and bias conditions before starting the actual design.Such an evaluation gives designers valuable insights and may guide design choices. Thechapter also highlighted an extremely simple class-A design procedure to aid design-ers size CMOS devices based on voltage and current swings. Chapter 3 further shows

73

5

74 5. CONCLUSION

a power amplifier view of an NMOS-only oscillator, which in its simplest form, is verypowerful. The power oscillator may be viewed as a system of single-device PAs feedingeach other (to maintain steady-state oscillations), while delivering power to an externallyconnected load. Well established principals to derive target output power and efficiencyapplicable to conventional PAs, still apply to the power oscillators albeit, with minor cor-rections, arising from the fact that drive power is implicit. Therefore, it is expected thatthe efficiency of a power-oscillator is equivalent to PAE of a conventional PA. The use ofa common-gate input match for the purposes of a test-chip have also been highlighted.

Chapter 4 finally, shows the result of various simulations used to evaluate the ILPA’sperformance. Stage-wise simulations of the ILPA are used depict performance parame-ters at various reference planes. These simulations further, highlight passive losses andtheir impact on system performance. The ILPA core system comprising of injectors,power oscillator and output stage including matching networks is expected to deliver anoutput power of ≈ 13dBm, PAE ≈ 15% and Gain ≈ 15dB with a locking range of ≈ 5G H zcentered around 78.5G H z, while the test-chip is expected to deliver an output power of≈ 12dBm, PAE ≈ 12% and Gain ≈ 12dB when measured pad-to-pad.

5.2. FUTURE DEVELOPMENTSThe phenomenon of injection locking opens up a wide range of applications specificallyfor high gain, high PAE power amplifiers as presented in this work. Further research intoILPAs may possibly leverage results of this work.

• A major issue has been the matching between the ILPA predriver and the outputstage. Output device sizing, requires low shunt-inductance at its gate, which in-evitably are lossy. Different matching structures, such as a transformer or tapped-inductor may matching losses and therefore, improve output power and PAE.

• The sizing problem may potentially be solved by use of a power splitting and com-bining architecture. Power may be split at the injectors into individual chain ofpower-oscillators and combined at output drivers. Such an architecture may al-leviate interstage-matching losses considerably, while maintaining parallel chainsinjection locked to the input.

• For higher output power, stacked amplifier topology may be used while increasingsupply voltage.

REFERENCES 75

REFERENCES[1] G. Kergoski. FMCW RADAR in Automotive Applications - Technology Overview and

Testing. [Online]. Available: https://www.cst.com/~/media/cst/landing-pages/2016automotive/understanding--testing-fmcw-automotive-radar-devices.ashx?la=en

[2] M. Babaie, “Power efficient RF/mm-wave oscillators and power amplifiers for wire-less applications,” Ph.D. Thesis, TU Delft, 2016.

[3] J. Brewer. Jr and P. Gammel. Silicon BiCMOS - the optimal technology forRF power. [Online]. Available: http://www.microwavejournal.com/ext/resources/BGDownload/2/a/BiCMOS%20vs%20CMOS%20White%20Paper.pdf?1497021537

[4] N. Demirel, E. Kerherve, R. Plana, D. Pache, and D. Belot, “59-71GHz widebandMMIC balanced power amplifier in a 0.13um SiGe technology,” in Microwave Inte-grated Circuits Conference, 2009. EuMIC 2009. European. IEEE, 2009, pp. 499–502.

[5] W. Fei, H. Yu, W. M. Lim, and J. Ren, “A 53-to-73GHz power amplifier with74.5mW/mm2 output power density by 2D differential power combining in 65nmCMOS,” in 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2013,pp. 271–274.

[6] A. Agah, H. Dabag, B. Hanafi, P. Asbeck, L. Larson, and J. Buckwalter, “A 34% PAE,18.6dBm 42-45GHz stacked power amplifier in 45nm SOI CMOS,” in 2012 IEEE Ra-dio Frequency Integrated Circuits Symposium, 2012, pp. 57–60.

[7] N. Kurita and H. Kondoh, “60GHz and 80GHz wide band power amplifier MMICs in90nm CMOS technology,” in 2009 IEEE Radio Frequency Integrated Circuits Sympo-sium, 2009, pp. 39–42.

[8] D. Zhao and P. Reynaert, “A 60-GHz dual-mode class AB power amplifier in 40-nmCMOS,” IEEE Journal of Solid-State Circuits, vol. 48, no. 10, pp. 2323–2337, 2013.

[9] H. C. Lin and G. M. Rebeiz, “A 70-80-GHz SiGe amplifier with peak output power of27.3 dBm,” IEEE Transactions on Microwave Theory and Techniques, vol. 64, no. 7,pp. 2039–2049, 2016.

[10] B. Wicks, E. Skafidas, and R. Evans, “A 75-95 GHz wideband CMOS power amplifier,”in European Conference on Wireless Technology, 2008. EuWiT 2008, 2008, pp. 230–233.

[11] C. Kim, P. Park, D. Y. Kim, K. H. Park, M. Park, M. K. Cho, S. J. Lee, J. G. Kim, Y. S. Eo,J. Park, D. Baek, J. T. Oh, S. Hong, and H. K. Yu, “A CMOS centric 77GHz automotiveradar architecture,” in 2012 IEEE Radio Frequency Integrated Circuits Symposium,2012, pp. 131–134.

[12] F. Shirinfar, M. Nariman, T. Sowlati, M. Rofougaran, R. Rofougaran, and S. Pamarti,“A fully integrated 22.6dBm mm-wave PA in 40nm CMOS,” in 2013 IEEE Radio Fre-quency Integrated Circuits Symposium (RFIC), 2013, pp. 279–282.

https://www.cst.com/~/media/cst/landing-pages/2016automotive/understanding--testing-fmcw-automotive-radar-devices.ashx?la=en



http://www.microwavejournal.com/ext/resources/BGDownload/2/a/BiCMOS%20vs%20CMOS%20White%20Paper.pdf?1497021537

http://www.microwavejournal.com/ext/resources/BGDownload/2/a/BiCMOS%20vs%20CMOS%20White%20Paper.pdf?1497021537

76 REFERENCES

[13] T.-Y. Chang, C.-S. Wang, and C.-K. Wang, “A 77 GHz power amplifier usingtransformer-based power combiner in 90 nm CMOS,” in 2010 IEEE Custom Inte-grated Circuits Conference (CICC), 2010, pp. 1–4.

[14] J. Wursthorn, H. Knapp, J. Al-Eryani, K. Aufinger, S. Majied, S. Boguth, H. Li, R. Lach-ner, and L. Maurer, “SiGe power amplifier for automotive radar applications from76 to 81 GHz,” in 2016 IEEE MTT-S International Conference on Microwaves for In-telligent Mobility (ICMIM), 2016, pp. 1–4.

[15] M. Babaie, R. B. Staszewski, L. Galatro, and M. Spirito, “A wideband 60 GHz class-E/F2 power amplifier in 40nm CMOS,” in 2015 IEEE Radio Frequency Integrated Cir-cuits Symposium (RFIC), 2016, pp. 215–218.

[16] J. Lin, C. C. Boon, X. Yi, and W. M. Lim, “A compact single stage V-Band CMOSinjection-locked power amplifier with 17.3% efficiency,” IEEE Microwave and Wire-less Components Letters, vol. 24, no. 3, pp. 182–184, 2014.

[17] J. Lin, C. C. Boon, X. Yi, and G. Feng, “A 50-59 GHz CMOS injection locking poweramplifier,” IEEE Microwave and Wireless Components Letters, vol. 25, no. 1, pp. 52–54, 2015.

[18] M. Törmänen, J. Lindstrand, and H. Sjöland, “A 13dbm 60GHz-band injectionlocked PA with 36% PAE in 65nm CMOS,” in Asia-Pacific Microwave Conference2011, 2011, pp. 1–4.

[19] B. Razavi, RF Microelectronics, 2nd ed., ser. Prentice Hall Commnunications Engi-neering and Emergining Technology. Prentice Hall, 2011.

[20] D. Rowell, “2.161-Signal Processing: Continuous and Discrete, MIT OpenCourse-Ware.” [Online]. Available: https://ocw.mit.edu/courses/mechanical-engineering/2-161-signal-processing-continuous-and-discrete-fall-2008/study-materials/fourier.pdf

[21] R. Adler, “A study of locking phenomena in oscillators,” Proceedings of the IRE,vol. 34, no. 6, pp. 351–357, 1946.

[22] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE Journal ofSolid-State Circuits, vol. 39, no. 9, pp. 1415–1424, 2004.

[23] J. J. Carr and J. M. Brown. Noise factor, noise figure, and noise temperature- National Instruments. [Online]. Available: http://www.ni.com/white-paper/14822/en/

[24] J. M. W. Rogers and C. Plett, Radio Frequency Integrated Circuit Design, 2nd ed.Norwood, MA, USA: Artech House, Inc., 2010.

[25] J. Segura and C. F. Hawkins, CMOS Electronics: How It Works, How It Fails. JohnWiley & Sons, 2004.

https://ocw.mit.edu/courses/mechanical-engineering/2-161-signal-processing-continuous-and-discrete-fall-2008/study-materials/fourier.pdf



http://www.ni.com/white-paper/14822/en/

http://www.ni.com/white-paper/14822/en/

REFERENCES 77

[26] G. Gonzalez, Microwave transistor amplifiers (2nd Ed.): Analysis and Design.Prentice-Hall, Inc., 1996.

[27] E. Maricau and G. Gielen, “CMOS reliability overview,” in Analog IC Reliability inNanometer CMOS, 2013.

[28] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Artech House Inc.,1999.

High Efﬁciency Power Ampliﬁers for 77GHz Automotive RADARs

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