A 77GHz Power Amplifier in Silicon Germanium

BiCMOS Technology

by

Khoa Minh Nguyen

Submitted to the Department of Electrical Engineeringand Computer Science

in partial fulfillment of the requirements for the degree of

Masters of Science in Electrical Engineering and Computer Science

at the

MASSACHUSETTS INSTITUTE OF TECHNOLOGY

August 2006

@ Massachusetts Institute of Technology 2006. All rights reserved.

Author .Department of EArilf Engineering and Computer Science

August 31, 2006

Certified by.Charles G. Sodini

Professor, Electrical Engineering and Computer ScienceThesis Supervisor

A ccepted by ... _ .:.-.-..----- -....... ..Arthur C. Smith

Chairman, Department Committee on Graduate Students

MASSACHUSETTS INSilTUTEOF TECHNOLOGY BARKER

JAN 1 1 2007

LIBRARIES

2

A 77GHz Power Amplifier in Silicon Germanium BiCMOS

Technology

by

Khoa Minh Nguyen

Submitted to the Department of Electrical Engineering and Computer Scienceon August 31, 2006, in partial fulfillment of the

requirements for the degree ofMasters of Science in Electrical Engineering and Computer Science

Abstract

The allocation of millimeter-wave frequencies has opened new possibilities for imag-ing applications such as vehicular radar and concealed weapons detection. Recent ad-vances in silicon processes offer a new means of implementing cost-effective millimeter-wave integrated circuits, a field previously dominated by III-V semiconductors. Bymoving towards silicon, millimeter-wave circuits can achieve new levels of integrationthat were not possible when designed with III-V semiconductors. This thesis discussesthe challenges and design of a 2-stage cascoded class-AB 77GHz power amplifier thatcould be used for imaging applications. Simulation results show a maximum outputpower of 20dBm, 26dB gain, and a maximum power-added efficiency (PAE) of 16%.

Thesis Supervisor: Charles G. SodiniTitle: Professor, Electrical Engineering and Computer Science

3

4

Acknowledgments

This project has been a great learning experience for me, and I could not have done it

without the help of so many others. I would first like to thank my advisor, Professor

Charles Sodini, for giving me the opportunity to work on this project. I appreci-

ated his guidance and intuition throughout this work, and he always provided new

perspectives for approaching problems.

I would also like to thank Helen Kim of Lincoln Laboratory for her insight in

millimeter-wave technologies and design.

The members of the Sodini and Lee research groups also deserve acknowledgement

for providing such an enjoyable and motivating work environment. Particularly, I

want to thank Johnna for her knowledge of and help in millimeter-wave design. I

want to thank Todd for always being around to answer my questions and to help me

with Cadence. I greatly appreciated Anh's guidance in power amplifier design and

his enthusiasm when helping me. I also want to give a special thanks to Albert for

his extensive knowledge in all things RF and for having the patience to answer my

endless stream of questions.

Although working on two projects was a challenge, I learned so much from working

on both, so I want to thank the members of the WiGLAN project. I want to thank

Nir for helping me join and get started in this research group. I also want to thank

Ken and Farinaz for the hours spent working on the WiGLAN project, which gave me

much needed breaks from millimeter-wave design to tackle other interesting problems.

Finally, I would like to thank my parents for all of their support throughout the

years and providing me with the discipline to make it this far. And I would also like

to thank my little sister for always being there to cheer me on.

Thanks everyone,

Khoa

5

6

Contents

1 Introduction 13

1.1 Imaging System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.2 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2 Previous Work 17

3 Power Amplifier Design 19

3.1 D esign M etrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2 Conjugate Match versus Load-line Match . . . . . . . . . . . . . . . . 20

3.3 Breakdown Voltage ....... ............................ 21

3.4 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Circuit Design 27

4.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.1 G ain Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.2 B ias Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2 Current Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3 P assives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.4 Transformation Networks . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.5 L ayout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5 Simulation Results 37

5.1 O utput power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.2 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7

5.3 S-parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.4 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6 Conclusion

A Circuit Schematics

B Acronyms

8

45

47

51

List of Figures

1-1 Block diagram for front-end of imaging system. . . . . . . . . . . . . 15

3-1 (a) The common-emitter configuration. (b) The common-base config-

u ration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3-2 Common-emitter configuration with base resistance. . . . . . . . . . . 23

3-3 A 2-port model for stability. . . . . . . . . . . . . . . . . . . . . . . . 24

4-1 (a) Schematic of common-emitter. (b) Schematic of cascoded common-

em itter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4-2 I vs Vcc for cascode and common-emitter with similar biasing condi-

tions (15mA, 300Q base resistance). . . . . . . . . . . . . . . . . . . . 29

4-3 (a) Bias circuit for active transistor. (b) Bias circuit for cascode tran-

sistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4-4 Schematic of gain stages. . . . . . . . . . . . . . . . . . . . . . . . . . 33

4-5 C hip layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5-1 Input power versus output power. . . . . . . . . . . . . . . . . . . . . 38

5-2 Input power versus power added efficiency. . . . . . . . . . . . . . . . 38

5-3 S-param eters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5-4 (a) First stage k-factor stability plot. (b) First stage k-factor stability

plot zoomed at minimum. . . . . . . . . . . . . . . . . . . . . . . . . 40

5-5 First stage BI stability factor. . . . . . . . . . . . . . . . . . . . . . . 41

5-6 (a) Second stage k-factor stability plot. (b) Second stage k-factor sta-

bility plot zoomed at minimum. . . . . . . . . . . . . . . . . . . . . . 41

9

5-7 Second stage B1 stability factor. . . . . . . . . . . . . . . . . . . . . . 42

5-8 (a) Overall k-factor stability plot. (b) Overall k-factor stability plot

zoomed at minimum. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5-9 Overall BI stability factor. . . . . . . . . . . . . . . . . . . . . . . . . 43

A-1 Schematic of gain stages. . . . . . . . . . . . . . . . . . . . . . . . . . 47

A-2 Schematic of bias for first stage. . . . . . . . . . . . . . . . . . . . . . 48

A-3 Schematic of bias for second stage. . . . . . . . . . . . . . . . . . . . 48

A-4 Schematic of bias for cascode. Each cascode has a separate bias circuit. 49

10

List of Tables

2.1 Performance summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

A.1 Values and sizes for components used. . . . . . . . . . . . . . . . . . . 50

11

12

Chapter 1

Introduction

The millimeter-wave (MMW) frequency spectrum, which spans from 30 to 300GHz,

features properties that are highly suitable for imaging. Its sensitivity to metals

through opaque objects like clothing and inclement weather like fog make it ad-

vantageous over the infrared and visible spectrums, which are highly attenuated in

such conditions. MMW frequencies also have wavelengths small enough to provide

sufficient resolution for imaging, which makes them advantageous over microwave fre-

quencies. As a result, certain bands of this spectrum, such as the 77GHz, 94GHz,

and 120GHz bands, have been allocated for imaging applications such as vehicular

radar and concealed weapons detection.

It is only recently that advancements in silicon-germanium (SiGe) technology have

produced devices with transit frequencies capable of operating at MMW frequencies.

SiGe processes have progressed to the point that they can challenge the III-V tech-

nologies that currently dominate MMW circuits. Moving towards silicon will not only

be cheaper but allow for greater integration between MMW circuits and the analog

and digital processing circuits.

1.1 Imaging System

These developments motivate the research for integrated imaging transceiver arrays

in SiGe technology. Figure 1-1 depicts an active imaging system discussed in [1] by

13

Accardi. The system has a planar array of 1000 transceiver elements. Each element

will have a heterodyne architecture with a 76GHz voltage-controlled oscillator (VCO)

and an intermediate frequency (IF) of 1GHz. On the receiver side, the analog-to-

digital converter (ADC) will oversample the IF at an expected rate of approximately

4Gs/s. A key feature to this system is that the IF on the transmitter side does not

carry information. It is generated by multiplying the system clock of the central

processing unit (CPU). A 77GHz VCO could potentially drive the transmitter's

power amplifier without a mixer. But the need for a synchronous 1GHz clock for

the ADC and the capability to share the VCO with the receiver side led to the

heterodyne architecture. Ideally, a spectrally pure 77GHz tone will be transmitted

from the antenna. However, the aggregate signal transmitted from the antenna array

is expected to have a bandwidth of about 200MHz due to mismatches in center

frequency between the VCOs of the 1000 elements. This creates challenges that

are currently being explored for the subsequent digital processing block, which must

reduce the data rate from 4Gs/s to about 100ks/s in each of the 1000 elements before

sending the data to the CPU. To compute the intensity of radiation at each pixel,

the CPU will perform beamformation of the antenna array by controlling the amount

of delay and weight given to each element's received data. Accardi shows that the

pixel resolution p is dependent on the carrier frequency wavelength A, the length of

the antenna array L, and the distance of the target r with the following relationship.

p ~~ 0.8859- (1.1)L

For a 77GHz system with an array length of 2m and a target distance of 30m, the

pixel resolution would be approximately 5.2cm. Beamformation is used to calculate

each pixel intensity which are then combined to form an image. Work is currently

being done to determine an efficient means to improve image quality given an appli-

cation requirement of 10 frames per second.

14

*. Array of 1000 transceiver elements

P A 4 - I m a g e ----- 1 G H z 1PA Reject Mixer x10 100MHzfrom CPU

76GHz

>LNA LPF ADC DigitalSProcessing

1OOks/s pertransceiver to CPU

Figure 1-1: Block diagram for front-end of imaging system.

1.2 Power Amplifier

RF transceiver blocks are currently being designed to operate at MMW frequencies.

One block of particular interest is the power amplifier. Its role is essential to signal

transmission, but its design features are severely hindered by the scaled technology

and the operating frequency of interest.

This thesis will explore the challenges of designing a 77GHz power amplifier in

the most advanced SiGe BiCMOS technology currently available, the 120nm IBM

8HP process with its high-fT devices and high-Q passives. Although MOSFETs are

available, the design will focus on the heterojunction bipolar transistors (HBT), which

are more viable since they have a higher fT of approximately 200GHz compared to the

MOSFETs' fT of 150GHz. Chapter 2 will review similar works that has been done in

this field and describe their approaches and contributions. Chapter 3 will provide a

background in power amplifier design and the performance metrics that will be used.

Limitations that arise from the technology will then be discussed. Chapter 4 will

15

describe the methodology and design in this work. Chapter 5 will show simulation

results. And finally, chapter 6 will conclude the thesis.

16

Chapter 2

Previous Work

MMW power amplifier design in SiGe processes has only recently garnered research

interest. This chapter reviews related works that were published prior to the tapeout

of this design.

Pfeiffer et al. presented the first 77GHz power amplifier in a 120nm SiGe process in

[2]. They designed a 2-stage Class-AB power amplifier with a 2-stage common-emitter

topology. Using 300Q of base resistance for each stage, they established that they

could raise the HBT's BVCER to approximately 4V, providing more swing and en-

abling them to increase the supply voltage to 2.5V. Quarter wavelength transmission

lines were used as RF chokes, and impedance transformation networks were formed

with transmission lines and metal-insulator-metal (MIM) capacitors. A power gain of

6.1dB was measured at 77GHz, and a maximum PAE of 2.5% was achieved. The max-

imum single-ended output power was 9.5dBm with a 1-dB compression point (CP1dB)

of 8.6dB.

Hajimiri et al. presented a 77GHz class-AB power amplifier that had a 4-stage

common emitter configuration in [3]. Like Pfeiffer, they relied on a 300Q base resis-

tance to raise the BVCER to 4V, but they also used power combining in the last stage

to further increase the output power. The power combining was done by splitting

the output stage into two sets of transistors of the same size. The outputs of these

devices travelled through near quarter wave length of transmission line (840) before

combining into a single node. This node then saw the transmission line choke to the

17

supply voltage and a coupling capacitor to the output. They reported a gain of 17dB

and a peak PAE of 12.8% with a supply voltage of 1.5V. They recorded a maximum

output power of 17.5dBm with a supply voltage of 1.8V and a CP1dB compression

point of 14.5dBm with a supply voltage of 1.5V.

Pfeiffer later presented a 61.5GHz transformer matched class-AB power amplifier

in [4]. This amplifier had a single-stage differential cascode topology, in which the

cascode base was grounded to overcome the breakdown voltage and allow a supply

voltage of 4V. The main contribution of this design was the use of a transformer with a

center-tapped supply voltage that coupled the outputs of the cascodes to a differential

output load. The transformer was implemented using a stacked architecture rather

than a coplanar one, and it had a coupling factor of k=0.8. It achieved a maximum

differential output power of 14dBm and a CP1dB of 8.5dBm. It had a 14dB power

gain and a 4.2% PAE. The benefits of the cascode topology will be discussed in

Chapter 4.

Table 2.1 summarizes the performances parameters of these works.

Work Topology Max P0, [dBm] CPldB Power Gain Max PAE(single-ended) [dBm] [dB] [%]

77 GHz PA 2 Stage CE 9.5 8.6 6.1 2.5Pfeiffer 2004 Class-AB77GHz PA 4 Stage CE 17.5 14.5 17 12.8Hajimiri 2005 Class-AB (Vcc=1.8V) (Vcc=1.8V) (Vcc=1.5V)61.5GHz PA 1 Stage Cascode 11 5.5 14 4.2Pfeiffer 2005 Class-AB

Table 2.1: Performance summary.

18

Chapter 3

Power Amplifier Design

3.1 Design Metrics

Power amplifier design differs from traditional amplifier design due to the emphasis

on output power and efficiency. A power amplifier must be able to output a specified

amount of power, and as output power increases, consideration for large signal as well

as small signal behavior must be taken into account. One consequence of this is the

use of a load-line match rather than a conjugate match, which will be discussed in

Section 2.2. The other key aspect of a power amplifier is its efficiency, since a power

amplifier typically drives and consumes the most power in a transceiver front-end.

The common metric for efficiency is the power added efficiency (PAE) which takes

the input power into consideration and is shown below.

Pout - PinPA E= " " (3.1)

PDC

Along with these two major tradeoffs, power gain and linearity are also of impor-

tance. Power gain between the input and output has a direct effect on PAE, and is a

consideration for any amplifier. However, as will be shown in the next section, power

gain is typically sacrificed for increased output power. Power gain is observed by

measuring the S21. The requirement for linearity is often determined by the amount

of distortion the system can withstand. A standard metric for linearity is the CPldB,

19

which is the output power that is 1dB less than the linear power on the input versus

output power transfer curve. Another metric is the third-order intercept point (IP3),

which is the intersection between the fundamental power gain and the extrapolated

3:1 slope of the third-order intermodulation products [5].

Generally, an output power is specified, and the amplifier is designed such that

maximum efficiency is obtained while still maintaining acceptable gain and linearity.

The same approach will be used for this project, in which the target output power is

20dBm. The design will focus on conducting class power amplifiers, particularly the

Class-A and Class-AB. With a conducting class amplifier, linearity is not expected

to be a major concern. Since the goal is to transmit a spectrally pure 77GHz tone,

harmonics of 77GHz are far out of band and are unlikely to cause problems from the

system's perspective.

3.2 Conjugate Match versus Load-line Match

Conjugate match is the transformation of the load to be the complex conjugate of

the amplifier's output impedance, which minimizes return loss and maximizes power

transfer. However, this assumes that the transistor can support the required current

and voltage. As the output power increases, the currents and voltages become large,

and small signal conditions can no longer be assumed. The transistor is limited by

the amount of current it can control and the amount of voltage it can swing. Device

breakdown voltages are typically the first to limit, so a conjugate match would cause

the signal voltage to compress before the device's maximum output power can be

achieved [5].

An alternative approach is the load-line match, which transforms the output load

to be an R,t given the current and voltage limits of the device. This enables the

transistor to reach its maximum output voltage and current, which maximizes the

output power. Assuming the output resistance of the amplifier is larger than Rop,,

20

which is typically true for cases such as the common-emitter, R0 ,, is defined as follows.

Rot - Vmax (3.2)Imax

Because Ropt is smaller than the output resistance of the amplifier, which is what a

conjugate match transforms to, the load-line match gives a larger output power at

the cost of power gain [5].

3.3 Breakdown Voltage

One of the growing challenges of designing power amplifiers in advanced bipolar pro-

cesses is the decrease in breakdown voltages. This is a direct consequence of tech-

nology scaling. As device dimensions become smaller, devices become faster due to

decreased parasitics capacitances and shorter base transit times, which increase the

fT. However, the doping concentrations must increase accordingly. As shown in

[6] and [7], reducing the base width requires increasing the base doping to prevent

punchthrough and to maintain the forward current gain F. The collector doping

must also increase proportionally to the increase in collector current density and to

reduce the intrinsic collector resistance. From Equation 3.3 in [8], the breakdown volt-

age of the base-collector PN-junction is inversely proportional to the lighter doping

concentration, or collector doping, so it decreases with each generation of technology

scaling.

VB R E2 K, Eo NANDcrit 2q NA+ ND

D NA ND\

NA + ND

c 1 (3.3)Nc

The breakdown of the base-collector PN-junction will be shown to be equivalent

to BVCBO and is the upper limit of the device's breakdown. The actual breakdown

of the device depends on its configuration in the circuit. The two bounding cases

21

VCE VCE

1+ I +

E B C EAB C

'B

(a) (b)

Figure 3-1: (a) The common-emitter configuration. (b) The common-base configura-tion.

are the common-emitter and common-base configurations, which give rise to BVCEO

and BVCBO, respectively, and are shown in Figure 3-1. These are slightly different

from the standard setups for breakdown, like the ones found in [9], because they have

current sources where [9] shows an open circuit. However, having a fixed current

source rather than an open is more representative of an actual circuit and does not

change the mechanism for breakdown, so BVCEO and BVCBO are unchanged.

For both cases, when the device is in forward active mode, increasing the collector

voltage causes electron-hole pairs to be generated by impact ionization in the base-

collector depletion region. The electric field in the depletion region causes electrons

to accelerate towards the collector and holes to accelerate to the base. The path of

the holes is the distinguishing feature between the common-emitter and common-base

cases as shown in Figure 3-1. For the common-base, all of the holes will flow out of

the base to analog ground. Consequently, the emitter is isolated, and the breakdown

of the transistor is the breakdown of the PN-junction between the base and collector,

which is BVCBO and is nominally 5.9V. For the common-emitter configuration with

the base assumed open, the holes generated from the base-collector depletion region

do not exit from the base but travel through the base to the emitter. This, in turn,

increases the electron current through the device which causes impact ionization in the

22

I-'h+

h +

e,e e

h h

base-collector depletion region and generates even more holes. This positive feedback

significantly reduces the breakdown voltage. The voltage at the onset of this effect is

known as BVCEO and is approximately 1.8V in this process.

A third case is a common-emitter with a finite base resistance as shown in Figure 3-

2, which provides an alternate path at the base for the generated holes to exit. The

amount of holes that exit through the base is dependent on the value of the base

resistance. As more holes exit through the base, fewer holes will cross the base-emitter

junction, which will reduce the positive feedback effect and increase the breakdown

voltage. As the base resistance approaches zero, the breakdown voltage will approach

BVCBO-

VCE

+

E B C

h+ e

h+ h

IBC RB

Figure 3-2: Common-emitter configuration with base resistance.

For a power amplifier, a higher breakdown voltage allows for more swing at the

collector, which translates into more output power. As shown in Chapter 2, various

methods for overcoming the low breakdown voltage in MMW power amplifier design

that have been discussed in the literature.

3.4 Stability

An amplifier's stability refers to its resistance to oscillation and is a common concern

in power amplifier design. Coupling between the nodes, particularly with the high-

23

FS FIN FOUT FL

Two-port ZLVS Network

ZIN ZOUT

Figure 3-3: A 2-port model for stability.

powered output node, combined with the high gain of the design can create conditions

that cause the amplifier to behave like an oscillator. In Figure 3-3, the two-port

network is considered unconditionally stable if the real parts of ZIN and ZOUT are

greater than zero at any frequency for any load and source with a positive real part.

In other words, ZIN and ZOUT will not have a negative resistance given any passive

load and source impedances [10]. A negative resistance implies that the port has a

reflection coefficient 1F greater than one, which means a signal travelling towards

the port will be reflected with a larger magnitude. Therefore a signal, or possibly

noise, reflecting back and forth between the port and the passive source or load has

the potential to build up into an oscillation. A negative resistance alone may not be

enough to excite an oscillation, but to ensure unconditional stability, there can be no

negative resistances looking into the network or in the load or source [11]. This can

be represented mathematically in terms of reflection coefficients, as shown from the

following conditions:

Fsr < 1 (3.4)

IF'L < 1 (3.5)

24

|FINI S11 + S12S21 FL < (3.6)1 - S2217L

FOUT = S22 + S12S2 Fs9 <1 (3.7)1 - SlIrF

Kurokawa shows in [12] that these conditions can be manipulated to produce a

k-factor and B1, shown in Equations 3.8 and 3.9.

1 - -Sn|2 _S 2212 + |SlIS 22 - s12s21 2 (3.8)2|S12S211

B 1 = 1 + ISiil 2 - IS2212 -- ISIS22 - S12S2112 (3.9)

For unconditional stability, the k-factor must be greater than one, and B1 must

be greater than zero. Otherwise, the amplifier is considered potentially unstable.

It should be noted that for multistage amplifiers further care must be taken to en-

sure stability. Since all but the first and last stages have active sources or loads, testing

the k-factor and B1 conditions for the overall circuit is necessary but insufficient to

guarantee unconditional stability. However in [13], Uchida et al. determined the con-

ditions for unconditional stability for a multistage amplifier by extending Equations

3.6 and 3.7 into the amplifier and recursively deriving the reflection coefficients for

each stage. For a multistage amplifier with N stages, the kth stage has the following

reflection coefficients.

F-IN,k -A1(k -1Pin,k (2 < k < N + 1) (3.10)S"1 - S2 in,k

FOUT,k-1 = - AkFutk1 (1 < k < N) (3.11)1 - SFk

where

Ak = 22 2 - 21 (3.12)

25

PIN,N+1 =FL (3.13)

FOUT,O -- s (3.14)

For unconditional stability of the overall amplifier, the reflection coefficients for

every stage cannot not exceed unity. Assuming a passive source and load, they found

that, due to the recursive nature of the reflection coefficients, only the initial and

final stages need be unconditionally stable for the remaining reflection coefficients to

be greater than one. Since this project focuses on a two-stage design, ensuring that

both stages are unconditionally stable will show unconditional stability for the entire

design.

26

Chapter 4

Circuit Design

4.1 Topology

In order to simplify the test measurement setup, a single-ended design was chosen.

This allows for a direct interface with the available test setup, which will consist of

single-ended waveguides and equipment, and eliminates the need for a balun. Com-

mercial off-chip baluns are unavailable at this frequency range, and on-chip baluns

are costly in terms of area and add a source of loss.

4.1.1 Gain Stages

After experimenting with various topologies including the common-emitter and common-

base, a cascode topology was chosen for the gain stages of the amplifier. Since a

cascode is simply a cascade of a common-emitter and a common-base stage, if bi-

ased properly, it can resolve the issue of low breakdown. By providing a low base

impedance at the base of the cascode, the breakdown of the cascode transistor will

approach BVCBO, which is a large increase in swing compared to a similarly biased

common-emitter stage. Figure 4-1 shows the setup for two similarly biased circuits

with the cascode base biased with zero base impedance, and the Ic versus VCE plots

are shown in Figure 4-2. Contrary to conventional belief, the cascode actually pro-

vides more headroom in this case, so the supply voltage was raised to 3.5V.

27

IC V0

(a)

Figure 4-1: (a) Schematicemitter.

IC

VCC

(b)

of common-emitter. (b) Schematic of cascoded common-

The cascode provides other advantages as well. It decouples the input and output

of each stage, which improves the reverse isolation, S12, and the stability. The Miller

effect is reduced because the gain between the base and collector of the active tran-

sistor is now approximately -gm/gm, or -1, rather than -gmRL. For identical setups

where a common-emitter stage and cascode are each sourced with an R, and loaded

with an RL, Equations 4.1 and 4.2 show how this reduced Miller effect increases the

3dB frequency for the cascode, which corresponds to an increase in bandwidth.

1f3dB,ce -- [c RL

2-F [ Rs||ry] [Cr+ Cj(1 + gmRL +.IIr

1f3dB,casc 21r[R8 T][ +2C p

(4.1)

(4.2)

Power gain is also increased. Equation 4.3 shows that the IS21 2, which is the

power gain PG, is inversely proportional to the real part of the input impedance.

G PoutPi-

Re{Z 0ot}V.2

Re{Z fi}

28

0.

0.5-

0.4-

0.3

0.2-

0.1

0

-0.10 1 2 3 4 5 6 7 8 9

Vcc (V)

Figure 4-2: I, vs Vc, for cascode and common-emitter with similar biasing conditions(15mA, 300Q base resistance).

V2t Re{Zj,}

VnRe{ Zut }

_ (gmRe{Zout}) 2 Re{Zin }Re{f Z,,ut }

= 92nRe{Zout}Re{Z}9M(.3

The power gain for similarly loaded common-emitter and cascode are shown in

Equations 4.4 and 4.5. It can be seen that the reduced Miller effect in the cascode

case causes the real part of the input impedance to be larger, which causes the power

gain to be larger.

PGce g. RL-

PG,casc gm RL

Te {sCj,(I + g,,R L )

Re 1Re, s(I + g") I

29

}1r7,

sC,

1 |sC, |r,

(4.4)

(4.5)I

o

(4.3)

- - - --

4.1.2 Bias Stages

Because the base resistance on the cascode is critical to the transistor breakdown, the

bias stages must present a very low resistance. The topologies in Figure 4-3 were used

for biasing the active and cascode transistors. Both relied on "helper" transistors,

QB2 and QB6, which provided negative feedback and produced an output resistance

of about 8Q. The bias circuitry for the cascode had a diode-connected transistor, QB4

to offset the current mirror device. It was also biased by the supply voltage V,,, unlike

the biasing cicuits for the active devices which are controlled by an external voltage

source via a bondpad. This was done so that the bias for the active device can be

adjusted while the bias for cascode is set to about 1.9V. Also, a bypass capacitor of

2pF was placed at the base of the helper transistor to AC short any signal reaching

the bias stage and improve stability.

BP CBP RBl RB7

QB2 BB6

()B1 QB4RB VB VBcasc

CBP RB3 CBP 0 B5 - CBP

R~8

(a) (b)

Figure 4-3: (a) Bias circuit for active transistor. (b) Bias circuit for cascode transistor.

The cascode transistors from each stage had their bases tied directly to their own

bias stage to ensure the low resistance, and a 2pF bypass capacitor was placed at

each bias node. The active transistors' bases cannot be tied directly or the input

signal would short to the bias stage rather than flow into the active device. Following

precedence from Pfeiffer in [2], 300Q was chosen to be the base resistance of the active

transistor. This ensured that the active device would not reach its breakdown due to

swing at the cascode's emitter node. Therefore the base resistance of transistor QB1

was designed to be proportional to the 300Q base resistance of the active transistor

30

based on the current mirror ratio.

4.2 Current Allocation

A target output power of 20dBm was specified. The input is expected to come

from a VCO or mixer that would have an input power up to about OdBm. From

preliminary simulations with the cascode topology, a power gain of approximately

10dB was achieved for a single stage. At least 20dB of power gain was needed, so a

2-stage design was used.

The breakdown voltage dictates the amount of swing that can be achieved. Since

the cascode base voltage was tied to approximately 1.9V, and the VBEOn of the HBTs

in this process is about 0.9V, the cascode transistor's emitter voltage was pinned to

approximately 1V. By setting the supply voltage to 3.5V, a swing of approximately

2.5V can be expected for each stage. Design began with the output stage, in which

a load-line match was used, and Rpt was found from the following equation.

V2ROPE = swng (4.6)

2POut

Substituting 2.5V for Vwing and 100mW for Pout gave an Ropt of 31Q. The bias

current can then be found by substituting 3.5V and 31Q into the Equation 4.7.

IDC - CC(47)Ropt

The first stage was also designed with a load-line match but with an expected out-

put power of 1OdBm. It was designed such that its 1-dB compression point (CPldB)

occurred after the CP1dB of the second stage. These equations were used as a start-

ing point, and after a number of iterations, the final bias currents were chosen to

be 15mA for the first stage and 105mA for the second stage. With this biasing, the

devices shut off for a portion of its conduction cycle with the expected OdBm input,

leading to Class-AB rather than Class-A operation. The Ropt was 120Q for the first

stage and 22Q for the second stage. The transistors were sized based on the fT ver-

31

sus current density characteristic curves found in the BiCMOS-8HP Model Reference

Guide [14] found in the process's design kit.

4.3 Passives

The transmission lines in this design were used primarily for their inductances. To

maximize the inductances, the transmission lines were composed of the two farthest

metal layers: analog metal AM for the signal and Ml for the ground shield. Also,

these lines did not employ grounded side shields. This was done to further increase the

inductances of the transmission lines while reducing capacitances for a given length.

However, this reduced the isolation between structures in the layout. Further work

will be done to explore the consequences of this design decision.

Capacitors were realized using MIM capacitors which are formed using metal

layers QY and LY. At 77GHz, care had to be taken such that the large capacitors in

the design did not operate beyond their self-resonant frequencies. Doing so causes the

capacitors to present an inductive rather than a capacitive impedance. A large bypass

capacitor of 10pF was placed at the input of supply voltage. 2pF bypass capacitors

were used throughout the design at the bias voltages and ends of transmission line

chokes. Coupling capacitors between the input bondpad and the first stage and

between the first and second stages were also 2pF. Because the operation frequency

is at 77GHz, all of these capacitors were split into parallel arrangements of 250fF

capacitors to ensure that they were not operating beyond their self-resonant frequency.

The bondpads were designed to be 50pm by 50pm, which was smaller than the

foundry's recommended size of 100am by 100pm. This was done to reduce the amount

of capacitance introduced by the bondpad.

4.4 Transformation Networks

The input port required a conjugate match to ensure that maximum power was

transferred to the amplifier. Since the input power is much smaller than the output

32

power, the small signal model was assumed for the input, which made the conjugate

match valid. The input match therefore transformed the input impedance of the first

stage to be 50Q. Transmission line shunt-stub matching was not used in this case.

Rather, MIM capacitors were used in a pi-match transformation network. Because

the minimum MIM capacitor value that can be achieved is 92fF, the ir-match gave

enough degrees of freedom to allow realizable values of MIM capacitors to be used.

Due to the high power at the output, the large signal model was assumed, and a

load-line match was used. From the previous section, the second stage required an

R0,p of 22Q. An L-match was used to transform the 50Q port and the capacitance

from the bond pad to be 22Q.

Like the output match, the interstage match between the first and second stages

required a load-line match. A T transformation network was employed to transform

the input impedance of the second stage to be 120Q.

The final circuit design for the gain stages is shown in Figure 4-4. The entire

circuit and specific component values can be found in Appendix A.

CBPT2 2

QiC, T

H ( (+---( Q, -(

BP C2 C3

TBPT5

C7 BP

R2Q 4

Q3

C5

Figure 4-4: Schematic of gain stages.

33

4.5 Layout

The final chip layout is shown in Figure 4-4 and was submitted for fabrication on

May 8, 2006 using IBM's SiGe 8HP BiCMOS 7 metal layer process. The chip size is

550pum by 840pm. There are 9 bondpads: 2 for signal, 1 for supply, 2 for biasing, and

4 for ground.

34

Figure 4-5: Chip layout.

35

36

Chapter 5

Simulation Results

The power amplifier was simulated in SpectreRF using the vertical bipolar inter-

company (VBIC) model for the 120nm HBTs. Parasitic resistances and capacitances

were extracted and included in these simulations.

5.1 Output power

Figure 5-1 shows the output power versus input power. The maximum power is

shown to be 20dBm, and the 1-dB compression point is 15.3dBm. The dip in output

power at an input power of about 6dBm is puzzling, but one conjecture is that this

simulation result is due to limitations of the VBIC model. The VBIC model is known

to have discrepancies at high current densities, when the device is operating beyond

its peak on the fT versus current density characteristic curve. The authors of [15]

and [16] have reported that the Kirk effect and heterojunction barrier effect are not

accurately modelled when the device is in high injection operation. For a power

amplifier operating at near maximum fT with large signal swings, the DC operating

point of the transistors can be pushed beyond the peak into the poorly modelled

rolloff region. The inaccurate fT would result in an inaccurate gi, which could cause

deviations seen in the amplifier's gain plot.

37

20

18

16

E14

0

12

10

8

-20 -15 -10 -5 0 5 10 15Pin (dBm)

Figure 5-1: Input power versus output power.

18

16-

14-

12

10

8

6 -. . . .. . . .. .. . .

Figure 5-2:

Pin (dBm)

Input power versus power added efficiency.

38

0-

-. -.... -.--.--.--.

5.2 Efficiency

Figure 5-2 shows the PAE versus input power. The peak PAE is 16% at an input of

2.5dBm. This shows a marked improvement over the PAE of the published amplifiers.

It should be noted that the simulated results for PAE are typically optimistic when

compared to actual measured results.

5.3 S-parameters

Figure 5-3 show the amplifier's S-parameters. The S11 has a notch of -20.5dB at

76GHz and is -19dB at 77GHz, which shows that the input is well matched. The S21

shows a power gain of 26.2dB. The 3dB bandwidth of the power gain is 6.1GHz. The

improved isolation of the cascode configuration gives the S12 a reverse isolation of

-58.2dB at 77GHz. The S22 is -8.6dB at 77GHz. It does not have a notch directly at

77GHz due to the use of a load-line match instead of a conjugate match.

5.4 Stability

As described in Chapter 3, for a multistage amplifier to be unconditionally stable, the

first and last stages must be unconditionally stable. The amplifier was partitioned

into its separate stages by dividing the circuit at the base input of the second stage,

and stability analysis was performed on each stage. The stability factors for the first

stage are shown in Figures 5-4 and 5-5, while the stability factors for the second stage

are shown in Figures 5-6 and 5-7. The k-factor is greater than one and B1 is greater

than zero for each stage, so both stages are unconditionally stable. The stability of

the whole amplifier was also simulated. Figure 5-8 shows the overall k-factor, which

drops to a minimum of 16.4 at 76.4GHz, and Figure 5-9 shows the overall B1 stability

factor, which is always greater than zero.

39

40 60frequency (GHz)

40 60frequency (GHz)

-40

-60

C.~j

C/)

...... ...........

.............

...... 71-1 . 1810 -140

80 100 20

C/)

80 100

40 60 80 100frequency (GHz)

0.

-2

-4

-6

-8

-10

-12

-142 40 60 80 100

frequency (GHz)

Figure 5-3: S-parameters.

7000

6000

5000

o 40000CO

3000

2000

1000

06 20 40 60 80frequency (GHz)

(a)

Figure 5-4:

COJ

3.8

3.6

3.4

3.2

3

2.8

2.6

2.4

2.2

100 120 92

(a) First stage k-factor stability plot.

94 96 98 100 10294 96 98 100 102

frequency (GHz)

(b)

(b) First stage k-factor stabilityplot zoomed at minimum.

40

0

-5

a-10

cn -15

-20

-25'20

30

20

10

C/) 0

-20'2

104 106

.......... -

........-

-120

' ' '

-80-

-100-

-. ..-. .-

0

10

0

60frequency (GHz)

80 100 120

Figure 5-5: First stage BI stability factor.

16

14

12-

10-

8

6

4-

2-

0 0 4 0 80 20 40 60 80

frequency (GHz)

(a)

4.

4

3.5

3C13

2.5

2

1.5

100 120 55 60 65 70 75 80frequency (GHz)

(b)

Figure 5-6: (a) Second stage k-factor stability plot. (b) Second stage k-factor stabilityplot zoomed at minimum.

41

1.8

1.6

1.4

1.2

"m0.8

0.6

0.4

0.2

0 20 40

0CO

85 90

. . . .. .. . . ...... .-

J

60frequency (GHz)

80 100 120

Figure 5-7: Second stage BI stability factor.

18 x 10

16-

14-

12-

10-

6

4-

2-

0120 40 60

frequency (GHz)

(a)

80

35

30F

15

in

100 72 73 74 75 76 77frequency (GHz)

(b)

Figure 5-8: (a) Overall k-factor stability plot. (b) Overall k-factor stability plotzoomed at minimum.

42

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

Co

0-0 20 40

L00Co

0 78 79 80

25- -

S20-

0- 0 2 0 4 0 6 0 8

0 10 20 30 40 50 60 70 8frequency (GHz)

Figure 5-9: Overall Bi stability factor.

0 90 100

43

1.6

1.4

1.2

1

Cm 0.8

0.6

0.4

0.2

)

44

Chapter 6

Conclusion

A 77GHz Class-AB power amplifier was designed and submitted for tapeout on May

8, 2006. By taking advantage of the cascode topology, a 20dBm power amplifier with

a CP1dB of 15.3dBm was simulated. It has a power gain of 26dB and a maximum

PAE of 16%. It will be tested and characterized upon its return. The issues learned

from this run will be used to push the power amplifier design to 120GHz in SiGe 8HP.

The motivation for operating at even higher MMW frequencies is to use the smaller

wavelengths of 120GHz to obtain an improvement in the imaging resolution. The

8HP's performance is expected to fail at 120GHz, but determining where the failure

occurs will be useful in determining which direction to take the next generation of

SiGe technology.

45

46

Appendix A

Circuit Schematics

T2 CBP T5 CBP

7 T6 BP

Rl Q2 R2 Q4

C1 T, T3 T4Q1 Q3

BP C2 C3 C5

Figure A-1: Schematic of gain stages.

47

BP CBP RB1

0 B2

QB1 R9RB2 \/B1

BBP3

Figure A-2: Schematic of bias for first stage.

BP CBP RB4

QB4

QB3 RIRB5 VB2

CBP -R B 2

Fhb e

Figure A-3: Schematic of bias for second stage.

48

RB7

~B6

B4

VE

CBP- QB5 -- CBP

I RB8

Figure A-4: Schematic of bias for cascode. Each cascode has a separate bias circuit.

49

Component Value Description

Q1 0.12pm x 10pm M=4 First Stage Active TransistorQ2 0.12pm x 10pm M=4 First Stage Cascode TransistorQ3 0.12pm x 10pm M=15 Second Stage Active Transistor

Q4 0.12pm x 10pm M=15 Second Stage Cascode Transistor

QBI 0.12pm x 10pm M=1 First Stage Bias TransistorQB2 0.12pm x 10pm M=1 High Breakdown First Stage Bias TransistorQB3 0-12pm x 10pm M=1 Second Stage Bias TransistorQB4 0.12pm x 10pm M=1 High Breakdown Second Stage Bias TransistorQB5 0.12pm x 10pm M=2 Second Stage Bias TransistorQB6 0.12pm x 10pm M=2 Second Stage Bias TransistorQB7 0.12pm x 10pm M=1 High Breakdown Second Stage Bias TransistorC1 2pF Input Coupling CapacitorC2 92fF Input Matching Capacitor

C3 100fF Input Matching Capacitor

C4 2pF Interstage Coupling Capacitor

C5 92fF Interstage Matching Capacitor

C6 92fF Output Matching Capacitor

C7 2pF Input Coupling Capacitor

C8 2pF Input Coupling Capacitor

CBP 2pF Bypass Capacitor

T1 L=56p W=4p Input Matching Trans. Line

T2 L=70p W=4p First Stage Choke Trans. Line

T3 L=65p W=4p Interstage Matching Trans. Line

T4 L=60.6p W=4p Interstage Matching Trans. Line

T5 L=38p W=22p Second Stage Choke Trans. Line

T6 L=106.6p W=4p Output Matching Trans. LineR, 300Q First Stage Bias Resistor

R2 300Q Second Stage Bias Resistor

RB1 173Q First Stage Bias ResistorRB2 1.2kQ First Stage Bias ResistorRB3 10kQ First Stage Bias ResistorRB4 92Q Second Stage Bias ResistorRB5 4.5kQ Second Stage Bias ResistorRB6 10kQ Second Stage Bias ResistorRB7 500Q Cascode Bias ResistorRB8 l0kQ Cascode Bias ResistorBP 50pm x 50pm Bondpad

Table A.1: Values and sizes for components used.

50

Appendix B

Acronyms

ADC analog-to-digital converter

CP1dB 1-dB compression point

CPU central processing unit

H BT heterojunction bipolar transistors

IF intermediate frequency

IP3 third-order intercept point

MIM metal-insulator-metal

MMW millimeter-wave

PAE power added efficiency

SiGe silicon-germanium

VBIC vertical bipolar inter-company

VCO voltage-controlled oscillator

51

52

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54