IMPLEMENTATION OF AN FPGA BASED VIDEO CAPTURE CARD

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PRESENTED BY: SHEHRYAR

SEQUENCE

• Project Aim• Spartan 3A Board Overview• Available Tools• Adopted Path• Xilinx Platform Studios• Video Capture• Universal Serial Bus• Challenges

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SEQUENCE (CONTD.)

• Video Compression• AccelDSP• Challenges• Future Work• Questions

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PROJECT AIM

• FPGA based video capture card • Input from an Analog VGA source– Resolution = 1024x768 pixels– Frame Rate= 30 fps– Format = RGB (8:8:8)– Data Rate = 566 Mbps

• Output through a USB 2.0 port – Interfacing VGA with USB– Data Rate = 480 Mbps at hi-speed

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PROJECT AIM (CONTD.)

• Video compression– Data Rate reduction– Memory reduction

• Capture and storage of compressed video data on PC– Standard video format

• Play back through media player• Major parts of project– Video capturing– USB interfacing– Video compression

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SPARTAN 3A BOARD OVERVIEW

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SPARTAN 3A BOARD OVERVIEW (contd.)

• FMC-Video daughter board

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AVAILABLE TOOLS

• Integrated Software Environment

• Xilinx Platform Studios

• System Generator

• AccelDSP

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ADOPTED PATH

• Xilinx Platform Studios– Video Capturing– USB Interface

• AccelDSP– Video compression core

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XILINX PLATFORM STUDIOS

• Embedded processor system– Microblaze– Libraries and drivers– Integration of hardware with software

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XILINX PLATFORM STUDIOS (CONTD.)

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VIDEO CAPTURE

• VGA Analog input– RGB Intensity Signal– Hsync, Vsync

• IIC Programming– Desired mode and resolution– XPS IIC PCORE

• DVI input PCORE– Unified bus interface

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Analog Interface AD9984A

VIDEO CAPTURE

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Microblaze Processor

Processor Local Bus

BRAM

ILMB DLMB

XPS IIC PCORE

IIC MUXPCA 9546A

Analog Interface AD9984A

Digital ReceiverTFP403

DVI Input PCORE

DVI-I Port

FPGA

VIDEO CAPTURE (CONTD.)

• DE-Gen PCORE– Data Enable signal – Generated from HSYNC and VSYNC signals combined with

front porch and back porch values– Output fully captured video signal

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VIDEO CAPTURE (CONTD.)

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Microblaze Processor

Processor Local Bus

BRAM

ILMB DLMB

XPS IIC PCORE

IIC MUXPCA 9546A

Analog Interface AD9984A

Digital ReceiverTFP403

DVI Input PCORE

DVI-I Port

FPGA

DE-GenOther Cores

UNIVERSAL SERIAL BUS

• Introduction– Serial Bus– 4 Wires– Host Controlled– USB Devices

• Unique Addresses• 8 Endpoints

– USB protocol• Token packet• Data packet• Status packet

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FPGA

UNIVERSAL SERIAL BUS (CONTD.)

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Cypress CY7C67300

MICROBLAZE

USB PortPC

USB Controller RISC Core

Proc

esso

r Loc

al B

us

BRAM

ILMB DLMB

SIE

Host Port

Interface

Spartan 3A DSP 3400 Board

USB port

CHALLANGES

• Understanding of different languages– HDL– C/C++

• Learning of XPS– Integration of PCOREs– Developing the driver – Integrating software with hardware

• Development of USB controller– Difficult as RISC processor is involved

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VIDEO COMPRESSION

• What is Video• What is Compression• Need for Compression– Space requirements

• Storage constraints

– Bandwidth requirements• Channel constraints

VIDEO COMPRESSION (CONTD.)

• Spatial Redundancies– Correlation between adjacent data points– Intra –within the frame

• Temporal Redundancies– Correlation between different frames in a video– Inter –across the frames– uses block-based motion compensation

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VIDEO COMPRESSION (CONTD.)

• Three types of frames– I frame –key frame– P frame –Predicted frame– B frame –Bidirectional predicted frame

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VIDEO COMPRESSION (CONTD.)

• To encode a frame each operation is performed at macroblock (MB) level (n x n block of pixel. n=16 )– Intra coded frame (I): every MB of the frame is coded using spatial

redundancy– Inter coded frame (P): most of the MBs of the frame are coded

exploiting temporal redundancy (in the past) – Bi-predictive frame (B): most of the MBs of the frame are coded

exploiting temporal redundancy in the past and in the future

• Group of Picture (GOP): – sequence of pictures between two I-frames

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VIDEO COMPRESSION (CONTD.)

• Exploiting Spatial Redundancies– RGB to YCC

• Chrominance vs luminance• Chroma-sub sampling• Sensation of human eye

– 8x8 Blocks– DCT2

• Frequency Domain• Real part of FFT• DC and AC coefficients • Easy to implement

VIDEO COMPRESSION (CONTD.)

• Exploiting Spatial Redundancies– Zig Zag Scan

• Scan Pattern

– Quantization• Quantization Table• Quantization threshold value• Truncation of coefficients• High frequency values approaching zero

VIDEO COMPRESSION (CONTD.)

• Exploiting Spatial Redundancies– Run Length Encoding

• Consecutive coefficients with the same value• Assigning number of repetitions of same value

– Huffman Encoding• Order of probability of occurrence• Huffman Table

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VIDEO COMPRESSION (CONTD.)

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VIDEO COMPRESSION (CONTD.)

• Exploiting Temporal Redundancies– Motion Estimation

• Two consecutive frames • Macroblock comparison• Recovery of motion vector

– Motion Compensation• Frame segmentation• Block matching • Motion vector correction(prediction error)• Sending prediction error

VIDEO COMPRESSION (CONTD.)

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VIDEO COMPRESSION (CONTD.)

AccelDSP

• Xilinx FPGA tool • Transform Matlab syntax to HDL• Exports the HDL design to System Generator

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BITSTRAEM

COMPLETE DESIGN IN FPGA

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DVI-I in DE-Gen Frame Buffer

USB Controller

Video Compression

Microblaze Processor

Processor Local Bus

BRAM

ILMB

DLMB

XPS IIC PCORE

THANKYOU

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QUESTIONS?

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