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plane output to produce the logicalsum of any AND plane output. With this

structure, PLAs are well-suited for im-plementing logic functions in sum-of-

products form. They are also quiteversatile, since both the AND and OR

terms can have many inputs (productliterature often calls this feature wideAND and OR gates).

When Philips introduced PLAs in the

Terminology

CPLD (com plex PLD): an arrangement of multiple SPLD-like blocks on a single

chip. Alternative names are enhanced PLD (EPLD), superPAL, and

megaPAL.

FPD (field-progra mma ble device): any integrated circuit used for implement-

ing digital hardware that allows the end user to configure the chip to re-

alize different designs. Programming such a device often involves placingthe chip into a special programming unit, but some chips can also be

configured in system. Another name for FPDs is programmable logic de-

vices (PLDs); although PLDs are the same type of chips as FPDs, we pre-

fer the term FPD because historically PLD denoted relatively simple devices.

FPGA (field-programmable gate array): an FPD featuring a general structure

that allows very high logic capacity. Whereas CPLDs feature logic re-

sources with a wide number of inputs (AND planes), FPGAs offer nar-

rower logic resources. FPGAs also offer a higher ratio of flip-flops to logic

resources than do CPLDs.HCPLD (high -cap a city PLD): term coined in trade literature refers to both CPLDs

and FPGAs. We do not use this term here.

Interconnect: the wiring resources in an FPD.

Log ic block: a relatively small circuit block replicated in an FPD array. A circuit

implemented in an FPD is first decomposed into smaller subcircuits that

can each be mapped into a logic block. The term occurs mostly in the

context of FPGAs but can also refer toablock of circuitry in aCPLD

OutputsANDplane

Inputs and flip-flopfeedbacks

D

D

D

D

D

D

Figure 1. PAL structure.


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F I E L D - P R O G R A M M A B L E D E V I C E S

ty is that the programmable-logic plane

fabricated transistors customized for theusers logic circuit by means of wire con-nections. Because the silicon foundry

performs customization during chip fab-rication, the manufacturing time is long,

and the users setup cost is high.Although MPGAs are clearly not

FPDs, we mention them here because

they motivated the design of the field-programmable equivalent, FPGAs. Like

MPGAs, an FPGA consists of an array ofuncommitted circuit elements (logic

blocks) and interconnect resources,but the end user configures the FPGA

through programming. Figure 2 shows atypical FPGA architecture. As the onlytype of FPD that supports very high log-

ic capacity, FPGAs have engendered amajor shift in digital-circuit design.

Figure 3 illustrates the logic capaci-ties available in each FPD category.

Equivalent gates refers loosely to thenumber of two-input NAND gates. Thechart serves as a guide for selecting a

device for an application according to

I/O block

Logicblock

Figure 2. FPGA structure.


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are floating gate transistors like thoseused in EPROM (erasable programma-ble read-only memory) and EEPROM

(electrically erasable PROM). ForFPGAs, they are SRAM (static RAM) and

antifuse. Table 1 lists the most impor-tant characteristics of these program-

ming technologies.To use an EPROM or EEPROM tran-

sistor as a programmable switch for

CPLDs (and many SPLDs) the manu-

Table 1 . Summary of FPD programming technologies.

Sw itch type Reprogra m m a ble? V ola tile? Technology

Fuse No No Bipolar

EPROM Yes No UVCMOS

(out of circuit)

EEPROM Yes No EECMOS

(in circuit)SRAM Yes Yes CMOS

(in circuit)

Antifuse No No CMOS+

+5V

EPROM

Input wire

EPROM

Input wire

Productwire

Figure 4. EPROM programmable

switches.

SRAM

Logic block

Logic block

SRAM SRAM


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might use a small hardware descriptionlanguage such as ABEL for some mod-ules, a symbolic schematic capture tool

for others, and a full-featured hardwaredescription language such as VHDL for

still others. Also, the device-fittingprocess may require steps similar to

those described next for FPGAs, de-

pending on the CPLDs sophistication.Either the CPLD manufacturer or a third

party supplies the necessary softwarefor these tasks.

The FPGA design process is similar tothat of CPLDs but requires additional

tools to support increased chip com-plexity. The major difference is in de-vice fitting, for which FPGAs need at

least three tools: a technology mapperto transform basic logic gates into the

FPGAs logic blocks, a placement toolto choose the specific logic blocks, and

a router to allocate wire segments to in-terconnect the logic blocks. With thisadded complexity, the CAD tools take a

fairly long time (often more than an

Silicon substraten+diffusion

Dielectric

PolysiliconWire

Wire

Antifuse

Oxide

Figure 6. Actels PLICE antifuse structure.

Design entry:Text or

schematic

SPLDsimulation

Fix errors

Configurationfile

Manual Automatic

Translateand merge Optimizeequations

Programming unit

Devicefitting


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ond-sourced by other companies. Thedesignation 16R8 means that the PALhas a maximum of 16 inputs (eight ded-

icated inputs and eight input/outputs)and a maximum of eight outputs, and

that each output is registered (R) by a Dflip-flop. Similarly, the 22V10 has a max-

imum of 22 inputs and ten outputs. The

V means versatilethat is, each outputcan be registered or combinational.

Another widely used and second-sourced SPLD is the Altera Classic

EP610. This device is similar in com-plexity to PALs, but offers more flexibil-

ity in the production of outputs and haslarger AND and OR planes. The EP610soutputs can be registered, and the flip-

flops are configurable as D, T, JK, or SR.Many other SPLD products are avail-

able from a wide array of companies.All share common characteristics such

as logic planes (AND, OR, NOR, orNAND), but each offers unique featuressuitable for particular applications. A

partial list of companies that offer SPLDs

PIA

Logicarrayblock

I/O

block

Figure 8. Altera Max 7000 series architecture.

Array of 16macrocells

Logic array block


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architecture supports wider functionswhen necessary. Variable-size OR gatesof this sort are not available in basic

SPLDs (see Figure 1), but similar fea-tures exist in other CPLD architectures.

Max 7000 devices are available inboth EPROM and EEPROM technolo-

gies. Until recently, even with EEPROM,

Max 7000 chips were programmableonly out of circuit in a special-purpose

programming unit; in 1996, however,Altera released the 7000S series, which

is in-circuit reprogrammable.

AMD Mach. AMD offers a CPLD fam-ily comprising five subfamilies calledMach. Each Mach device consists of

multiple PAL-like blocks (or optimizedPALs). Mach 1 and 2 consist of opti-

mized 22V16 PALs, Mach 3 and 4 con-sist of several optimized 34V16 PALs,

and Mach 5 is similar to Mach 3 and 4but offers enhanced speed perfor-mance. All Mach chips use EEPROM

technology and together the five sub-

ProductselectmatrixPIA

Local logic

array blockinterconnect

Clear(global clearnot shown)

Global clock

Array clock

To PIA

Set

Inputs from othermacrocells inlogic array block

State

SD Q

R

Figure 10 . Max 7000 macrocell.

34V16 PAL-like blockI/O (32)


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between this block and a normal PAL:1) a product term (PT) allocator be-tween the AND plane and the macro-

cells (the macrocells comprise an ORgate, an EXOR gate, and a flip-flop), and

2) an output switch matrix between theOR gates and the I/O pins. These fea-

tures make a Mach 4 chip easier to use

because they decouple sections of thePAL-like block. More specifically, the

product term allocator distributes andshares product terms from the AND

plane to OR gates that require them, al-lowing much more flexibility than the

fixed-size OR gates in regular PALs. Theoutput switch matrix enables anymacrocell output (OR gate or flip-flop)

to drive any I/O pin connected to thePAL-like block, again providing greater

flexibility than a PAL, in which eachmacrocell can drive only one specific

I/O pin. Mach 4s combination of in-sys-tem programmability and high flexibil-ity allow easy hardware design changes.

ANDplane

Output

switchmatrix

Inputswitchmatrix

16 834

Clock generator

I/Ocells

I/O (8)

16

16

PTallocator,

OR,EXOR

Output/buried

macrocells

(flip-flops)

80 16

Centralswitchmatrix

PAL-like block

Figure 12 . Mach 4 34V16 PAL-like block.

Generic logicblocks

Output

routingpools

AND Product MacrocellsGlobal routing pool


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directs from 0 to 16 product terms toeach of 32 OR gates. The feedback pathfrom the macrocell outputs to the pro-

grammable interconnect matrix con-tains 32 wires. This means that a

macrocell can be buried (not drive anI/O pin), and yet the I/O pin that the

macrocell would have driven can still

serve as an input. This capability is an-other type of flexibility available in PAL-

like blocks but not in normal PALs.

Xilinx XC7000. Although primarily amanufacturer of FPGAs, Xilinx also of-

fers the XC7000 series of CPLDs. The twomain XC7000 families are the 7200 se-ries (originally marketed by Plus Logic

as Hiper EPLDs) and the 7300 series de-veloped by Xilinx. The 7200s are mod-

erately small devices with about a 600to 1,500 gate capacity, and they offer

speed performance of about 25-ns pin-to-pin delays. Each chip consists of acollection of SPLD-like blocks contain-

ing nine macrocells each Unlike those

32 (macrocellsand I/O pins)

Clock (4)

I/Os

I/Os

I/Os

I/Os

I/Os

I/Os

I/Os

I/Os

I/O

I/O

I/O

I/O

36 86

12

3

16

0-16 inputs

0

OR, bypassable(D, T, latch)flip-flop,tristate buffer

PTallocator

ANDPIM

Figure 14 . Cypress Flash370 architecture. (PIM: programmable interconnect matrix.)

ClockIn

I/OI/OI/OI/O

I/O I/O I/O I/O

Global interconnect matrix

CFB

CFB

CFB

CFB

CFB

CFB

CFB

CFB


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all other CPLDs: Instead of containingAND/OR logic, a CFB can serve as a10-ns SRAM block. Figure 15b shows a

CFB configured as a PAL, and Figure15c shows another configured as an

SRAM. In the SRAM configuration, thePAL block becomes a 128-word by 10-

bit read/write memory. Inputs that

would normally feed the AND plane inthe PAL become address lines, data

lines, or control signals for the memo-ry. Flip-flops and tristate buffers are still

available in the SRAM configuration.In the Flashlogic device, the AND/OR

logic planes configuration bits areSRAM cells connected to EPROM orEEPROM cells. Applying power loads

the SRAM cells with a copy of the non-volatile EPROM or EEPROM, but the

SRAM cells control the chips configu-ration. The user can reconfigure the

chips in system by downloading new in-formation into the SRAM cells. The usercan make the SRAM cell reprogram-

ming nonvolatile by writing the SRAM

well into the CPLD category.Nevertheless, we include them here be-

cause they exemplify PLA-based (ratherthan PAL-based) devices and offer larg-

er capacity than a typical SPLD.The PEEL Array logic cell, shown in

Figure 17, includes a flip-flop, config-urable as D, T, or JK, and two multi-plexers. Each multiplexer produces a

logic cell output either registered or

can exploit wide AND/OR gates and do

not need a large number of flip-flops aregood candidates for CPLD implemen-tation. Finite state machines are an ex-

cellent example of this class of circuits.A significant advantage of CPLDs is that

they allow simple design changesthrough reprogramming (all commer-

cial CPLD products are reprogramma-ble). In-system programmable CPLDseven make it possible to reconfigure

hardware (for example change a pro-

Inputpins

80 ANDterms

80 OR

terms

I/Opins

Arraylogic cells

80

Group of foursum terms

Figure 16 . ICT PEEL Array architecture.

Globalclock

Foursum

terms

To ANDarray

To I/Opins

Global reset

Global preset

D,T,J Q

K

P

R

Figure 17 . ICT PEEL Array logic cell

structure.


11/16


2,000 to more than 15,000 equivalentgates. The XC5000 family provides sim-ilar features at a more attractive price

with some penalty in speed. Xilinx hasrecently announced an antifuse-based

FPGA family, the XC8100. The XC8100has many interesting features, but since

it is not yet in widespread use, we do

not discuss it here.The XC4000 features a configurable

logic block (CLB) based on lookup ta-bles. A lookup table is a 1-bit-wide mem-

ory array; the memory address lines arelogic block inputs, and the 1-bit mem-

ory output is the lookup table output. Alookup table with Kinputs correspondsto a 2K 1-bit memory, and the user can

realize anyK-input logic function byprogramming the logic functions truth

table directly into the memory. In theconfiguration shown in Figure 18, an

XC4000 CLB contains two four-inputlookup tables fed by CLB inputs, and athird lookup table fed by the other two.

This arrangement allows the CLB to im-

SelectorInputs

Clock

VCC

F

G

Q1

Q2

RE

D Q

S

SD Q

RE

State

State

G4

G3

G2

G1

F4

F3

F2

F1

C1 C2 C3 C4

Outputs

Lookuptable

Lookuptable

Lookuptable

CFB

Figure 18 . Xilinx XC4000 CLB.

Verticalchannels

not shown


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short wire segments that span a singleCLB (the number of segments in eachchannel varies for each member of the

XC4000 family), longer segments thatspan two CLBs, and very long segments

that span the chips entire length orwidth. Programmable switches are

available (see Figure 5) to connect CLB

inputs and outputs to the wire segmentsor to connect one wire segment to an-

other. A small section of an XC4000routing channel appears in Figure 19.

The figure shows only the wire seg-ments in a horizontal channelnot the

vertical routing channels, CLB inputsand outputs, and the routing switches.An important point about the Xilinx in-

terconnect is that signals must passthrough switches to reach one CLB

from another, and the total number ofswitches traversed depends on the par-

ticular set of wire segments used. Thus,an implemented circuits speed perfor-mance depends in part on how CAD

tools allocate the wire segments to in-

I/O

I/O

FastTrackinterconnect

Logic array block(8 logic elementsand localinterconnect)

Figure 20 . Altera Flex 8000 architecture.

Cascade inCascade out


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24Control Cascade, carry

Data

4

Logicelement

Logic

element

Logicelement

To adjacentlogic arrayblock

To FastTrackinterconnect

To FastTrack

interconnect

To FastTrackinterconnect

FromFastTrack

interconnect

Localintercon

nect

Logic array block

Figure 22 . Flex 8000 logic array block.

I/O

I/O

Embeddedarrayblock

Embeddedarrayblock

Figure 23 . Altera Flex 10K architecture.D

D

Q

Q

trix

Lookuptable

Lookuptable


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units based on the original ORCAarchitecture.

Actel FPGAs. Actel offers three mainFPGA families: Act 1, Act 2, and Act 3.

Although the three generations havesimilar features, we focus on the most

recent devices. Unlike the FPGAs de-

scribed so far, Actels devices use anti-fuse technology and a structure similar

to traditional gate arrays. Their designarranges logic blocks in rows with hor-

izontal routing channels between adja-cent rows (Figure 25). Actel logic

blocks, based on multiplexers, aresmall compared to those based onlookup tables. Figure 26 illustrates the

Act 3 logic block, which consists of anAND and an OR gate connected to a

multiplexer-based circuit block. In com-bination with the two logic gates, the

arrangement of the multiplexer circuitenables a single logic block to realize awide range of functions. About half the

logic blocks in an Act 3 device also con-

to several other FPGAs: Like XilinxFPGAs, it has an array-based structure;

like Actel FPGAs, its logic blocks usemultiplexers; and like Altera Flex 8000s,

its interconnect consists only of longlines. The pASIC2 is a recently intro-duced enhanced version, which we will

not discuss here Cypress also offers de-

LogicblockrowsRouting

channels

I/O blocks

I/O blocks

I/Oblocks

I/Oblocks

Figure 25 . Actel FPGA structure.

Inputs OutputMultiplexer-based

circuit block


15/16


ing layer, and a metal bottom layer.Compared to Actels PLICE antifuse,ViaLink offers very low on-resistance

about 50 ohms (PLICEs is about 300

lation of entire large hardware systemsvia the use of many interconnectedFPGAs. QuickTurn4 and others have de-

veloped products consisting of theFPGAs and software necessary to parti-

tion and map circuits for hardware em-ulation.

An application only beginning devel-

opment is the use of FPGAs as customcomputing machines. This involves us-

ing the programmable parts to executesoftware, rather than compiling the soft-

ware for execution on a regular CPU. Forinformation, we refer readers to the pro-

ceedings of the IEEE Workshop onFPGAs for Custom Computing Machines,held for the last four years.5

As mentioned earlier, pieces of de-signs often map naturally to the SPLD-

like blocks of CPLDs. However, designsmapped into an FPGA break up into

logic-block-size pieces distributedthrough an area of the FPGA. Dependingon the FPGAs interconnect structure,

the logic block interconnections may

References1. E. Hamdy et al., Dielectric-Based Anti-

fuse for Logic and Memory ICs, Tech. Di-

gest IEEE Intl Electron Devices Meeting,

IEEE, Piscataway, N.J., 1988, pp. 786-789.

2. J. Birkner et al., A Very-High-Speed Field-

Programmable Gate Array Using Metal-

to-Metal Antifuse Programmable

Elements,Microelectronics J., Vol. 23,1992, pp. 561-568.

3. D. Marple and L. Cooke, Programming

Antifuses in CrossPoints FPGA,Proc.

IEEE Intl Custom Integrated Circuits

Conf., IEEE, Piscataway, N.J., 1994, pp.

185-188.

4. H. Wolff, How QuickTurn Is Filling the

Gap,Electronics, Apr. 1990.

5. Proc. IEEE Symp. FPGAs for Custom Com-puting Machines, IEEE Computer Society

Press, Los Alamitos, Calif., 1993-1996.

Suggested rea dingS. Brown et al.,Field-Programmable Gate Ar-

rays, Kluwer Academic Publishers, Nor-

well Mass 1992 A general introduction

QSA1A2A3A4A5A6

D Q

B1B2C1C2

D1D2E1E2

F1F2F3F4F5F6

R

S

QC

QR

FZ

NZ

QZ

AZ

OZ0

1

0

1

0

1

Figure 28 . Quicklogic pASIC logic cell.


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Proc. Design Automation Conference (DAC),

IEEE CS Press.

FPGA Symp. Series: Third Intl ACM Symp.

Field-Programmable Gate Arrays (FPGA

95)andFourth Intl ACM Symp. Field-Pro-

grammable Gate Arrays (FPGA 96),

Assoc. for Computing Machinery, New

York.

Stephen Brown is an assistant professor of

electrical and computer engineering at the

University of Toronto. He holds a PhD in

electrical engineering from that university;

his dissertation (on architecture and CAD

for FPGAs) won him the Canadian NSERCs

1992 prize for the best doctoral thesis in

Canada. In 1990, the International Confer-ence on Computer-Aided Design awarded

him and coauthor Jonathan Rose a Best Pa-

per award. A coauthor of the book Field-

Programmable Gate Arrays, he has also won

four awards for excellence in teaching elec-

trical engineering, computer engineering,

and computer science courses. Brown is

the general and program chair for the

Fourth Canadian Workshop on Field-Pro-

grammable Devices (FPD 96), and is on the

Technical Program Committee for the Sixth

International Workshop on Field-Program-

mable Logic (FPL 96). He is a member of

the IEEE and the Computer Society.

Jonathan Rose is an associate professor

of electrical and computer engineering at

the University of Toronto. His research in-

terests are in the area of architecture and

CAD for field-programmable gate arrays

and systems. He coauthored the bookField-

Programmable Gate Arrays . Rose holds a

PhD in electrical engineering from the Uni-

versity of Toronto. He is the general chair

of the Fourth International Symposium on

FPGAs (FPGA 96) and serves on the tech-

nical program committee for the Sixth

International Workshop on Field-Program-

mable Logic. In 1990, ICCAD awarded himand coauthor Stephen Brown a Best Paper

award. He is a member of the IEEE, the

Computer Society, the Association for

Computing Machinery, and SIGDA.

Direct questions concerning this article

to Stephen Brown, Dept. of Electrical and

Computer Engineering, Univ. of Toronto, 10

Kings College Rd., Toronto, ONT, Canada

M5S 3G4; [email protected].

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