© LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 1 CPLD Vs. FPGA Positioning...

© LATTICE SEMICONDUCTOR CORPORATION

CPLD VS FPGA

February, 02

1

CPLD Vs. FPGA Positioning Presentation


CPLD VS FPGA

February, 02

2

Agenda

• Architecture Descriptions– CPLD

– FPGA

– Advantages / Disadvantages

• Gate Counting

• Common Terms

• Positioning


CPLD VS FPGA

February, 02

3

Basic Definitions

• CPLD– Course Grained Architecture

– Best for Wide, Fast Function Processing

– Relatively Small Designs

• FPGA– Fine Grained Architecture

– Best for Narrow / Pipelined Functions

– Large DesignsLUT

4LUT LUT


CPLD VS FPGA

February, 02

4

FPGA Architecture

FPGACPLD

Global Routing Pool(GRP)

BoundaryScan

Interface

GO

E0

GO

E1

SET/RESET

TDI

TC

KT

MS

TDO

CL

K 1

CL

K 0

1 CL

K 3

1 CL

K 2

VCCIO

Input Bus

Generic Logic Block

Input Bus

Generic Logic Block

Input Bus

Input BusInput Bus Input Bus

Generic Logic Block

Generic Logic Block

Generic Logic Block

Generic Logic Block

Inp

ut B

us

Gen

eric L

og

ic Blo

ck

Inp

ut B

us

Gen

eric L

og

ic Blo

ck

Inp

ut B

us

Inp

ut

Bu

s

Gen

eric L

og

ic Blo

ck

Gen

eric

L

og

ic B

lock

Gen

eric

L

og

ic B

lock

Gen

eric

L

og

ic B

lock

Inp

ut

Bu

sIn

pu

t B

us

I/O

0 /

TO

EI/

O 1

I/O

2I/

O 3

I/O

20

I/O

21

I/O

22

I/O

23

I/O

24

I/O

25

I/O

26

I/O

27

I/O

44

I/O

45

I/O

46

I/O

47

I/O

48

I/O

49

I/O

50

I/O

51

I/O

68

I/O

69

I/O

70

I/O

71

I/O 72I/O 73I/O 74I/O 75

I/O 92I/O 93I/O 94I/O 95

I/O 96I/O 97I/O 98I/O 99

I/O 116I/O 117I/O 118I/O 119

I/O 120I/O 121I/O 122I/O 123

I/O 140I/O 141I/O 142I/O 143

I/O

167

I/O

166

I/O

165

I/O

164

I/O

147

I/O

146

I/O

145

I/O

144

I/O

191

I/O

190

I/O

189

I/O

188

I/O

171

I/O

170

I/O

169

I/O

168

I/O

215

I/O

214

I/O

213

I/O

212

I/O

195

I/O

194

I/O

193

I/O

192

I/O 239I/O 238I/O 237I/O 236

I/O 219I/O 218I/O 217I/O 216

I/O 263I/O 262I/O 261I/O 260

I/O 243I/O 242I/O 241I/O 240

I/O 287I/O 286I/O 285I/O 284

I/O 267I/O 266I/O 265I/O 264


CPLD VS FPGA

February, 02

5

High Density Logic Overview

• Field Programmable Gate Arrays– Small Logic Building Blocks

– Register Intensive

– Distributed Interconnect

– Slower pin to pin performance, due to lots of routing, but pipelining can help

– Good at “Narrow Gating” Funcitions

» Datapath

» Random Logic

• High-Density or Complex PLDs– Large Logic Building Blocks

– PLD-Like Architectures

– Centralized Interconnect

– Fast Predictable Performance

– Good at “Wide Gating” Functions

» State Machines

» Counters

A B

C

FPGA HDPLD or CPLD

FPGAs and CPLDs Can Compliment One Another In the Same Design!


CPLD VS FPGA

February, 02

6

Performance

• FPGA - 4 input Look Up Table (LUT)– Two possible implementations

» Pipelining (preferred)

• High internal frequency achievable higher latency

» Two levels of logic

• Lower latency, but high frequencies not achievable

• CPLDs have wide fan in – Single level allows high frequency AND low

latency

– Very small functions burn logic

LUT

LUT

LUT

4

4

4

LUT4

Loca

l In

terc

onne

ct

RowInterconnect

Loca

l In

terc

onne

ct

LUT4

LUT4

LUT4

LE

LE

LE

Logic68

Macrocell


CPLD VS FPGA

February, 02

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Predictability and Delay

• Row / column design of FPGA– Design changes potentially changes routing

– Routing changes result in timing changes

– Larger delta in I/O to I/O delay

» Design for worst case delay

• Centralized routing of CPLDs– Consistent Routing through GRP

– All GRP lines equally loaded

– Re-route has minimal effect on timing

– Wide inputs results in fewer paths

» Higher speed

» Better predictability


CPLD VS FPGA

February, 02

8

FPGA Architecture

• FPGAs use fine grain logic blocks– Many of these logic blocks are used to implement logic functions due to fine grain

blocks,

» 16 LBs for 16-Bit adder

• FPGAs Work Best With One - hot encoding for state functions– Fine Grain / Abundance of Registers makes One-Hot a good fit

Register

Register

Register

Logic

Logic


CPLD VS FPGA

February, 02

9

FPGA EPROM

• Most FPGAs are volatile SRAM

• Devices are reprogrammed on power-up– Program can be stored in companion, EPROM next to FPGAs

– Device can be programmed with P via Flash programming

– Logic is not available when power is initially applied

FPGAEPROM or P


CPLD VS FPGA

February, 02

10

FPGA Vs CPLD Logic Element

• FPGA Has a Basic, Fine Grain Logic Element– Typical FPGA has 4 Inputs and 8 Product Terms Per Logic Element

– Wide Designs Speed Limitation Can be Overcome with Pipelining

• CPLD Has Complex Logic Element– 5KVG Family has 68 Inputs and 32 Product Terms Per Logic Element

– The CPLD Has Less Registers but uses these registers more efficiently

– Simple Designs Use up the Registers and Logic Elements are Under Utilized

Logic Element

8 PTs

FPGA

4 1

Logic Element

32 PTs

CPLD

68 1

CPLD vs FPGA Input Ratio = 17 : 1

CPLD vs FPGA Product Term Ratio = 4 : 1


CPLD VS FPGA

February, 02

11

Technology Comparisons

Feature E2CMOS Flash SRAM Antifuse

Reprogrammability Yes Yes Yes NO

In-System ProgrammableYes Yes Yes NO (Volatile)

Program Time Fast Med. Fast Slow

Erase Time Fast Slow Fast N/A (OTP)

Testability Full Full Full Limited

External Hardware No No EPROM Pgmr


CPLD VS FPGA

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Gate Counting


CPLD VS FPGA

February, 02

13

CPLD Vs. FPGA Fitting

• Number of PLD Gates or Registers Doesn’t Tell the Entire Story, The Application Does

– Even among equivalent product types, Gate count is “specsmanship”, the only real way to see if a design will fit or fit better is to run it!

• Applications Needing High Speed and Predictability Should Use CPLD

• Large Register Intensive Logic Applications Should Use FPGA

• Most Designs Have a Mixture of Qualities that Could Fit Either, So Both CPLD and FPGA Should Be Considered


CPLD VS FPGA

February, 02

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A Gate Is a Gate Is a Gate

• FPGA and CPLD Both Build Gates Out of Transistors

• The Basic CMOS Gates Are the Same in Both Architectures– Inverter

– NAND

– NOR

• Example NAND

B

A

F

VCC

B

AF


CPLD VS FPGA

February, 02

15

CPLD Gate Count Vs FPGA Gate Count

• It is Difficult to Compare Apples to Apples

• What Is an “Equivalent PLD Gate”?– A Simple PLD Gate Is Considered 2-input AND

• How Many Simple PLD Gates to Build an 8-input AND?– Seven

• FPGA Vendors Have Different Standards for Gate Counts– A Higher Percentage of Gates Are Used for Interconnect in FPGA and

some Vendors count Memory in Total Gate Count

• The First Order of Importance Is to Have Enough Registers to Compete, Not Fight Over Gate Counts

• The Only Way To Know if a Design Fits is to FIT IT!!!


CPLD VS FPGA

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Terms


CPLD VS FPGA

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17

FPGA Terms

• FPGA - Field Programmable Gate Array

• SRAM - Static RAM – Program stored in outside EPROM, intelligent controller or through JTAG Port,

FPGAs must be reprogrammed on every power-up

• Configuration EPROM– External hardware used to hold FPGA programming file

• ICR - In-Circuit Reconfigurability

• Anti-fuse - One-Time Programmable (OTP)– (Quicklogic and Actel)

• Interconnect - Basic Routing element– FPGAs rely on a Fine Grain routing structure

• LUT - Look-Up Table– 4-input SRAM based look-up table produces the output of any 4 input function

• LE/CLB - Logic Element – Smallest logic unit. 4 input Look-Up Table, Carry/cascade chains, register and

register control signals


CPLD VS FPGA

February, 02

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FPGA Terms

• LAB - Logic Array Block (Altera)– Consists of 8 LEs and associated control signals and routing

• EAB - Embedded Array Block (Altera)– High level building block, includes Ram and registers

• One Hot Encoding– When single registers (bits) are used to represent states instead of the common binary

method

– Example: 20 state-state machine

» One Hot: 20 registers (bits)

» Binary: 5 registers (bits)

• Pipeline– Putting functions in an “assembly line” format. Small portions done quickly allows a high

clock speed and results at short intervals. The drawback is results take longer to get from input to output (latency)

Register Register Register Register

1 Clk Delay 3 Clk Delay2 Clk DelayNo Clk Delay


CPLD VS FPGA

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FPGA Terms

• SoC– System on a Chip

• MPI– Microprocessor Interface

• EBR– Embedded Block RAM

• PLC– Programmable Logic Cell

• PIO– Programmable Input/Output Cells

• CIB– Common Interface Block

• PFU– Programmable Function Unit

• SLIC– Decoder / PAL like logic


CPLD VS FPGA

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Positioning


CPLD VS FPGA

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CPLDProduct Positioning

Mem

ory

Micro-Processor

ASSP

ROM

ASIC

ChipSet

SPEED

Mach

5K5K

FPGA/FPSC

GDX

DENSITY

FPGA/FPSC

GDX


CPLD VS FPGA

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CPLD Product Positioning

Mach/Mach4K• High Speed Decode

• Small High speed Control

• ASIC Fixes

• PCI Arbitration

FPGA / FPSC• Data Path

• Logic consolidation

• DSP Functions

5KVG• Wide Decode

• Buss Control (16-32-64 bit Buses) In One Level

• Complex High Speed Control

• Fast Muxing

Speed

Den

sit

y


CPLD VS FPGA

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CPU Requirements

Propagation Delay

Den

sit

y

CPU

5K Family

Fast Slow

M4K Family

FPGAs

Fast address decodeand Control logicBus Arbitration

Wide DatapathSwitching

Fast Control / Datapath

DatapathS

mal

lLa

rge

FPSCs


CPLD VS FPGA

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Some CPLDs Can Do Large Designs

• Some Small Designs Fit Better in Large CPLDs, Some Designs Require FPGA features

FPGA

Mach4K

5KVG

CPLD


CPLD VS FPGA

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Summary

• Understand the Design – Don’t Assume the Best Hardware is an FPGA or CPLD

• CPLDs Are Best Suited for:– Wide Designs

– Speed Critical, Low Latency, Low Skew

– Relatively Small

– Hot-Plugable

• FPGAs Are Best Suited for:– Large Register Intensive Designs

– Narrow Gating, Pipeline-able

• Fit the Design to Determine the Size in Our Devices

© LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 1 CPLD Vs. FPGA Positioning...

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Transcript of © LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 1 CPLD Vs. FPGA Positioning...