Introduction to CPLD&FPGA

8/2/2019 Introduction to CPLD&FPGA

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CPLD &FPGA ARCHITECTURES

P.PRASAD RAO


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PLDs

SPLDs CPLDs

PLAsPROMs PALs GALs etc.

The Design Warriors Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright 2004 Mentor Graphics Corp. (www.mentor.com)

First Programmable Logic Devices


3/74

Programmable logic device as a

black box

Logic gatesand

programmableswitches

Inputs

(logic variables)Outputs

(logic functions)


4/74

General structure of a PLA

(Programmable Logic Array)

f1

AND plane OR plane

Inputbuffers

& inverters

P1

Pk

fm

x1 x2 xn

x1 x1 xn xn


5/74

Gate-level diagram of a PLA

f1

P1

P2

f2

x1 x2 x3

OR plane

Programmable

AND plane

connections

P3

P4


6/74

Customary schematic for a PLA

f1

P1

P2

f2

x1 x2 x3

OR plane

AND plane

P3

P4


7/74

Programmable Array Logic

f1

P1

P2

f2

x1 x2 x3

AND plane

P3

P4


8/74

Macrocell at the output of PAL

f1

To AND plane

D Q

Clock

Select Enable

Flip-flop

C


9/74

Programmable

Interconnectmatrix

Input/output pinsSPLD-like

blocks



A generic structure of CPLD

(Complex Programmable Logic Device)


10/74

Structure of a CPLD

PAL-likeblock

I/Ob

lock

PAL-likeblock

I/Oblock

PAL-likeblock

I/Ob

lock

PAL-likeblock

I/Oblock

Interconnection wires


11/74

A section of a CPLD

D Q

D Q

D Q

PAL-like block


12/74

100 wires

30 wires

Programmablemultiplexer

interconnect matrix and simple PAL-like

blocks




13/74

Programmableinterconnect

Programmablelogic blocks



General structure of an FPGA


14/74

CLB CLB

CLB CLB

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Configurable logic block (CLB)



Xilinx CLB


15/74

CLB Structure


16/74

16-bit SR

16x1 RAM

4-inputLUT

LUT MUX REG

Logic Cell (LC)

16-bit SR

16x1 RAM

4-inputLUT

LUT MUX REG

Logic Cell (LC)

Slice



Xilinx CLB Slice


17/74

CLB Slice Structure Each slice contains two sets of the

following: Four-input LUT

Any 4-input logic function,

or 16-bit x 1 sync RAM (SLICEM only)

or 16-bit shift register (SLICEM only)

Carry & Control Fast arithmetic logic

Multiplier logic

Multiplexer logic

Storage element Latch or flip-flop

Set and reset

True or inverted inputs

Sync. or async. control


18/74

LUT (Look-Up Table)Functionality

Look-Up tablesare primaryelements forlogicimplementation

Each LUT canimplement anyfunction of4 inputs

x1 x2 x3 x4

y

x1 x2

y

LUT

x1x2x3x4

y

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

0100010

101001100

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

1111111

111110000

x1 x2 x3 x4

y

x1 x2 x3 x4

y

x1 x2

y

x1 x2

y

LUT

x1x2x3x4

y

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

0100010

101001100

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

0100010

101001100

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

1111111

111110000

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

1111111

111110000

5 Inp t F nctions implemented


19/74

5-Input Functions implementedusing two LUTs

One CLB Slice can implement any function of 5 inputs

Logic function is partitioned between two LUTs

F5 multiplexer selects LUT

A4

A3

A2

A1WS DI

D

LUT

ROMRAM

1

0

F4

F3F2

F1

A4

A3A2

A1

WS DI

D

LUT

ROM

RAM

F5

GXOR

G

nBX

BX

1

0

BX

X

F5

A4

A3

A2

A1WS DI

D

LUT

ROMRAM

A4

A3

A2

A1WS DI

D

LUT

ROMRAM

1

0

1

0

F4

F3F2

F1

A4

A3A2

A1

WS DI

D

LUT

ROM

RAM

A4

A3A2

A1

WS DI

D

LUT

ROM

RAM

F5

GXOR

G

F5

GXOR

G

nBX

BX

1

0

nBX

BX

1

0

BX

X

F5

5 I t F ti i l t d i t


20/74

5-Input Functions implemented using two

LUTs

LUTLUT

X5 X4 X3 X2 X1 Y

0 0 0 0 0 0

0 0 0 0 1 1

0 0 0 1 0 0

0 0 0 1 1 0

0 0 1 0 0 1

0 0 1 0 1 1

0 0 1 1 0 0

0 0 1 1 1 0

0 1 0 0 0 1

0 1 0 0 1 0

0 1 0 1 0 0

0 1 0 1 1 1

0 1 1 0 0 1

0 1 1 0 1 1

0 1 1 1 0 1

0 1 1 1 1 1

1 0 0 0 0 0

1 0 0 0 1 0

1 0 0 1 0 0

1 0 0 1 1 0

1 0 1 0 0 0

1 0 1 0 1 0

1 0 1 1 0 01 0 1 1 1 1

1 1 0 0 0 0

1 1 0 0 1 1

1 1 0 1 0 0

1 1 0 1 1 1

1 1 1 0 0 0

1 1 1 0 1 1

1 1 1 1 0 0

1 1 1 1 1 0

LUTLUT

OUT


21/74

16-bit SR

16 x 1 RAM

4-input LUT



Xilinx Multipurpose LUT


22/74

16-bit SR

flip-flop

clock

mux

y

qe

a

b

c

d

16x1 RAM

4-inputLUT

clock enable

set/reset



Simplified view of a Xilinx Logic Cell


23/74

RAM16X1S

O

D

WE

WCLKA0

A1

A2

A3

RAM32X1S

O

DWE

WCLKA0A1A2A3A4

RAM16X2S

O1

D0

WE

WCLKA0

A1

A2

A3

D1

O0

=

=

LUT

LUT or

LUT

RAM16X1D

SPO

D

WE

WCLK

A0

A1

A2

A3

DPRA0 DPO

DPRA1

DPRA2

DPRA3

or

Distributed RAM

CLB LUT configurable asDistributed RAM A single LUT equals 16x1

RAM

Two LUTs Implement Singleand Dual-Port RAMs

Cascade LUTs to increaseRAM size

Synchronous write

Synchronous/Asynchronous read Accompanying flip-flops used

for synchronous read


24/74

D Q

CE

D Q

CE

D Q

CE

D Q

CE

LUT

INCE

CLK

DEPTH[3:0]

OUTLUT =

Shift Register

Each LUT can beconfigured as shiftregister Serial in, serial out

Dynamically addressabledelay up to 16 cycles

For programmablepipeline

Cascade for greater cycledelays

Use CLB flip-flops to adddepth


25/74

Shift Register

Register-rich FPGA

Allows for addition of pipeline stages to increasethroughput

Data paths must be balanced to keep desiredfunctionality

64

Operation A

4 Cycles 8 Cycles

Operation B

3 Cycles

Operation C

64

12 Cycles

3 Cycles

9-Cycle imbalance


26/74

COUT

D Q

CK

S

REC

D Q

CK

REC

O

G4G3G2G1

Look-Up

TableCarry

&

Control

Logic

O

YB

Y

F4F3F2F1

XB

X

Look-Up

Table

F5IN

BY

SR

S

Carry

&

Control

Logic

CINCLKCE

SLICE

Carry & Control Logic


27/74

Each CLB contains separatelogic and routing for the fastgeneration of sum & carrysignals Increases efficiency and

performance of adders,subtractors, accumulators,comparators, and counters

Carry logic is independent ofnormal logic and routingresources

Fast Carry Logic

LSB

MSB

CarryLog

ic

Routing


28/74

Accessing Carry Logic

All major synthesis tools can infer carrylogic for arithmetic functions

Addition (SUM


29/74

Input/Output Blocks(IOBs)


30/74

Basic I/O Block Structure

D

EC

Q

SR

D

EC

Q

SR

D

EC

Q

SR

Three-StateControl

Output Path

Input Path

Three-State

Output

Clock

Set/Reset

Direct Input

RegisteredInput

FF Enable

FF Enable

FF Enable


31/74

IOB Functionality

IOB provides interface between thepackage pins and CLBs

Each IOB can work as uni- or bi-directionalI/O

Outputs can be forced into HighImpedance

Inputs and outputs can be registered

advised for high-performance I/O

Inputs can be delayed

RAM Blocks and Multipliers in Xilinx


32/74

RAM blocks

Multipliers

Logic blocks

RAM Blocks and Multipliers in XilinxFPGAs




33/74

uP

(a) One embedded core (b) Four embedded cores

uP uP

uP uP



Embedded Microprocessor Cores


34/74


35/74

Clock signal fromoutside world

Clock

treeFlip-flops

Special clockpin and pad

A simple clock tree




36/74



Daughter clocksused to drive

internal clock treesor output pins

Clock

Manageretc.



Clock Manager


37/74

Ideal clock signal

1 2 3 4

Real clock signal with jitter

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Superimposed cycles



Jitter


38/74


with jitter


Clean daughter

clocks used to driveinternal clock trees

or output pins

ClockManager

etc.



Removing Jitter

S


39/74

1.0 x original clock frequency

2.0 x original clock frequency

.5 x original clock frequency



Frequency Synthesis

Ph hif i


40/74

Figure 4-20

0o Phase shifted

90o Phase shifted

180o Phase shifted

270o Phase shifted



Phase shifting

R i Cl k Sk


41/74

Main (mother) clock

Untreated daughter clock

De-skewed daughter clock

1 2 3 4

1 2 3 4

1 2 3



De-skewed daughterclocks used to driveinternal clock trees

or output pins

Daughter clock (monitoreddownstream of the clock manager)

fed back to special input



Removing Clock Skew


42/74

Programming ReconfigurableLogic Devices

A Fusible Link Technologies:


43/74

a

Fat

Logic 1

y = 0 (N/A)&

Faf

b

Fbt

Fbf

Pull-up resistors

NOT

NOT

AND

Fuses



A Fusible Link Technologies:Unprogrammed Device

A Fusible Link Technologies:


44/74

a

Fat

Logic 1

y = a & !b&

b

Fbf

Pull-up resistors

NOT

NOT

AND



A Fusible Link Technologies:Programmed Device

An Antifuse Technology:


45/74

a

Logic 1

y = 1 (N/A)&

b

Pull-up resistors

Unprogrammedantifuses

NOT

NOT

AND



An Antifuse Technology:Unprogrammed Device

An Antifuse Technology:


46/74

a

Logic 1

y = !a & b&

b

Pull-up resistors

Programmedantifuses

NOT

NOT

AND



An Antifuse Technology:Programmed Device

G i A tif


47/74

(a) Before programming

Substrate

Metal

Oxide

Metal

Amorphous silicon column

(b) After programming

Polysilicon via



Growing an Antifuse

EPROM T h l


48/74

control gate

source drain

control gate

floating gate

source drain

(a) Standard MOS transistor (b) EPROM transistor

Siliconsubstrate

Silicondioxide

Sourceterminal

Control gateterminal

Drainterminal

Sourceterminal

Control gateterminal

Drainterminal



EPROM Technology

A EPROM T i t B d M C ll


49/74

Logic 1

Pull-up resistor

Row(word) line

Column(data) line

EPROMTransistor

Logic 0The Design Warriors Guide to FPGAs

Devices, Tools, and Flows. ISBN 0750676043Copyright 2004 Mentor Graphics Corp. (www.mentor.com)

An EPROM Transistor-Based Memory Cell

EEPROM T h l


50/74

E2PROM Cell

Normal

MOS transistor

E2PROM

transistor



EEPROM Technology

St ti RAM b d T h l


51/74

SRAM



Static RAM-based Technology

Summary of Programming Technologies


52/74

Technology Symbol

Predominantly

associated with ...

Fusible-link SPLDs

Antifuse FPGAs

EPROM SPLDs and CPLDs

E2PROM/FLASH

SPLDs and CPLDs(some FPGAs)

SRAM FPGAs (some CPLDs)SRAM



Summary of Programming Technologies

The Design Warriors Guide to FPGAsD i T l d Fl ISBN 0750676043


53/74

State-of-the-art

Feature

Technology node

SRAM AntifuseE2PROM /

FLASH

One or moregenerations behind

One or moregenerations behind

FastReprogramming

speed (inc.erasing)

----3x slower

than SRAM

YesVolatile (must

be programmedon power-up)

NoNo

(but can be if required)

MediumPower

consumptionLow Medium

Acceptable(especially when usingbitstream encryption)

IP Security Very Good Very Good

Large(six transistors)

Size ofconfiguration cell

Very smallMedium-small

(two transistors)

NoRad Hard Yes Not really

NoInstant-on Yes Yes

YesRequires externalconfiguration file

No No

Yes(very good)

Good forprototyping

NoYes

(reasonable)

Yes

(in system)Reprogrammable No

Yes (in-system

or offline)

Devices, Tools, and Flows. ISBN 0750676043Copyright 2004 Mentor Graphics Corp. (www.mentor.com)

Configuration of SRAM based FPGAs


54/74

Configuration data inConfiguration data out

= I/O pin/pad

= SRAM cell



Configuration of SRAM based FPGAs


55/74

FPGA Design Flow


56/74

Design flow (1)

Design and implement a simple unit permitting to

speed up encryption with RC5-similar cipher with

fixed key set on 8031 microcontroller. Unlike in

the experiment 5, this time your unit has to be able

to perform an encryption algorithm by itself,

executing 32 rounds..

LibraryIEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity RC5_core is

port(clock, reset, encr_decr: in std_logic;

data_input: in std_logic_vector(31downto0);

data_output: out std_logic_vector(31downto0);

out_full: in std_logic;

key_input: in std_logic_vector(31downto0);

key_read: out std_logic;

);

end AES_core;

Specification (Lab Experiments)

VHDL description (Your Source Files)

Functional simulation

Post-synthesis simulationSynthesis


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Design flow (2)

Implementation

Configuration

Timing simulation

On chip testing


58/74

Synthesis


59/74

Synthesis Tools

and others

Synplify Pro Xilinx XST

Logic Synthesis


60/74

architecture MLU_DATAFLOW of MLU is

signal A1:STD_LOGIC;

signal B1:STD_LOGIC;

signal Y1:STD_LOGIC;

signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;

begin

A1


61/74

Implementation


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Implementation

After synthesis the entire implementationprocess is performed by FPGA vendortools


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Translation

Translation

UCF

NGD

EDIF NCF

Native Generic Database file

Constraint Editor

User Constraint File

NativeConstraint

File

Electronic Design

Interchange Format

Circuit netlist Timing Constraints

Synthesis


65/74

Pin Assignment

LAB2

CLOCK

CONTROL(0)

CONTROL(2)

CONTROL(1)

RESET

SEGMENTS(0)

SEGMENTS(1)

SEGMENTS(2)

SEGMENTS(3)

SEGMENTS(4)

SEGMENTS(5)

SEGMENTS(6)

H3

K2G5

K3H1K4

G4

H5

H6

H2

P10

B10FPGA


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67/74

Circuit netlist


68/74

Mapping

LUT2

LUT3

LUT4

LUT5

LUT1FF1

FF2

LUT0

FPGA


69/74

PlacingCLB SLICES

G

FPGA


70/74

RoutingProgrammable Connections


71/74

Configuration

Once a design is implemented, you must createa file that the FPGA can understand

This file is called a bit stream: a BIT file (.bitextension)

The BIT file can be downloaded directly to theFPGA, or can be converted into a PROM file

which stores the programming information


72/74

Report files


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Virtex 4

Source: [Xilinx, Inc.]


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Three Virtex-4 Families

Application-Specific Modular BlockArchitecturemakes it easier to create sub-families

LX has logic, BlockRAMs, DSP-Blocks, I/O

SX has more DSP Blocks and BlockRAMs,less logic

FX adds powerful system features:

PPC, Ethernet controller, 11 Gbpstransceivers

Introduction to CPLD&FPGA

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