Flip-Flop Summaryp p y

D flip-flop

SR flip-flop

JK fli flJK flip-flop

T flip-flopp p

Latch VS Flip-Flopp p

D flip-flopD Latch

Master-slave

Edge trigger

Simple cell

Level trigger Edge trigger

Clock, 50% duty

Level trigger

Pulse clock

CostRace condition

D FF

D FF

D FF

D FF

SR FF

SR FF

JK FF

JK FF

T FF

T FF

T FF

T FF

ALL

Using Xilinx ISE 9.2igProject with Schematic

1. New Project/Open Project

2. New Source/Add Source

3 Schematic3. Schematic

4. Synthesize

5 C t S b l S b l Wi d5. Create Symbol, Symbol Wizard

6. Implement Design

7. Create Test Bench WaveForm

8. Simulate Post-Place & Route Model

Using Xilinx ISE 9.2igProject with Schematic

Save All filesSave All files

Out-of-Date Symbols

Crash, recover?

SCH schematic file.SCH schematic file

.SYM symbol file

TBW T tb h fil.TBW Testbench file