Chapter 11 Latches and Flip-FlopsCombinational vs Sequential LogicUngated LatchesGated...
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Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips Chapter 11 Latches and Flip-Flops SKEE1223 Digital Electronics Mun’im/Arif/Izam FKE, Universiti Teknologi Malaysia December 8, 2015
Transcript of Chapter 11 Latches and Flip-FlopsCombinational vs Sequential LogicUngated LatchesGated...
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
Chapter 11Latches and Flip-FlopsSKEE1223 Digital Electronics
Mun’im/Arif/Izam
FKE, Universiti Teknologi Malaysia
December 8, 2015
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
Types of Logic Circuits
Combinational logic:Output depends solely on the present input.Has no memory.
Sequential logic:Output depends not only on the present input and also onpast history of inputs.Has memory.Synchronous sequential logic
Use a ‘clock’ signal to regulate operations.Simpler to design
Asynchroous sequential logicDoes not use a clock.
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
Types of Memory Elements
Ungated LatchesGated LatchesFlip-flops
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
Bistable Circuits
Bistable circuitAny circuit stable in 0 or 1Has memoryValue does not change by itselfSimplest bistable circuit : cascaded inverters
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
SR Latch
SR = set/resetReplace inverters in prev page with NOR gatesWhen S = R = 0, operates exactly as cascaded inverters
S R
Q
Q
Q
R
S
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
SR Latch
S
R
Q
Q
Logic symbol.
S R Q(next) Q(next) Action
0 0 Q Q No change0 1 0 1 Reset1 0 1 0 Set1 1 0 0 Forbidden
Characteristic table.
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
SR Latch
S
R
Q
Q
Set Reset SetIllegalinputs
Unknownvalues
Both outputs LOW
Q and Q̄ are always oppositeS = R = 0 holds previous valueS = 1, R = 0 sets Q to 1S = 0, R = 1 resets Q to 0S = R = 1, both Q and Q̄ goes to 0, → forbidden state
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
S̄R̄ Latch
Same idea as SR latchS and R are active low
Q
Q
R
S
S̄ R̄ Q(next) Q(next) Action0 0 1 1 Forbidden0 1 0 1 Set1 0 1 0 Reset1 1 Q Q No change
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
Gated SR Latch
Q
Q
R
S
EN
S
EN
R
Q
Q
EN = 1enables latchopens gate for SR inputs to cross-coupled gatesworks like ungated SR latch
EN = 0disables latchholds prev stateignores SR inputs
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
Gated SR Latch
S
R
Q
Q
EN
EN S R Q(next) Action0 X X Q No change1 0 0 Q No change1 0 1 0 Reset1 1 0 1 Set1 1 1 X Forbidden
EN
S
R
Q
Set Reset
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
D Latch
Q
Q
D
EN
Q
Q
D
EN
Modify SR latch to avoid SR=11 conditionEN = 1
latch become ‘transparent’input D is passed to output Q after some delay
EN = 0disables latchignores D inputsholds last D input when EN went 1 → 0
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
D Latch
D Q
QEN
EN D Q(next) Action0 X Q Storage state1 0 0 Transparent mode1 1 1 Transparent mode
EN
D
Q
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
Clock Inputs
Synchronous digital systems use a clockClock signal is distributed to all system componentsAll outputs change simultaneously when a clock pulsearrives
Clock.
T1 T2 T3 T4
T1 = T2 = T3 = T4
Not a clock.
T1 ≠ T2 ≠ T3 ≠ T4
T1 T2 T3 T4
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
Parts of a Clock Signal
Clock period
Clock width
Rising edge
Falling edge
Device How it uses the clockLatch Does not use the clock
Gated latch Enabled when clock is highFlip-flop Triggered by rising or falling clock edge
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
Master Slave Flip-Flop
D Q
Q
D Q Q
Q
D
Clock
Master Slave
EN EN
Clock highMaster enabled, slave disabledInput D is transparently passed on to Qmaster
Clock lowMaster disabled, slave enabledQmaster is locked, and read by slaveQslave is updated
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
D Flip-Flop
D Q
Q
Clk D Q(next) Action0 X Q No change1 X Q No change↑ 0 0 Reset↑ 1 1 Set
D
Q
Q
R
S
CLK
Output latch
Reset latch
Set latch
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
D Flip-Flop
D
c
b
Qa
Clock Clk
D
D
D
Q
Q
Clock
D
Qa
Qb
Qc
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
T Flip-Flop
T Q
Q
Clk T Q(next) Action0 X Q No change1 X Q No change↑ 0 Q Hold↑ 1 Q Toggle
D Q
Q
T
Clock
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
JK Flip-Flop
J
K
Q
Q
C S R Q(next) Action0 X X Q No change1 X X Q No change↑ 0 0 Q No change↑ 0 1 0 Reset↑ 1 0 1 Set↑ 1 1 X Toggle
Clock
J
K
Q
Set Reset Reset Toggle Toggle Toggle
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
JK Flip-Flop
J
K
Q
Q
D
Clock
J
K
Q
Q
T
Clock
D Q
QClock
K
J
C
Q
Q
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
Flip-Flop Timing
Flip-flopinput
Clockinput
tSU tH
Flip-flopoutput
tCO
ts – Setup timeThe time a control input must be maintained before theclock transition.
th – Hold timeThe time a control input must be maintained after the clocktransition.
tPCQ – Propagation delay from clock to output changeThe time a flip-flop changes after a clock edge is given
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
74x74 D PET FF
D Q
Q
PR
CLR
Preset Clear D Clock Q(next)1 1 0 ↑ 01 1 1 ↑ 11 1 x 0 Q1 1 x 1 Q0 1 x x 11 0 x x 00 0 x x NA
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
74x76 Master Slave JK FF
J Q
Q
PR
CLR
K
Preset Clear J K Clock Q(next)1 1 0 0 ↑ Q1 1 0 1 ↑ 01 1 1 0 ↑ 11 1 1 1 ↑ Q̄1 1 x x 0,1 Q0 1 x x x 11 0 x x x 00 0 x x x NA
Combinational vs Sequential Logic Ungated Latches Gated Latches Flip-Flops Flip-Flop Chips
SKEE1223
https://www.openlearning.com/courses/SKEE1223x
