Flip Flop
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Transcript of Flip Flop
![Page 1: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/1.jpg)
Latches e Latches e Flip-FlopsFlip-Flops
Circuitos LógicosCircuitos LógicosDCC-IM/UFRJ
Prof. Gabriel P. Silva
![Page 2: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/2.jpg)
Diagrama Geral de um Sistema Digital
![Page 3: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/3.jpg)
“Latch” com Portas NOR
![Page 4: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/4.jpg)
Diagrama de Tempos “Latch” com Portas NOR
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“Gated Latch” c/ portas NOR
Q
Q
R ′
S ′
R
S
Clk
S R
x x
0 0
0 1
1 0
Q( t ) (no change)
0
1
Clk
0
1
1
1
1 1 1
Q t 1 + ( )
Q( t ) (no change)
x
![Page 6: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/6.jpg)
“Gated Latch” c/ portas NOR
S Q
Q
Clk
R
R
Clk
Q
Q
S
1
0
1
0
1
0
1
0
1
0
Tempo
?
?
![Page 7: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/7.jpg)
“Latch” c/ Portas NAND
Dois estados de repouso possíveis quando SET=CLEAR=1
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“Latch” c/ Portas NAND
Quando a entrada SET pulsa para ´0´ força a saída Q para ´1´.
![Page 9: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/9.jpg)
“Latch” c/ Portas NAND
Quando a entrada CLEAR pulsa para ´0´ força a saída Q para ´0´.
![Page 10: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/10.jpg)
“Latch” c/ Portas NAND
![Page 11: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/11.jpg)
“Latch” c/ Portas NAND
![Page 12: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/12.jpg)
Diagrama de Tempos“Latch” com Portas NAND
![Page 13: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/13.jpg)
Aplicação do “Latch”
![Page 14: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/14.jpg)
“Gated SR Latch” com NAND
S
R
Clk
Q
Q
Qual a tabela verdade?
![Page 15: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/15.jpg)
“Gated D Latch” com NAND
Q
S
R
Clk
D (Data)
D Q
Q Clk
Clk D
0 1 1
x 0 1
0 1
Q t 1 + ( )
Q t ( )
Q
![Page 16: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/16.jpg)
“Gated D Latch” com NAND
t 1
t 2
t 3
t 4
Tempo
Clk
D
Q
![Page 17: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/17.jpg)
“Latch” Transparente
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Diagrama de Tempos“Latch” Transparente
![Page 19: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/19.jpg)
VHDL“Latch” Transparente
entity d_latch isport ( d, clk : in bit; q : out bit );
end entity d_latch;
architecture basic of d_latch isbegin
latch_behavior : process isbegin
if clk = ‘1’ thenq <= d after 2 ns;
end if;wait on clk, d;
end process latch_behavior;end architecture basic;
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Sinal de Relógio (Clock)
![Page 21: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/21.jpg)
Flip-Flop
![Page 22: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/22.jpg)
Flip-Flop SC ativado na transição positiva do “clock”
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Diagrama de Tempo Flip-Flop SC
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Flip-Flop SC ativado na transição negativa do “clock”
![Page 25: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/25.jpg)
Circuito Interno Flip-Flop tipo SC
![Page 26: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/26.jpg)
Circuito Detector de Transição
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Flip-Flop JK
![Page 28: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/28.jpg)
Flip-Flop JK
![Page 29: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/29.jpg)
Flip-Flop JKTransição Negativa
![Page 30: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/30.jpg)
Flip-Flop Tipo D
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Diagrama de TemposFlip-Flop Tipo D
![Page 32: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/32.jpg)
Aplicação do Flip-Flop Tipo D
![Page 33: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/33.jpg)
Flip-Flop Tipo D com SET e RESET
![Page 34: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/34.jpg)
Flip-Flop Tipo D com SET e RESET
![Page 35: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/35.jpg)
Temporização
Definição de termoso Relógio: sinal elétrico periódico que provoca a
mudança de estado do elemento de memória; (transição de subida ou descida, nível alto ou baixo)
o Atraso de propagação: tempo máximo depois do evento de relógio (transição de subida ou descida) até a mudança do valor na saída do fl ip-flop (T
PHL e
TPLH
)
o Tempo de setup: tempo mínimo antes do evento de relógio (transição de subida ou descida) em que a entrada precisa estar estável (Tsu)
o Tempo de hold: tempo mínimo depois do evento de relógio (transição de subida ou descida) durante o qual a entrada precisa continuar estável (Th)
![Page 36: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/36.jpg)
Atrasos de Propagação
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Tempo de Setup e Hold
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entrada
clock
T su Th
Temporização
Existe uma “janela” de tempo em torno da subida ou descida do relógio durante a qual a entrada precisa permanecer estável e inalterada para que seja corretamente reconhecida.
![Page 39: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/39.jpg)
clock
entrada
alterandoestável
clock
entrada D Q D Q
Temporização
![Page 40: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/40.jpg)
Todas as medidas são feitas a partir do evento de clock, isto é,
a partir da borda de subida do clock
Especificações de Tempo Típicas
Positive edge-triggered D flip-flopo Tempos de Setup e Hold
o Largura de clock mínima
o Retardos de propagação (0 para 1, 1 para 0, máximo e típico)
Th5ns
25ns
Tplh21ns Tphl
23ns
Tsu20ns
D
CLK
Q
Tsu20ns
Th5ns
![Page 41: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/41.jpg)
probabilidade baixa, mas não nula, de que a saída do FF fique presa
em um estágio intermediário
gráficos no osciloscópio demonstrandofalha de sincronização e eventualdecaimento ao estado permanente
Nível Lógico 0 Nível Lógico 1logic 0
logic 1
Falha de Sincronização
Ocorre quando a entrada do flip-flop muda próximo à borda do clocko FF pode entrar num estado metaestável – nem 0 nem 1
o FF pode permanecer neste estado indefinidamente
![Page 42: Flip Flop](https://reader033.fdocuments.net/reader033/viewer/2022060114/557210dd497959fc0b8dcfa9/html5/thumbnails/42.jpg)
D DQ Qentrada
assíncronaentrada
sincronizada
sistema síncrono
Clk
Lidando com a Falha de Sincronização
Probabilidade da falha não pode ser reduzida a 0, mas pode ser diminuída(1) desacelerar o clock do sistema: isto dá ao sincronizador
mais tempo para entrar em um estado permanente; falha de sincronizacão se torna um grande problema para sistemas de alta velocidade
(2) usar no sincronizador a tecnologia mais rápida possível(3) cascatear dois sincronizadores: isto efetivamente
sincroniza duplamente