Fixed Point Implememnation of Adaptive Filter

7/25/2019 Fixed Point Implememnation of Adaptive Filter

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International Journal of Advanced R

Vol. 3, Issue 1, January 2016

moo FIXED POINT IMP

R.Mythili

Department of ECE

Karpagam college of engineering

Coimbatore, India.

[email protected]

ABSTRACT: The least mean squar

adaptive filter, because of its simpli

LMS algorithm does not support

transformed to a form called d

implementation of the filter .This p

delayed least mean square Adaptive

for that we use a novel partial prod

the time-consuming combinational

area-delay product (ADP) and less

structures, for various filter length

decreased to a great extent using the

INDEX TERMS: LMS Adaptive filt

efficient, low power.

I .INTRODUCTION:

The direct-form LMS adaptive filte

long critical path due to an i

computation to obtain the filter output.

path is needed to be reduced b

implementation when it exceeds the de

period. The LMS algorithm does

pipelined implementation, a variation

Mean Squares (LMS) called delayed L

algorithm which ideally suited for high

adaptive digital filter implementatiowork has been done to implement

algorithm in most efficient way. In t

proposed a 2-bit multiplication cell

efficient adder tree for pipelined i

computation to minimize the critical p

without increasing the number of ada

The existing work on DLMS does no

the fixed point implementation issu

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EMEMNATION OF ADAPTIVE FILTER

Dr.B.Nagaraj

HOD department of ECE

Karpagam college of engineering

Coimbatore, India.

[email protected]

e (LMS) adaptive filter is the most popular and m

ity and superior convergence performance .Since t

ipelined implementation because of its repetitive

layed LMS (DLMS) algorithm, which supports

aper presents an efficient architecture for the imple

filter. For achieving lower adaptation-delay and ar

uct generator and propose an optimized balanced pi

locks of the structure. It is find that the proposed

energy delay product (EDP) than the best of the

. Hence it is clear that the total area- ower consu

proposed method.

rs, fixed point arithmetic, least mean square (LMS) a

involves a

ner-product

The critical

y pipelined

sired sample

not support

of the Least

S (DLMS)

ly pipelined,

. A lot ofthe DLMS

is paper we

nd with an

ner product

ath and area

tion delays.

t discuss on

es, such as

location of radix point, choice

quantisation at various stages

Therefore fixed-point Implemen

proposed design reduce the num

delays along With the area, sampl

energy consumption. The proposed

to be more efficient in terms of

product (PDP)and energy-d

(EDP)compared to the exist ing str

to reduce the adaptation delay.

II. ADAPTATION DELAY

ADAPTIVE FILTR OVER COLMS ADAPTIVE FILTER

Fig.1 shows the block diagram

adaptive filter, shows the adaptat

cycles amounts to the delay int

whole of adaptive filter structur

finite impulse response (FIR) fi

weight-update process. The adap

conventional LMS can be decom

parts: first part is the delay int

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st widely used

e conventional

ehaviour, it is

the pipelined

mentation of a

a-delay power,

pelining across

esign with less

xisting systolic

mption can be

lgorithms, area

f word length,

f computation.

tations in the

ber of pipeline

ing period, and

design is found

he power-delay

elay product

ctures proposed

IN DLMS

VENTIONAL

of the DLMS

ion delay of m

oduced by the

e consisting of

tering and the

tation delay of

posed into two

oduced by the


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pipeline stages in FIR filtering, and the

due to the delay involved in pipelinin

update process. Based on such a deco

delay, the DLMS adaptive filt

implemented by a structure shown i

modified DLMS algorithm decouple

computation block and the weight-upd

allows performing optimal pipelini

forward cut-set retiming to minimize t

pipeline stages and adaptation delay

.

Fig.1 Structure of conventional LMS a

Fig.2 Structure of delayed LMS adapti

Because of its pipelined structure th

delay gets reduced in DLMS, but in

structure of DLMS, the systolic arch

used so that there exist a high adaptatio

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other part is

g the weight

position of

r can be

Fig.2. The

s the error-

te block and

g by feed

e number of

aptive filter

e filter

e adaptation

conventional

itectures are

n delay.

III. OPTIMIZATION IN

STRUCTURES

A. Error-computation blockThe proposed structure for error-c

of an N-tap DLMS adaptive filter

3. It consists of N number of 2-bi

generators (PPG), corresponding t

and L/2 binary adder trees, then

single shiftadd tree. Each sub bloc

detail

Fig.3 Structure of error-computatio

1)Structure of PPG: The struc

product generator (PPG) is sho

consists of L/2 number of 2-to-3

AND/OR cells (AOC). Each of the

takes a 2-bit digit (u1u0) as its inp

b0 = u0. u1, b1 = u0 u1, and b2

three outputs, such that b0 = 1 for

1 for (u1u0) = 2, and b2 = 1 for

decoder output b0, b1 and b2 alo

and 3w are given as input to an

2w, and 3w are in 2s compleme

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PIPELINED

omputation unit

s shown in Fig.

partial product

o N multipliers

followed by a

k is described in

block

ture of partial

wn in Fig.4.It

decoders and of

2-to-3 decoders

ut and produces

= u0 u1 these

u1u0) = 1, b1 =

u1u0) = 3. The

ng with w, 2w,

AOC, where w,

t representation


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and sign-extended to have (W +

Fig.4 structure of partial product gener

2) Structure of AOCs: three AND c

OR cells are present in an AOCs. Ea

takes an n-bit input and a single bit i

present an n number of AND gates. Ea

act as one of the input and it distribute

of D input.The remaining inputs of all

gates are fed with the single-bit input

of an AOC is w, 2w, and 3w correspo

decimal values 1, 2, and 3 of the 2-b i

The decoder performs 2-bit multiplicaparallel multiplications with a 2-bit dig

L/2 partial products of the product wor

an AOC block.

3) Structure of Adder Tree: The struc

tree is shown which performs shifts-a

on the partial products of each PP

product value and then add all the N pr

to compute the inner output of t

However, this shift-add operation

product value which increases the wor

also the adder size. To avoid the

increasing word size of the adders,add all the N partial products of the

value from all the N PPGs by a singl

Table I shows the pipeline latches for

lengths.

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) bits each

tor

lls and two

h AND cell

put b, there

h AND gate

all the n bit

the n AND

. The output

nding to the

nput (u1u0).

tion and L/2it to produce

d along with

ure of adder

dd operation

gives the

oduct values

he product.

obtains the

length, and

problem of

e going tosame place

e adder tree.

arious filter

B. weight-update block

The Fig. 5 shows the proposed stru

update block. It performs N mul

operations of the form ( e) xi

filter weights. The step size is tak

power of 2 to realize the mul

recently available error by the shift

MAC unit is used to performs the

the shifted value of error with th

samples xi followed by the ad

corresponding old weight values

perform all the MAC operation,an

by N shiftadd trees. Each of the

L/2 partial products corresponding

the recently shifted error value

number of 2-bit digits of the input

expression can be shared across all

This results to a gradual redu

complexity. The final outputs of M

to updated weights to be used as in

computation block and the weight-

the next iteration.

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cture of weight-

iply-accumulate

wi to update N

en as a negative

tiplication with

operation. Each

ultiplication of

e delayed input

itions with the

i. The N PPGs

then followed

PPGs generates

o the product of

e with the

ord xi. The sub

the multipliers.

tion in adder

C units is used

uts to the error-

pdate block for


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Fig.5 structure of weight-update block

C. Fixed-point considerations

The fixed-point implementation of t

DLMS adaptive filter shows the bit le

of the adder tree, to reduce th

complexity without the degradation o

MSE. For fixed-point implementatio

lengths and radix points for input samp

and internal signals are need to be deshows the fixed-point representation

number. Table II shows the fixed-repr

the desired signals; its quantization is

as an input. For this purpose,

scaling/sign extension and truncation/

are required. Since the LMS algorit

learning so that y has the same sign a

signal e can also be set to hav

representation as y without overflo

subtraction.

Fig.6 fixed-point representation of bina

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e proposed

vel cut back

e hardware

steady state

, the word

les, weights,

ided. Fig. 6of a binary

sentation of

sually given

he specific

ero padding

m performs

d, the error

the same

after the

ry number.

Table II. Fixed-point representati

signals.

IV. ADDER TREEThe adder tree and shift add tree

be cut back for further optimizatio

and power complexity.fig 7 shows t

order to reduce the complexity

some of the least bits are truncate

bits are used to reduce the truncat

occur in adaptive filter. since

hardware usage the truncated bits a

by the PPGs. This further redu

complexity

Fig.7 structure of adder tre

This can be done using carry save

nothing but a type of digital

computer micro architecture to co

three or more n-bit numbers in b

from other digital adders in thatnumbers of the same dimensions a

which is a sequence of partial sum

which is a sequence of carrybits.

carry save adder complexity of

reduced.

V. RESULT ANALYSISThe Simulation results are carrie

point LMS adaptive filter using car

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on then of the

omputation can

of area, delay

he adder tree .in

in computation

d and the guard

ion error which

to reduce the

re not generated

ces the PPGs

e

adder ,which is

dder, used in

pute the sum of

nary. It differs

it outputs two the inputs, one

bits and another

ith the help of

ddition can be

out for Fixed-

ry save adder to


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find out the low adaptation delay. Th

is carried out by the Xilinx 13.2 as a si

The performance of the delay block isgiving various inputs to the weight-

with various weight is given below. T

be estimated from the various iteratio

shown below. The Simulation M

waveform for delay with its weights

w4 is given below in fig 8.

Fig 8: simulation result of filter block

Fig 9: simulation result of weight-upda

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Simulation

ulator tool.

simulated bypdate block

he error can

s which are

odel & its

1, w2, w3,

e block

Fig 10: simulation result o

consumption

VI. CONCLUSIONThis paper is based on efficient i

adaptive filter to achive faster p

reduction in the critical path su

input-sampling rates .The adap

reduced by using fixed point imDLMS adaptive filter by using a

implementation of general mul

inner-product computation by carr

From this, proposed strategy an opt

pipelining across the time-consum

reduce the adaptation delay

consumption. The proposed struct

reduces adaptation delay and pro

saving of ADP and EDP compare

structures.

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Fixed Point Implememnation of Adaptive Filter

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