Final Project Report (1)

Peripheral Interfacing in APC

CHAPTER 1

INTRODUCTION

Advancements in technology have increased the efficiency and security. There is a drastic

reduction in the cost of the product, because of the usage of well fabricated memory

chips, interface and microprocessors.

With the use of volatile memory (RAM), the important information contained will

be lost whenever the system failure has occurred. Nonvolatile memory was designed to

overcome such problems. Nonvolatile memory protects the data being corrupted or lost in

many ways. Whenever the event of a power failure occurs in the data acquisition system,

the collected data or program remains uncorrupted. Nonvolatile memory increases the

memory capacity virtually and eliminates the purged data in order to make memory

available for other useful measurements.

Atom Palm Computer (APC) is a portable computer that has features of a hand

held computer like laptops. It has sense of touch. One of the features that make APC so

successful is that it can be used in remote areas for the purpose of communication. Many

peripherals can be interfaced to the APC such as keypad, Liquid Crystal Display (LCD)

etc….

1.1 Problem Statement

In remote areas there is a need for communication required for tracing the geographical

locations. In earlier technologies, mobile phones were used to obtain information about

location. But, this lead to the tracing of information by hackers, as mobile phones emits

radiations. So this was not secured. There was a problem in network accessibility in

remote areas, in turn this technology could not be efficiently used.

To overcome the above said problem, a new technology based on atom processor

used in this proposed project is x86 based. With this module, communication is possible

even in the remote areas. This is designed to emit no radiations of frequencies above the

specified threshold. In situations like failure of network accessibility, the Global

Positioning System (GPS) which uses satellite services can be used.

Dept. of TE, GSSSIETW, Mysore.


1.2 Scope of the project

The main objective of the proposed project is to develop a palm computer which

consumes less power and does not emit any radiations above the specified threshold. In

early days, cell phones used to emit some form of radiations which were used by the

hackers to locate the exact location in remote areas. Additional features such as Bluetooth

and wireless fidelity (Wi-Fi) are provided in order to enhance the communication.

1.3 Organization of the report

This report presents the detailed approach of peripheral interfacing in APC

Chapter 1 consists of a brief introduction about the project. It also defines the problems

faced in today’s world and how the current project was used to overcome them.

Chapter 2 describes the previously available technologies which could have been used to

implement the present project.

Chapter 3 explains the working and the designing of the project with the help of block

diagram. The circuit connections of the various modules has been depicted and explained.

The flowchart for working of the project is explained.

Chapter 4 consists of the results of the project.

Chapter 5 gives the various advantages, disadvantages and the applications of the project.

Chapter 6 gives the conclusion of the project and also suggests the possible enhancements

in future.



CHAPTER 2

LITERATURE SURVEY

Scope

Literature survey is the first face of the project work where importance is given for

understanding the present trends in the industry related to the task.

This project deals with interfacing peripherals in the device Atom Palm Computer. Atom

Palm Computer (APC) has replaced the device PxA Palm Computer (PPC). The features

of PxA Palm Computer are as listed below

1. PPC uses PxA based processor.

2. Memory implementation in PPC uses DDR technology.

3. PPC uses the Windows CE Operating system.

4. PPC does not support Ethernet.

2.1 PxA based Processor

PPC is implemented on PxA based processor. The PxA family of application processors

is designed to maintain customers return on their development investment through

architectural compatibility that enables software reuse across the entire product family.

The x-scale microprocessor core is Intel’s and Marvell’s implementation of the

ARMv5 architecture. The PxA family comprises of many processors with slight

variations in clock speed.

There was a time around the year 2000 when Microsoft essentially decreed that

pocket PC’s were to run Intel x-scale processors. That was a big change and a rude

awakening for some of the windows CE hardware vendors who had been promised that

windows CE was going to be a multiprocessor architecture platform, but Intel PxA

became the de-facto standard processor for virtually all vertical market handhelds for a

decade.



2.1.1 Comparison between PxA processor and Atom processor

1. PxA processor is based on ARMv5TE architecture whereas Atom processor is based on

Bonnell microarchitecture.

2. PxA processor is 32 bit processor in turn Atom processor is 64 bit processor.

3. Operating frequencies of PxA processor are 200MHz, 300MHz and 400MHz but,

Atom operates in the clock range of 600MHz to 2.13GHz.

2.2 DDR technology

PPC is based on DDR technology and APC is based on DDR2 technology.

DDR SDRAM is abbreviated as Double Data Rate Synchronous Dynamic

Random Access Memory, which is a class of memory Integrated Circuits used in

computers (sometimes referred to as DDR1 SDRAM).

With data being transferred 64-bits at a time DDR SDRAM gives a transfer rate of

(memory and bus clock rate)*2(for dual rate)*64(number of bits transferred)/8(no of

bits/byte). Thus, with a bus frequency of 100MHz, DDR SDRAM gives a maximum

transfer rate of 1600MbPS.

2.2.1 Comparison between DDR and DDR2

DDR2 is the next generation of DDR. Both are the types of SDRAM only, but the

difference is that in DDR2 the bus is clocked at twice the speed of the memory cells

through which four words of data can be transferred per memory cell cycle. Thus, without

speeding up the memory cells, DDR2 can effectively operate at twice the bus speed of

DDR.

Features DDR DDR2

Speed 200MHz,333MHz,400MHz 400MHz,533MHz,800MHz

Voltage 2.5V 1.8V

Prefetch buffer 2 bits 4 bits

Data strobes Single ended Differential ended



2.3 Operating System

Windows CE is used in PPC and Windows7 is used in APC.

Microsoft Windows Embedded Compact was previously known as Windows

Embedded CE. This is also called as WinCE. It is an Operating System (OS) developed

by Microsoft for embedded systems, which is a distinct OS and kernel, rather than

trimmed-down version of desktop windows.

The features of WinCE are

1. It is optimized for devices that have minimal storage.

2. Its kernel may run in under a mega byte of memory .

3. Devices are often configured without disk storage.

2.4 Other peripherals

PPC does not support Ethernet but APC is implemented to support Ethernet.Ethernet is a

family of computer networking technologies for Local Area Networks (LAN). It has been

standardized as IEEE 802.3.

Ethernet has largely replaced competing wired LAN technologies. Systems

communicating over Ethernet divide a stream of data into shorter pieces called frames,

each frame contains source and destination addresses and error checking data so that

damaged data can be detected and re-transmitted.

Figure 2.1 Overview of Ethernet



CHAPTER 3

DESIGN METHODOLOGY

Scope

This chapter includes the Block diagram, circuit diagram, design specifications of

the project and the components used.

3.1 Block diagram

This block diagram mainly consists of an atom processor, system controller hub,

embedded controller, LCD for display, BIOS, SODIMM module, SODIMM connector,

brightness controller, keypad, battery charger, battery monitor and the interfaces used are

Front Side Bus (FSB), Memory Controller Interface (MCI), Universal Serial Bus (USB),

Low Voltage Differential Signalling (LVDS), Parallel ATA (PATA), Serial Digital Input

Output (SDIO), Low Pin Count (LPC), General Purpose Input Output (GPIO), Serial

Peripheral Interface (SPI) and Inter- Integrated Circuit (I2 C).



BLOCK DIAGRAM:

Figure 3.1 Block diagram of peripheral interfacing in APC.



The interfaces mentioned in the above Block Diagram are listed below

1. Front Side Bus (FSB).

2. Memory Controller Interface (MCI).

3. Universal Serial Bus (USB).

4. Low Voltage Differential Signalling (LVDS).

5. Parallel ATA (PATA).

6. Serial Digital Input Output (SDIO).


8. Low Pin Count (LPC).


10. General Purpose Input Output (GPIO).

11. Serial Peripheral Interface (SPI).

12. General Purpose Input Output (GPIO).

13. Inter- Integrated Circuit (I2 C).

Working

The device is provided with a power supply voltage of 9V and 3A current, which in turn

charges the two batteries. One is internal and the other is external. External battery is used

during the operation of the device. Switching to the internal battery from external is done

when external battery is discharged completely. The status of charging and discharging is

indicated by the battery monitors. The source code for the device initialization will be

stored in BIOS memory. Execution of the instruction code is done by Atom processor

with the rate of two instructions per execution cycle, thus translating CISC to RISC

instruction. SCH (System Controller Hub) accounts for the interfacing of various modules

required for operation and is achieved via the corresponding bus interfaces.

Memory requirements are fulfilled with the help of SODIMM (Small Outline

Dual Inline Memory Module), which is connected to the SCH through SODIMM

connector. The screen necessary to provide user interface is met by interfacing LCD

(Liquid Crystal Display) to SC

H via LVDS (Low Voltage Differential Signaling) interface.



The technique necessary to control the peripherals such as keypad, battery

charger, battery monitor and BIOS is done with the help of embedded controller. The

keypad is used here to provide user friendly environment.

3.1.1 Atom processors

The Intel Atom processor is built on a new 45-nanometer Hi-k low power micro

architecture and 45 nm process technology. This supports System Controller Hub, a

single chip component designed for low power operation.

Major features of Atom processors

1. New single core memory for mobile devices offering enhanced performance.

2. 133MHz Source synchronous Front Side Bus (FSB).

3. Supports 32-bit architecture.

4. Advanced power management features including Enhanced Intel Speed Step

Technology.

5. Supports new Complementary Metal-Oxide Semiconductor (CMOS) FSB signaling

for reduced power.

Figure 3.2 INTEL Atom Processor z520



3.1.2 System Controller Hub (SCH)

The Intel System Controller Hub is a component of Intel atom processor technology. This

combines the functionality normally found in separate GMCH and SCH components in to

a single component consuming less than 2.3W of thermal design power. The features of

this, provide functionality necessary for traditional operating systems (such as windows

vista and Linux) as well as functionality normally associated with handheld devices (such

as SDIO/MMC and USB host). This was designed to be used with the Intel atom

processor Z520 processor.

Major features of System Controller Hub

1. CMOS front end bus signaling for reduced power.

2. 64-byte cache line size.

3. 64-bit data bus.

4. 32-bit address bus.

5. Power saving sideband control for enabling/disabling processor data input sense

amplifier.

6. 1.05v operation.

Figure 3.3 System Controller Hub

3.1.3 SODIMM

It is abbreviated as Small Outline Dual In-Line Memory Module. It is a type of computer

memory built using Integrated Circuits. SODIMMs have 72, 100, 144, or 200 pins. The

module used here has 144 pins. SODIMMS are often used in systems which have space



restrictions such as notebooks, small footprint PCs, high-end upgradable office printers,

and networking hardware like routers. The 100 pin package supports 32-bit data transfer,

while the 144 and 200 packages support 64-bit data transfer. SODIMMs are more or less

equal in power and voltage rating to Dual In-Line Memory Module (DIMM), and as

memory technology moves forward, both SO-DIMMs and DIMMs become available in

equal speed (clock speeds such as 400Mhz PC-3200, for example, and CAS latency such

as 2.0, 2.5, and 3.0) and capacity (512MB, 1GB, etc).

Figure 3.4 SODIMM module with 144 pins

3.1.4 SODIMM Connector

APC uses SODIMM connector suitable for DDR2 SODIMM cards, A memory card board is

securely fixed in the connector and incomplete insertion is prevented with arms on both ends set

by the lever moved up when the memory card board is depressed completely. It serves the uses

of various applications such as multifunction peripheral, printers, scanners and POS system

terminals.



Figure 3.5 SODIMM connector

3.1.5 Liquid Crystal Display (LCD)

This is a flat panel display or electronic visual display or video display that uses the light

modulating properties of liquid crystals. Liquid crystals do not emit light directly. LCDs

are available to display arbitrary images (as in a general-purpose computer display) or

fixed images which can be displayed or hidden, such as preset words, digits, and 7-

segment displays as in a digital clock.

Figure 3.6 Liquid Crystal Display

3.1.6 Keypad

Keypads are found on many alphanumeric keypads and on other devices such as

calculators, push-button telephone, combination locks, and digital door locks, which

require mainly numeric input. The keypad used here has 5 custom assigned keys. Each

key is implemented with 5 GPIOs.

3.1.7 Battery Charger



It is a device used to energize a secondary cell or rechargeable battery by forcing an

electric current through it. The battery used here is a Lithium-Ion battery. APC has 2

chargers namely internal and external charger, which performs charging and discharging

respectively.

Figure 3.7 Lithium Ion Battery Charger

3.1.8 Basic Input/output System (BIOS)

This is also known as the system BIOS or ROM BIOS. It is a de facto standard defining a

firmware interface. The BIOS software is built into the PC, and is the first software run

by a PC when powered on. The fundamental purposes of the BIOS are to initialize and

test the system hardware components and to load an operating system or other program

from a mass memory device. The BIOS provides a consistent way for application

programs and operating systems to interact with the keyboard, display, and other

input/output devices. Variations in the system hardware are hidden by the BIOS from

programs that use BIOS services instead of directly accessing the hardware.



Figure 3.8 BIOS chip

3.1.9 Wireless Fidelity (Wi-Fi)

Wi-Fi is a popular technology that allows an electronic device to exchange

data wirelessly (using radio waves) over a computer network, including high-speed

Internet connections. The Wi-Fi Alliance defines Wi-Fi as any "wireless local area

network (WLAN) products that are based on the Institute of Electrical and Electronics

Engineers (IEEE) 802.11 standards. However, since most modern WLANs are based on

these standards, the term "Wi-Fi" is used in general English as a synonym for "WLAN".

Only Wi-Fi products that complete Wi-Fi Alliance interoperability certification testing

successfully may use the "Wi-Fi CERTIFIED" trademark.

A device that can use Wi-Fi (such as a personal computer, video-game

console, smartphone, tablet, or digital audio player) can connect to a network resource

such as the Internet via a wireless network access point. Such an access point (or hotspot)

has a range of about 20 meters (65 feet) indoors and a greater range outdoors. Hotspot

coverage can comprise an area as small as a single room with walls that block radio

waves or as large as many square miles. This is achieved by using multiple overlapping

access points.

3.1.10 Bluetooth

Bluetooth is a wireless technology standard for exchanging data over short distances

(using short-wavelength radio transmissions in the ISM band from 2400–2480 MHz)



from fixed and mobile devices, creating personal area networks (PANs) with high levels

of security. Created by telecom vendor Ericsson in 1994, it was originally conceived as a

wireless alternative to RS-232 data cables. It can connect several devices, overcoming

problems of synchronization.

3.1.11 Global Positioning System (GPS)

The Global Positioning System (GPS) is a space-based satellite navigation system that

provides location and time information in all weather conditions, anywhere on or near the

Earth where there is an unobstructed line of sight to four or more GPS satellites. The

system provides critical capabilities to military, civil and commercial users around the

world. It is maintained by the United States government and is freely accessible to anyone

with a GPS receiver.

3.1.12 Interfaces

Front Side Bus (FSB)

A front-side bus (FSB) is a computer communication interface (bus) often used in Intel-

chip-based computers. The competing, and more general purpose, Hyper Transport bus

serves the same function for AMD CPUs. Both typically carry data between the central

processing unit (CPU) and a memory controller hub, known as the north bridge. "Front

side" refers to the external interface from the processor to the rest of the computer system,

as opposed to the back side, where the back-side bus connects the cache (and potentially

other CPUs).

A FSB is mostly used on PC-related motherboards ,seldom with the data and

address buses used in embedded systems and similar small computers. This design

represented a performance improvement over the single system bus designs of the

previous decades, but sometimes is still called the "system bus".

Front-side buses usually connect the CPU and the rest of the hardware via a

chipset, which Intel implemented as a north bridge and a south bridge. Other buses like

the Peripheral Component Interconnect (PCI), Accelerated Graphics Port (AGP), and

memory buses all connect to the chipset in order for data to flow between the connected

devices. These secondary system buses usually run at speeds derived from the front-side

bus clock, but are not necessarily synchronized to it. The FSB terminology used in this



document refers to a hybrid signaling mode. Where data and address busses run in CMOS

mode and strobe signals operate in GTL mode. The reason to use GTL on strobe signals

is to improve signal integrity.

Universal Serial Bus (USB)

USB is an industry standard developed in the mid-1990s that defines the cables,

connectors and communications protocols used in a bus for connection, communication

and power supply between computers and electronic devices.USB was designed to

standardize the connection of computer peripherals (including keyboards, pointing

devices, digital cameras, printers, portable media players, disk drives and network

adapters) to personal computers, both to communicate and to supply electric power.

Parallel ATA (PATA)

PATA is Parallel Advanced Technology Attachment. This is an interface standard for the

connection of storage devices such as hard disks, floppy drives, and optical disc drives in

computers. Parallel ATA cables have a maximum allowable length of only 18 in

(457 mm). Because of this limit, the technology normally appears as an internal computer

storage interface. For many years, ATA provided the most common and the least

expensive interface for this application.

Memory Controller Interface (MCI)

The memory controller is a digital circuit which manages the flow of data going to and

from the main memory. It can be a separate chip or integrated into another chip, such as

on the die of a microprocessor. This is also called a Memory Chip Controller (MCC).

Memory controllers contain the logic necessary to read and write to DRAM, and

to "refresh" the DRAM by sending current through the entire device. Without constant

refreshes, DRAM will lose the data written to it as the capacitors leak their charge within

a fraction of a second (not less than 64 milliseconds according to JEDEC standards).

Low Voltage Differential Signalling

LVDS or low voltage differential signalling is very popular in computers, where it forms

part of very high-speed networks and computer buses. It is a high-speed digital interface



that is used for several applications that require high noise immunity and low power

consumption for high data rates. LVDS is used in several applications and industries,

including commercial and military applications.

Low Pin Count (LPC)

The Low Pin Count bus, or LPC bus, is used on IBM-compatible personal computers to

connect low-bandwidth devices to the CPU, such as the boot ROM and the "legacy" I/O

devices. The "legacy" I/O devices usually include serial and parallel ports, PS/2keyboard,

PS/2 mouse, floppy disk controller and more recently the Trusted Platform Module

(TPM). The physical wires of the LPC bus usually connect to the south bridge chip on a

PC motherboard, which contains the circuit equivalents of the "legacy" onboard

peripherals of the IBM PC/AT architecture, such as the two programmable interrupt

controllers, the programmable interval timer, and the two ISA DMA controllers.

The LPC bus was introduced by Intel in 1998 as a substitute for the Industry

Standard Architecture (ISA) bus. It resembles ISA to software, although physically it is

quite different, replacing the 16-bit-wide, 8.33 MHz ISA bus with a 4-bit-wide bus

operating at 4 times the clock speed (33.3 MHz).

LPC's main advantage is that it requires only seven signals, and is therefore easy

to route on modern motherboards, which are often quite crowded. An integrated circuit

using LPC will need 30 to 72 fewer pins than its ISA equivalent.

The LPC controller implements a low pin count interface. The LPC controller

does not implement DMA or bus mastering cycles. This function contains many other

functional units, such as Interrupt controllers, Timers, Power Management, System

Management.

General Purpose Input/Output (GPIO)

General Purpose Input/Output (GPIO) is a generic pin on a chip whose behavior

(including whether it is an input or output pin) can be controlled (programmed) by the

user at run time. A GPIO is a flexible software-controlled digital signal. Each GPIO

represents a bit connected to a particular pin.

Serial Peripheral Interface (SPI)

The Serial Peripheral Interface Bus or SPI (pronounced as either ess-pee-eye or spy) bus

is a synchronous serial data link standard, named by Motorola, that operates in full



duplex mode. Devices communicate in master/slave mode where the master device

initiates the data frame. Multiple slave devices are allowed with individual slave

select (chip select) lines. Sometimes SPI is called a four-wire serial bus, contrasting

with three, two, and one-wire serial buses. SPI is often referred to as SSI (Synchronous

Serial Interface).

Secure Digital Input Output (SDIO)

SDIO card is an extension of the SD specification to cover I/O functions. Host devices

that support SDIO (typically PDAs like the Palm Treo, but occasionally laptops or mobile

phones) can use the SD slot to support GPS receivers, modems, barcode readers, FM

radio tuners, TV tuners, RFID readers, digital cameras, and interfaces to Wi-

Fi, Bluetooth, Ethernet, and IrDA. Many other SDIO devices have been proposed, but it

is now more common for I/O devices to connect using the USB interface.

SDIO cards support most of the memory commands of SD cards. SDIO cards can

be structured as 8 logical cards, although currently, the typical way that an SDIO card

uses this capability is to structure itself as one I/O card and one memory card.

Inter-Integrated Circuit (I2C)

I²C ("eye-squared cee" or "eye-two-cee" Inter-Integrated Circuit, generically referred to

as "two-wire interface") is a multi-master serial single-ended computer bus invented by

Philips that is used to attach low-speed peripherals to a motherboard, embedded

system, cell phone, or other electronic device.

3.3 Software and Hardware details

Software used

1. Windows XP or above for host computer

2. Windows 7 for APC

3. Visual studio 2010

Hardware used

1. ATOM Processor

2. System Controller Hub



3. Embedded Controller

4. SODIMM Module

5. SODIMM Connector

6. LCD Vertex 3.5", screen size 7.2x5.2cm(2.83"x2.04") with resolution of 640x480

7. BIOS

8. Keypad with 5 custom assigned keys

9. Battery charger

10. Battery monitor

11. Source power supply of 9v, 3A rating

3.4 Algorithm

Read Algorithm

1. Address = [EC-SC]

2. Wait EC free

3. Write 0x80 to [EC-SC]

4. Wait IBF free

5. Write address to [EC-SC]

6. Wait IBF free

7. Wait OBF full

8. Read data from [EC-DATA]

Write Algorithm

1. Address = [EC-SC]

2. Wait EC free

3. Write 0x81 to [EC-SC]

4. Wait IBF free

5. Write address to [EC-DATA]

6. Wait IBF free

7. Write DATA to [EC-DATA]

8. Wait IBF free



FLOWCHART

Reading The Data



Writing The Data



CHAPTER 4

RESULTS

Scope

This chapter discusses about the result of the project. It consists of results and

necessary outcomes of the project implementation.

4.1 Experimental observations

Figure 4.1 Checking the presence of embedded controller using RW utility software



Figure 4.2 Application window of peripheral controlling

Figure 4.3 Enabling of Bluetooth



Figure 4.4 Disabling of Bluetooth

Figure 4.5 Enabling of GPS



Figure 4.6 Disabling of GPS

Figure 4.7 Enabling of Wi-Fi



CHAPTER 5

ADVANTAGES, DISADVANTAGES AND

APPLICATIONS

Scope

This chapter includes merits, demerits and applications of the project. It also contains

information about where it is applied in various fields.

4.1 Advantages

1. Enhanced computing speed.

2. Supports all windows based applications.

3. Operates well in high altitude and damp heat(+50°C) conditions.

4. It has successfully undergone EMI and EMC tests, in order to meet the specifications

of radiation emission.

5. Possesses good susceptibility.

6. This can be stored at temperatures.

4.2 Disadvantages

1. It is bulky to handle.

2. Small screen size.

3. Small resolution of 640x480.

4.3 Applications

1. Sensor integration.

2. Sending of reports for data to communication centres.



CHAPTER 6

CONCLUSION AND FUTURE

ENHANCEMENT

Scope

The following section explains the conclusion drawn from the project work and the future

enhancements.

5.1 Conclusion

Atom Palm Computer (APC) is becoming a standard in military applications. In this

project, GUI for peripheral control on x86 architecture has been developed. This project

has used Atom processor with System controller hub and embedded controller on VC++

platform for LCD brightness control, enabling/disabling of peripherals (Bluetooth, GPS

and keypad) and battery monitoring. Hence this project is useful in defence for the

geographical location identification using Atom Palm Computer.

5.2 Future Enhancement

This project deals with interfacing peripherals in APC, which is implemented using

Atom Processor Z520, DDR2 technology. To provide more advantageous features, the

Atom Processor Z520 can be replaced by Z530 and DDR3 technology can replace DDR2

technology.

Memory implementation can be done with DDR3 (replacing DDR2) to provide more

beneficial features.

DDR3 SDRAM stands for Double Data Rate type 3 Synchronous Dynamic Random

Access Memory. It is a modern kind of DRAM with high band width interface. DDR3 is

neither forward nor backward compatible with any earlier type of RAM due to different

signaling voltages, timings and other factors.

The primary benefit of DDR3 over its immediate predecessor, DDR2 SDRAM is its

ability to transfer data at twice the rate (8 times the speed of its internal memory arrays),

enabling higher bandwidth or peak data rates.



5.2.1.1 Comparison between DDR2 and DDR3

1. DDR3 memory uses 30% less power, this reduction comes from the difference in

supply voltages -1.8V or 2.5V for DDR2, 1.5V for DDR3.

2. DDR3 has the benefit of prefetch buffer, which is 8-burst deep in contrast DDR2 has

4-burst deep. This is advantageous for higher transfer rate in DDR3. DDR3.

5.2.1.2 Advantages of DDR3 over DDR2

1. Higher bandwidth performance of up to 2133MT/S standardized.

2. Slightly improved latencies, as measured in nano seconds.

3. Higher performance at low power (longer battery life in laptops).

4. Enhanced low power features.

5. Thermal Dissipation Power (TDP) of less than 5W is achievable.

5.2.2 Atom processor Z530

Z520 Atom processor is succeeded by Z530 Atom processor. Z530 shows more useful

properties when compared to Z520. They both share the common features such as voltage

range (0.75V to 1.1V), maximum TDP (2W), possess no FSB (Front Side Bus) parity and

processing die size (26 square millimeter).

5.2.2.1 Comparison between Z520 and Z530

1. Clock speed of 1.33GHz can be achieved with Z520 whereas 1.6GHz clock speed can

be achieved with Z530 processor.

2. Z520 supports no embedded options in turn Z530 supports the embedded options.

3. Z530 is costlier than Z520 processor.



REFERENCES

Text books

[1] Barry B Brey, “The Intel Microprocessors”, Pearson Education, 2009.

Websites

[2] “Atom processor Z5XX series”

http://www.intel.com/design/chipsets/embedded/SCHUS15W/techdocs.htm

[3] “System Controller hub”

http://www.intel.com/design/chipset/embedded/SCHUS15W/techdocs.htm

[4] “Renasas Embedded Controller ” ww w .renasas.com

[5] “SODIMM module” www.sw i ssbit.com

[6] “Atmel BIOS” www.atmel.com/d e v i ces/at25df081a.aspx

[7] “Touch controller” w w w.ti.com/lit/ds/sbas162g/sbas162g.pdf

[8] “Battery Charger” www.ic-on-line.cn/search.ph p ?part=bq2147 & stype=part

APPENDIX A


http://www.ic-on-line.cn/search.php?part=bq2147&stype=part

http://www.ti.com/lit/ds/sbas162g/sbas162g.pdf

http://www.atmel.com/devices/at25df081a.aspx

http://www.swissbit.com/

http://www.renasas.com/

http://www.intel.com/design/chipset/embedded/SCHUS15W/techdocs.htm


Hardware

A.1 Atom Processor

Major Feature of Atom Processor

1. Supports for IA 32-bit architecture.

2. 133-MHz source-synchronous front side bus(FSB).

3. Supports new CMOS FSB signalling for reduced power.

4. Thermal management support and advanced power management features

including enhanced INTEL speed technology.

A 1.1 Enhanced Intel speed technology

The processor features Intel speed technology. The following are the key features

of enhanced Intel speed technology.

1. Multiple voltage and frequency operating points providing optimal performance at

the lowest power.

2. The processor controls voltage ramp rates internally to ensure glitch free

transitions.

3. Low transition latency and large number of transitions are possible per second.

4. Improved Intel thermal monitor mode.

A 1.2 Enhanced Low Power States

Enhanced low power states optimize for power by forcibly reducing the

performance state of the processor when it enters a package low-power state. Instead of

directly transitioning into the package low-power state, the enhanced low power state first

reduces the performance state of the process by performing an enhanced Intel speed

technology. The advantage of this feature is that it significantly reduces leakage while in

the deeper sleep states.

A 1.3 FSB Low Power Enhancements

The processor incorporates FSB Low Power Enhancements:

1. Control input buffers.

2. Dynamic bus parking.

3. Dynamic on die termination disabling.

4. Low I/O termination voltage.



5. CMOS front side bus.

A 1.4 CMOS front side bus

The processor has a hybrid signalling mode, where data and address bus run in

CMOS mode and strobe signals operate in GTL mode. The reason to use GTL on strobe

signal is to improve signal integrity.



APPENDIX B

SOFTWARE

B.1 RW Utility software v1.5.3.7

Steps to check the presence of embedded controller in the system

1. Start the RW Utility software

2. The RW Utility GUI will appear. Here we can check the presence of embedded

controller memory space.

3. The IO space base address is given as 00h. The ports used here are 62 and 66.The

corresponding values of these ports are read as shown above.

4. If the values read are other than FFh, then the presence of embedded controller is

confirmed else embedded controller is absent.



B.2 Microsoft Visual Studio 2010

Steps to upload the program

1. Start the tool chain by selecting visual studio 2010 from within the programs

group Start\Programs\ visual studio 2010 or by double-clicking on the visual

studio 2010 icon on your desktop.

2. Create a new project, and select MFC application and the project is named.



3. In the application type, select the options ‘Dialog based’ and ‘use MFC in a static

library’ and click the ‘Finish’ option.



4. Create the button using the corresponding option provided in the toolbox.



5. The button is named and the corresponding code is written by double clicking on

the button. This code performs the required actions.

6. Create checkbox by selecting corresponding option from the toolbox. The

respective code is written to perform mode inversion.



7. Create the horizontal scroll bar from the option provided in the tool box. This is

used for brightness monitoring.

8. After the creation and coding of 9 buttons, 1 checkbox and 1 horizontal scroll bar,

the code is debugged. If no errors, the solution is built using the options provided.

9. The above window appears after successfully running the code. The buttons in

this window are used to control the peripherals i.e, enabling, disabling, brightness



control and mode inversion is done. Enabling and disabling of GPS is shown

below.


Final Project Report (1)

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