RECONFIGURABLE CCSDS DECODER IN TELECOMMAND SYSTEM

Presented by

Navakanth Bydeti

(09HQ006)

II M.Tech -VLSI Design

UNDER THE GUIDANCE OF

Mr.G.MANOJ (PhD.),

Assistant Professor

KARUNYA UNIVERSITY

CONTENTS

OBJECTIVE

LITERATURE SURVEY

METHODOLOGY

INTRODUCTION

CONCLUSION

OBJECTIVE

• To develop a CCSDS(Consultative Committee for Space Data Systems) Telecommand system with Error Detection And Correction (EDAC) system and an Partially reconfigurable Authentication scheme.

• EDAC uses BCH( Bose–Chaudhuri–Hocquenghem) code to correct multiple random bit errors

• Reconfiguring CCSDS Telecommand Authentication scheme by using self partial dynamic reconfiguration.

LITERATURE SURVEY

[1] CCSDS Command Decoder with BCH EDAC and Level-0 Command Execution

Command decoding module and BCH error detection and correction.

The module must also serve as a level-0 mode. Used to speed up system throughput by off loading the command

process from the main computer’s tasks.

[2] Wireless Telecommand and Telemetry System for Satellite

The paper presents the architecture of Wireless Telecommand and Telemetry system.

The advantage and difficulties in implementing a wireless system in spacecraft is mentioned.

Replacement of the existing wired Telecommand & Telemetry systems with a wireless system is explained.

[3] Parallel Algebraic Approach of BCH coding in VHDL An algebraic approach, for Error Correction Code (ECC)

BCH code. A BCH (63,57) is used which is an usual configuration in

CCSDS Telecommand systems was considered.

[4]Consultative Committee for Space Data Systems The systems architecture of a spacecraft Telecommand system

is defined. The convention used by all the space agencies around the

world. This committee defines the Telecommand layers and the

transmission units to be encoded and the filling bits for the authentication of the data

[5] Optimized design for high speed parallel BCH encoder A new design method for parallel BCH encoder is presented,

which can eliminate the bottleneck in long BCH encoders. The bottleneck eliminated by the help of sub expression

elimination.

[6]Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

This paper presents efficient hardware/software implementation approaches for the AES algorithm.

AES coprocessor implementation using the self partial dynamically reconfiguration of FPGA is presented.

[7] Design Of A Reconfigurable AES Encryption/Decryption Engine For Mobile Terminals

This paper presents the hardware design of a reconfigurable encryption/decryption engine for the Advanced Encryption Standard (AES) supporting all key lengths.

[8] PlanAhead Software Tutorial Overview of the Partial Reconfiguration Flow

This reference illustrates how to create a Partial Reconfiguration (PR) design from HDL synthesis through bit file generation and download to the FPGA.

METHODOLOGY Designing of CCSDS Telecommand system in two

phases FPGA1 and FPGA2. Designing the EDAC system in the design. Designing the authentication scheme in the design. Reconfiguring the authentication scheme in the

design.

INTRODUCTIONTelecommand (TC) system:

The system that provides uplink for the spacecraft by decoding the up-linked command and gives out command information and data in binary form for operation of various subsystems.

CONVENTIONAL TELECOMMAND SYSTEM:

Low-level data commanding system having a fixed length commanding.

The input to the TC encoder is a stream of 32 bits representing a single command.

Conventional Telecommand system

CCSDS TELECOMMAND SYSTEM

CCSDS Telecommand System is a set of layered, Standardized command services that are applicable to a very wide range of mission needs.Advantages of CCSDS TC System are:

• Variable Length Commanding• Guarantees the command sequence with no omission or

duplication• Standardized format cross support is possible from ground

stations having CCSDS encoders and decoders.

CCSDS Telecommand system

CCSDS TELECOMMAND ARCHITECTURE

CCSDS Telecommand Standards only defines the Data Link Layer. Data Link Layer has two sub layers

• Data Link Protocol Sub-layer • Synchronization and Channel Coding Sub-layer

The Data Link Protocol Sub layer provides • Segmenting and Blocking of data units• Transmission Control of data units.

The Synchronization and Channel Coding Sub layer provides • Error-control coding• Synchronization

CCSDS Telecommand architecture

TELECOMMAND SYSTEM

Transponder (digital data)

CCSDS DECODER

Level-0/Normal Command execution

Authentication

Distribution Logic

Micro- Controller

8051

PROM/RAM

EDAC

Standard Interface

External MemoryInterface

Telecommand system components

DESIGN OF CCSDS TELECOMMAND DECODER: FPGA 1

It implements coding and synchronization sublayer and all frames reception function.

The functions of coding and

sync sublayer are

• Tc data stream cross tapping

• Start sequence detection

• Derandomization

• BCH Decoding

Block diagram of FPGA1

Telecommand stream cross tapping logic

Functions

• Detection of Start Sequence in a CLTU.

• Implementation of CLTU reception logic.

• Process the data stream and delivers the valid frames to FPGA2

BCH decoder logic

BCH decoder logic contains the following sub modules.

• BCH decoder control logic

• Syndrome generation logic

• Error correction logic

All Frames Reception FunctionThe all frames reception function performs

• Frame delimiting and Fill removal

• CRC decoding

• Frame Validation Check

DESIGN OF CCSDS TELECOMMAND DECODER: FPGA 2 It receives data from FPGA 1. The FPGA memory interface logic accepts the parallel data and

stores in the memory. Frame header octets are processed by FARM (Frame Acceptance and Reporting Mechanism )logic. FARM generates the command ready signal.

It will generate CLCWs that are delivered to telemetry through the telemetry interface.

Functional Diagram of FPGA 2

8051 MICROCONTROLLER

SPECIFICATIONS OF 8051:• 8-bit CPU optimized for control applications• 128 bytes of on-chip Data RAM.

64K Program Memory address space.

64K Data Memory address space.• Up to 4K bytes of on-chip Program Memory (ROM).• 32 bi-directional and individually addressable I/O lines• Two 16-bit timer/counters

The 8051 timers have following functions• Keeping time and/or calculating the amount of time between events,• Counting the events themselves.

CRYPTOGRAPHY

Provides a method for securing and authenticating the transmission of information

Two types of cryptographic systems

Symmetric and Asymmetric.

Symmetric cryptosystems • Data Encryption Standard (DES)• 3 DES• Advanced Encryption Standard (AES) .

Asymmetric cryptosystems • Rivest-Shamir-Adleman (RSA) • Elliptic Curve Cryptosystem (ECC)

Why symmetric crypto system ?• encrypt large amount of data • high speed

RIJNDAEL ALGORITHM It is a block cipher algorithm that has been developed by Joan

Daemen and Vincent Rijmen.

The AES Cipher • Block length is limited to 128 bit• The key size can be independently specified to 128, 192 or

256 bits

Key size (words/bytes/bits) 4/16/128 6/24/192 8/32/256

Number of rounds 10 12 14

Expanded key size (words/byte) 44/176 52/208 60/240

Encryption And Decryption Flow

STEPS IN EACH ROUND

There a four basic stepsthat are used to form therounds:

(1) The Sub Byte

(2) The Shift Row (3) The Mix Column (4) AddRoundKey

Step 1

Step 2

Step 3

Step 4

RECONFIGURTION

It allows specific regions of the FPGA to be reprogrammed with new functionality.

Types of reconfiguration

•Device is not active in Static reconfiguration.

•Dynamic type of reconfiguration permits to perform reconfiguration during run time.

Reconfiguration

Static Dynamic Self reconfigu

rable dynamic

logic

PARTIAL RECONFIGURATION

Allows the device to be partially reconfigured while the rest of the device continues its normal operation .

Partial reconfiguration addresses three fundamental uses that enables the designer to:

• Reduce cost and board space• optimized use of resources• Reduce power consumption

TYPES IN PARTIAL RECONFIGURATION

Two types of partial reconfiguration• Module-Based Partial Reconfiguration• Reconfiguration based on Bus Macro Communication

Module-Based Partial Reconfiguration•Partially reconfiguring a large portion of the design•It allows large designs to be partitioned into self-contained modules

Top-level design and modules are created using an HDL (Verilog or VHDL)

To synthesize Xilinx synthesis tool, Xilinx Synthesis Technology (XST), can be used. This tool produces a netlist in NGC format.

BUS MACRO COMMUNICATION• Communication between the modules. • Signals connecting the reconfigurable modules with other

modules can be routed differently in design implementation. • Bus macros are currently implemented using 3-state buffers

(TBUFs) in CLB

Bus macro module

RESULTS

WAVE FORM FOR THE VERIFIED DESIGN

Verified waveform of design

OUTPUT WAVEFORM FOR THE TESTED MICROCONTROLLER

Waveform for tested instructions

Fig.8 Verification of EDAC

Fig.9 Verification of FPGA2

Waveform Of AES

Device utilization summary:---------------------------Selected Device : 4vlx25ff668-12   Number of Slices: 7768 out of 10752 72% Number of Slice Flip Flops: 1165 out of 21504 5% Number of 4 input LUTs: 15103 out of 21504 70% Number of IOs: 262 Number of bonded IOBs: 262 out of 448 58% Number of GCLKs: 1 out of 32 3%

Timing Summary:---------------Speed Grade: 12  Minimum period: 8.220ns (Maximum Frequency: 121.647MHz) Minimum input arrival time before clock: 8.787ns Maximum output required time after clock: 3.806ns

Total memory usage is 552816 kilobytes

RECONFIGURATION RESULTS USING PLAN AHEAD SOFTWARE

Verification of DRC

RTL OF THE AES MODULE

RESOURCE UTILIZATION

The design utilizes only 9% out of the total resources available

AREA AND THROUGHPUT COMPARISION

SOFTWARE USED FOR RECONFIGURATION

Xilinx ISE® 12 software for partial reconfiguration applications.

In the ISE 12 software, the PlanAhead™ design tools manage all the details of building such a reconfigurable design,

Floorplanning, constraint entry, and design rule checks (DRCs) are all accessed through the PlanAhead software

environment.

CONCLUSION

Design of the CCSDS Telecommand system is designed by using VHDL language and simulated using model sim.

EDAC which can detect and correct multiple errors is implemented by using BCH code.

Encryption system was designed by using Rijndael algorithm Reconfiguration of the Authentication(AES) scheme isdone using

self partial reconfiguration. Results from planahead software

THANK YOU