FE8113 ”High Speed Data Converters”. Course outline Focus on ADCs. Three main topics: 1:...
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Transcript of FE8113 ”High Speed Data Converters”. Course outline Focus on ADCs. Three main topics: 1:...
FE8113 ”High Speed Data Converters”
Course outline
Focus on ADCs. Three main topics:1: Architectures
”CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters,” 2nd ed., Rudy van de Plassche, Kluwer Academic Publishers, Ch. 1-3
2: Digital background calibration Selected papers
3: State-of-the-art converters Selected papers
Part 1: Architectures
First three chapters of van de Plassche’s textbookCh.1: The Converter as a black boxCh.2: Specifications of convertersCh.3: High-Speed A/D Converters
Chapter 2Specifications of converters
Digital data coding
TTL, CMOS, ECLSerial to parallel conversion
- Data latched out by latch clock- Directly drives switches in DA-converters- Output glitches
- Deglitching- Switch optimization- Accurate board layout for matched delays
Serial input register
Parallel data latches
Bit switches
Binary weighted networkReference
input
Analogoutput
Latch
Data
Clock
Digital coding schemes
Offset binary code Major carry transition for signal around zero Glitch sensitive
Sign-magnitude code Signal inversion around zero Low-level linearity issues
Twos complement Used for computational operations
DC specifications
Absolute accuracy Full-scale input or output compared to the absolute standard of the
National Bureau of Standards Mostly related to the reference source
Relative accuracy Deviation of the output signal or code from a straight line Also called integral non-linearity (INL) No missing codes (monotonicity): INL<±1/2LSB
000 001 010 011 100 101 110 1110
1/8
1/4
3/8
1/2
5/8
3/4
7/8
Analog output
Digitalinput
Nonlinearity calculation
Binary w. output bit: Full-scale value B:
Ideal step-size:
Linearity error of kth bit:
INL:
2mm mb
1 1
0 0
2 2 1n n
m nm m
m m
B
1
012 1 2 1
n
mm
n n
BS
1
02 1 22 1
n
mk km
k kn
1
1 11 0
1 1 10
22 1 2
2 1 2 1
n
nm nn km
n n m nn nm
Nonlinearity calculation II
Monotonicity: D/A: No increase in
analog output value when input increases by a value of one LSB:
000 001 010 011 100 101 110 1110
½-2LSB
½-1LSB
½
½+2LSB
Analog output
Digitalinput
½+1LSB
Non-monotonicconverter
Missingcode
1 1
10
2 1
2 1 2
1
2
n n
m nnm
LSB
INL LSB
To guarantee monotonicity the sum of errors for all bits must never exceed ½ LSB level
Other static specifications
DNL Quote from book: ”The difference between two adjacent analog
signal values compared to the step-size (LSB-weight) of a converter generated by transitions between adjacent pairs of digital code numbers over the full range of the converter” (...)
Offset: Non-zero output when zero input.
Temperature dependence: For thermal mismatch below ¼ LSB:
Supply voltage variations: Typically specified, e.g. ±5%
1
1
: 1
: 1
out m out m
input m input m
DAC DNL S C S C LSB
ADC DNL A Q A Q LSB
2 per degree C
4
n
T
Dynamic specification
SNR Signal power divided by
integrated noise power. Harmonics not included If harmonics included:
SNDR: Signal to noise and distortion ratio
6.02n+1.76 dB SFDR
Ratio between full-scale fundamental and largest harmonic distortion component
ENOB (SNDR-1.76)/6.02
Element matching vs. INL
Requirements: INL≤ ½ LSB See book for details.
Based on measurement of many samples. σ=mismatch standard variation.
ENOB and SDNR vs. INL model
Transfer-function with INL:
INL-model (differential):
Out vs. in with three coefficients in INL-model:
Gives odd harmonics:
Only one coefficient:
Resulting ENOB:
1 ( )out inV V INL LSB
2 4 6( ) cos(2 ) cos(4 ) cos(6 ).....INL LSB a t a t a t
2 4 6cos( ) 1 cos(2 ) cos(4 ) cos(6 )out sigV a t a t a t a t
2 2 4
4 6 6
1 11 cos( ) cos(3 )
2 2
1 1cos(5 ) cos(7 )
2 2
out sig sig
sig sig
V a a t a a a t
a a a t a a t
2 2
4
12
42 2distortion
aP a
2log 1 3
2log 2
42 24
1.5 2 2 //12 / 4
, INL
ns
INL s
S SENOB INL a q
N N q a
2log 1 3
2log(2)reduction
INLn
SFDR and IMD vs. INL model
Distortion: Quantization component: SFDR:
Intermodulation:
4
1 1
2 2distort sa a INL q
1.52 bitsNquantization sa q
1.520log 2 2bits bitsN NSFDR INL
2 1 2 2 4 1 4 2( ) cos(2 ) cos(2 ) cos(4 ) cos(4 ).....INL LSB a t a t a t a t
1 1 2 2
1 1sin sin
2 2sig sig sigV a t a t
1 1 2 2 2 1 2 2
1 1sin sin cos(2 ) cos(2 )
2 2out sig sigV a t a t a t a t
1 1 2 1 2
1 2 2 2 1
1int sin 2
41
int sin 24
sig
sig
a a t
a a t
12
1,2 2
22
int , bitsN
s
Sa INL q INL
a
2
1,2
20log 2 2int
bits bitsN NSINL SFDR
Glitches
Important for performance of DAC
Major carry-code transition Modelled with square glitch
with area/energy (for MSB glitch):
Compare to LSB-energy:
+
-
R
DAC
MSB
LSB
Vout
01111
10000
glitch difE At
12nLSB sE At
Noise
Thermal noise No correlation with q-noise:
In a 16b DAC with 98.1dB quantization-SNR, the thermal noise must be less than -108dB for 0.5dB loss in total SNR.
2 2
2
2
/1
/
system quantization thermal
quantizer
system quantizer
thermal
N N N
S NN N
S N
Noise
ADC: Noise dithers the comparator in an ADC
Estimating comparator output-noise by using probability of wrong desicion: Noise: σ = ½ LSB:
Bias quantizer ½ LSB over quantization-level:
s
2s
3s
3s
2s
s
0
Qj
Qj-1
Qj-2
Qj+1
Aj+1
Aj
Aj-1
2 2 2_ _ 3 _ 50.954 0.046 0.00006total qns LSB qns LSB qns LSBP q q q
2_1.37total qns LSBP q
2 2_ 2 _ 40.317 0.0027total qns LSB qns LSBP q q
2_1.14total qns LSBP q
s
2s
3s
3s
2s
s
0 Qj
Qj-1
Qj-2
Qj+1
Aj+1
Aj
Aj-1
Qj+2
Aj+2
Other error sources
Minimum reference step-size: The possibility noise amplitude is
bigger than kσ
Min. Reference step size should be 6-7 times greater than comparator RMS-noise
Bit-error rate Number of desicion errors For ADC typically 10-15 to 10-10
Max sampling-rate Rate where DR is decreased 3dB
Digital signal feed-through Couple HF signals to the output
22 1
2 ( )k
Q k ek
k 2Q(k)
3 2.9∙10-3
4 6.7∙10-5
5 5.9∙10-7
6 2.0∙10-9
7 2.6∙10-12
8 1.3∙10-15
Other error sources Distortion
Signal band also present at multiples of fs.
Inter-modulation products may occur when applied to analog amplifier.
Mixing fs-fin with fs+fin Product at 2fs Harmonic
Mixing 2(fs-fin) with fs+fin Product at fs-3fin Non-harmonic
Only harmonics in baseband if fs>4fin.
PSRR Immunity no power-supply noise
Settling-time Very important in any successive
approximation ADC (internal DAC) Aquisition-time
Track-command to response delay Limits max fs
fsfs-finfin fs+fin
fsfs-fin fs+fin
2fin
finfs-3fin
Other error sources Aperture-time
Time-difference between hold-command and the time the sample is taken
Can give input-dependent error in sample-and-hold amplifier
Sample-and-hold step Charge-feedthrough can give step in
transition from sample-to-hold phase Droop-rate
Discharge of hold-capacitor in hold-phase
Signal feed-through To capacitor in hold mode Must be attenuated 70-80dB in 8-10bit
ADC Noise in S/H-amplifier
Input-noise will be tracked Peak-noise must be below LSB-level
Other error sources
Overview of S/H-specifications Settling-time Aquisition-time Aperture time / jitter S/H step Droop rate Hold-mode feedthrough S/H amplifier noise
Other error sources Analog system bandwidth
In an ideal converter system the maximum analog bandwidth is equal to fs/2.
ERB Effective resolution bandwidth Bandwidth where resolution is
within -3dB of nominal. Figure of merit:
Standard for comparison
FOM expected to drop factor 10 every 10th year
2 2ENOBin
PowerFOM
f
468
1012141618202224
1kHz 10kHz 100kHz 1MHz 10MHz 100MHz 1GHz
1µW
1mW1W 1kW
FOM=1pJ
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