Fabrication Steps: P-well Process

Digital IC Design/ATEC D. Al-KhaliliFab./layout-4Fab./layout-4 1

Fabrication Steps: P-well Process

DiffusionVDD

Vo

N well

P+

P+

n+n+

Vinp+

N well

p+n+ n+p+ p+

Substrate p-type


Fabrication Steps: P-well Process

Diffusion

VDD

VoP well

P+

P+

n+n+

Vin

p+

N well

p+n+ n+p+ p+

Substrate p-type


Fabrication Steps

p+p+N well

n+ n+

Substrate P-type

N well

p+ p+n+ n+


Fabrication StepsOxidation

Substrate p-type

Patterning of N-well mask

Substrate p-type

oxide


Fabrication StepsDiffusion: N dopant,Removal of Oxide

Deposit Silicon Nitride

N-well

N-well

Si3N4


Fabrication StepsPatterning: Diffusion (active) mask

Oxidation

N-well

substrate

FOXFOX FOX

substrate


Fabrication Steps

Remove Si3N4Grow thin oxide

Deposit polysilicon

N-well

N-well

FOX FOX FOX

Thin oxide


Fabrication StepsPatterning of Polysilicon

FOXFOX FOX

N -well

Poly gates

substrate


Fabrication StepsP+ Layers and n+ Layer in the Layout

N well

p+ layer

n+ layer

polysilicon


Fabrication StepsFormation of n+ and p+ Diffusion Areas:N+ Diffusion: - Covering with photo-resist - Patterning of the n+ layer - Diffusion: n+ dopant

PRFOX

N-well

FOX FOX

p+ dopant


Fabrication StepsFormation of n+ and p+ Diffusion Areas:

P+ Diffusion:- Cover with photo-resist - Patterning of the n+ layer - Diffusion: n+ dopant

n+ dopant

PR

N-well

N-well

p+ p+

p+ p+ n+ n+


Fabrication Steps

P well

p+ layer

polysilicon

n+ layer

metal

contact


Fabrication StepsStrip PR and Deposit Oxide

Patterning of Contact Mask

SiO2FOX FOX FOX

N-well

Substrate

p+ p+ n+ n+

N-well

Substrate

contact


Fabrication StepsDeposit metal layer

Patterning of metal layer

Passivation

N-well

FOX FOX

SubstrateDeposit Passivation layer


CMOS: 3D Structure

N-well

p+ p+

n+ n+

Substrate (P-type)

FOX

FOX FOX


The Bulk Contacts

N well

p+ layer

n+ layer

metal

contact

polysilicon

n+ layer

p+ layer

(substrate)

G

S

D

D

G

S

VDD

GND

B

B

MP

MN

Vin Vout

Note: Butting contacts provide more efficientarea utilization

VDD

GND

N-Well


P-Well CMOS

p+ layer

n+ layer

metal

contact

n+ layer

p+ layer

P-well


Twin Tub/Double Layer Metal CMOS

Substrate

p-welln-wel l

metal IIPassivation

FOX

ViaSiO2Metal I

P well

Metal II

Via


Layout Design Rules Specifies geometrical constrains on the layout art

work Dictated by electrical and reliability constraints

with the capability of fabrication technology Addresses two issues:

» reproduction of features on silicon» interaction between layers

Main approaches to describe rules: based (scalability)» absolute

widthspacing

extensionspacing

overlap


Based CMOS Design Rules : N Well Process

A. N-well A.1 Minimum size 10 A.2 Minimum spacing 6 (Same potential) A.3 Minimum spacing 8 (Different potentials)

B. Active (Diffusion) B.1 Minimum size 3 B.2 Minimum spacing 3 B.3 N-well overlap of p+ 5 B.4 N-well overlap of n+ 3 B.5 N-well space to n+ 5 B.6 N-well space to p+ 3

n+

n+

p+

p+ B4=3 B3=5

B5=5

B6=3p+

B2=3

B1=3

N-well


Based CMOS Design Rules

C PolyI C.1 Minimum size 2 C.2 Minimum spacing 2 C.3. Spacing to Active 1 C.4. Gate extension 2

D. p-plus/n-plus D.1 Minimum overlap of Active 2 D.2 Minimum size 7 D.3 Minimum overlap of Active 1 in abutting contact D.4. Spacing of p-plus/n-plus to 3 n+/p+ gate

C2=2 C1=2

C4=2C3=1

D2=7 D2=7

D1=2

active active

n-plusp-plus



E. Contact E.1 Minimum size 2 E.2 Minimum spacing (Poly) 2 E.3 Minimum spacing (Active) 2 E.4 Minimum overlap Active)2 E.5 Minimum overlap of Poly 2 E.6 Minimum overlap of Metal 1 E.7 Minimum spacing to Gate 2

F. Metal 1 F.1 Minimum size 3 F.2 Minimum spacing 3

G. Via G.1 Minimum size 3 G.2 Minimum spacing 3 G.3 Minimum Metal I overlap1 G.4 Minimum Metal II overlap 1

E3=2E4=2

E1=2

E6=1

E5=2

F1=3

F2=3

H2=4

H1=3

G3,G4=1 G2=3Metal II

Metal I



H. Metal II H.1 Minimum size 3 H.2 Minimum spacing 4 I. Via2 I.1 Minimum size 2 I.2. Minimum spacing 3

J. Metal III J.1 Minimum size 8 J.2. Minimum spacing 5 J.3 Minimum Metal II overlap 2

K. Passivation K.1 Minimum opening 100 K.2 Minimum spacing 150


Layout of a CMOS Inverter Based Design Rules

B3

B4

C1

C4

G1

E4D1

E6

N-well

n-plus

Metal II

p-plus

metalI

ActiveVia

p-plus

n-plus


Stick Diagram Notation

• It helps to visualize the function as well as topology• It helps in floor planning• 4 layers for SLM: Poly, diffusion, metal, contact• 6 layers for DLM: Poly, Diffusion, Metal I, Metal II, Contact, Via• Construction Guidelines:

• When two wires of the same color intersects or touch, they are electrically connected.• Contacts represented by (X) and via by ( )• When poly crosses diffusion, a transistor is formed• PMOS transistors identified by a small circle around the poly-diffusion intersection


Stick Diagram Notation

G

S

D

D

G

S

VDD

GND

B

B

MP

MN

Vin Vout VinVout

VDD

GND


Mixed Notation

AB

C

C


Standard Cells

Modularized approach for layout Follows certain guidelines in designing

these modules Each module represents a basic

combinational or sequential logic function.

Each module has a standard height and variable width referred to as Standard Cell

A collection of these cells referred to as a Standard Cell Library

ASIC Designers deal with abstracted representation of these cells to construct a complete design

The abstracted representation is referred to as the Foot Print

Each abstracted representation consists of input and output terminals referred to as I/O Ports

Cell Name

I/O ports

Foot Print


Standard Cells

Inputport

Outputport


Standard Cells

InputPort

OutputPort

INV

INPUT OUTPUT

VDD

VSS


Standard Cells

Routing Channel

For DLM process, vertical routes use metal II. Horizontal routes use Metal I

Notice the connections between Metal I and Metal II

For Multi-level metal processescell rows are flipped and butted.

Routing can be made on top of the cell rows (More to come in section 5)


Yield Analysis

Yield is defined as : Number of Good chips on wafer X 100% Total Number of chips

Influenced by Defect density Chip area Design rule lithography dimensions Number of mask levels

Defects Crystal defects film deposition and growth defects photo-resist imperfections


Yield Analysis

Y e AD–=

Y 1 e A– D–AD

----------------------2

=

Models: 1. Seed’s model for large chips and low yields

A= chip area D= defect density

2. Murphy’s model for small chips and high yields

Fabrication Steps: P-well Process

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