VLSI Design Lecture 2: Basic Fabrication Steps and ...

32
VLSI Design Lecture 2: Basic Fabrication Steps and Layout and Layout Shaahin Shaahin Hessabi Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Sharif University of Technology Adapted with modifications from lecture notes prepared by Adapted with modifications from lecture notes prepared by the book author the book author (from Prentice Hall PTR) (from Prentice Hall PTR)

Transcript of VLSI Design Lecture 2: Basic Fabrication Steps and ...

Page 1: VLSI Design Lecture 2: Basic Fabrication Steps and ...

VLSI DesignLecture 2: Basic Fabrication Steps

and Layoutand Layout

ShaahinShaahin HessabiHessabiDepartment of Computer EngineeringDepartment of Computer Engineering

Sharif University of TechnologySharif University of TechnologyAdapted with modifications from lecture notes prepared by Adapted with modifications from lecture notes prepared by

the book author the book author (from Prentice Hall PTR)(from Prentice Hall PTR)

Page 2: VLSI Design Lecture 2: Basic Fabrication Steps and ...

TopicsTopics

Basic fabrication steps Basic fabrication steps. Transistor structures.

B i i b h i Basic transistor behavior. Latch up.

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 2 of 32

Page 3: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Our technologyOur technology

We will study a generic 180 nm technology (SCMOS We will study a generic 180 nm technology (SCMOS rules).– Assume 1 2V supply voltageAssume 1.2V supply voltage.

Parameters are typical values.P /S i d l f il bl f Parameter sets/Spice models are often available for 180 nm, harder to find for 90 nm.

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 3 of 32

Page 4: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Fabrication servicesFabrication services

Educational services: Educational services:– U.S.: MOSIS (has defined SCMOS rules)– EC: EuroPractice– EC: EuroPractice– Taiwan: CIC

Japan: VDEC– Japan: VDEC

Foundry = fabrication line for hire.F d i j f f b i d– Foundries are major source of fab capacity today.

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 4 of 32

Page 5: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Silicon LatticeSilicon Lattice

Transistors are built on a silicon substrate Transistors are built on a silicon substrate Silicon is a Group IV material

F l l i i h b d f i hb Forms crystal lattice with bonds to four neighbors

Si SiSi

Si SiSi

Si SiSi

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 5 of 32

Page 6: VLSI Design Lecture 2: Basic Fabrication Steps and ...

DopantsDopants

Silicon is a semiconductor Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V (Arsenic, Phosphorus): extra electron (n-type)p ( yp ) Group III (Boron): missing electron, called hole (p-type)

Si SiSi Si SiSi- +

As SiSi

Si SiSi

B SiSi

Si SiSi

+ -

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 6 of 32

Si SiSi Si SiSi

Page 7: VLSI Design Lecture 2: Basic Fabrication Steps and ...

p-n Junctionsp n Junctions

A junction between p-type and n-type semiconductor A junction between p type and n type semiconductor forms a diode.

Current flows only in one direction Current flows only in one direction

N Diff P DiffN-Diff P-Diff

anodecathode

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 7 of 32

Page 8: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Fabrication processesFabrication processes

IC built on silicon substrate: IC built on silicon substrate:– some structures diffused into substrate;– other structures built on top of substrate– other structures built on top of substrate.

Substrate regions are doped with n-type and p-type impurities (n+ = heavily doped)impurities. (n+ = heavily doped)

Wires made of polycrystalline silicon (poly), multiple l f l i ( l)layers of aluminum (metal).

Silicon dioxide (SiO2) is insulator.

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 8 of 32

Page 9: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Simple cross sectionSimple cross section

SiO2 metal3

metal2

metal1transistor via

n+ n++

poly

substratep+

substrate

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 9 of 32

Page 10: VLSI Design Lecture 2: Basic Fabrication Steps and ...

PhotolithographyPhotolithography

Mask patterns are put on wafer using photo-sensitiveMask patterns are put on wafer using photo sensitive material:

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 10 of 32

Page 11: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Process stepsProcess steps

First place tubs (wells) to provide properly-doped First place tubs (wells) to provide properly doped substrate for n-type, p-type transistors.a twin tub process:a twin-tub process:

p-tub n-tub

substrate

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 11 of 32

Page 12: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Process steps, cont’d.Process steps, cont d.

Pattern polysilicon before diffusion regions:Pattern polysilicon before diffusion regions:

p t b n t b

poly polygate oxide

p-tub n-tub

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 12 of 32

Page 13: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Process steps, cont’dProcess steps, cont d

Add diffusions performing self-masking:Add diffusions, performing self masking:

p t b n t b

poly poly

n+n+ p+ p+p-tub n-tubn+n+ p+ p+

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 13 of 32

Page 14: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Process steps, cont’dProcess steps, cont d

Start adding metal layers:Start adding metal layers:

metal 1 metal 1

poly polyvias

p-tub n-tubn+n+ p+ p+

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 14 of 32

Page 15: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Transistor structureTransistor structure

n-type transistor:n type transistor:

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 15 of 32

Page 16: VLSI Design Lecture 2: Basic Fabrication Steps and ...

0.25 micron transistor (Bell Labs)0.25 micron transistor (Bell Labs)

gate oxide

silicide

gate oxide

source/drain

poly

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 16 of 32

Page 17: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Transistor layoutTransistor layout

n-type (tubs may vary):n type (tubs may vary):

L

w

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 17 of 32

Page 18: VLSI Design Lecture 2: Basic Fabrication Steps and ...

NMOS TransistorNMOS Transistor

Four terminals: gate source drain body Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor

G t d b d d t– Gate and body are conductors– SiO2 (oxide) is a very good insulator

C ll d t l id i d t (MOS) it– Called metal – oxide – semiconductor (MOS) capacitor» Even though gate is

no longer made of metalGateSource Drain

PolysilicongSiO2

n+

p bulk Si

n+

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 18 of 32

Page 19: VLSI Design Lecture 2: Basic Fabrication Steps and ...

NMOS OperationNMOS Operation

Body is commonly tied to ground (0 V) Body is commonly tied to ground (0 V) When the gate is at a low voltage:

P t b d i t l lt– P-type body is at low voltage– Source-body and drain-body diodes are OFF

N t fl t i t i OFF– No current flows, transistor is OFFGateSource Drain

Polysilicon

SiO2

0n+

p bulk Si

n+DS

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 19 of 32

Page 20: VLSI Design Lecture 2: Basic Fabrication Steps and ...

NMOS Operation (cont’d.)p ( )

When the gate is at a high voltage: When the gate is at a high voltage:– Positive charge on gate of MOS capacitor– Negative charge attracted to body– Negative charge attracted to body– Inverts a channel under gate to n-type

Now current can flow through n type silicon from source– Now current can flow through n-type silicon from source through channel to drain, transistor is ON

GateSource DrainGateSource Drain

SiO2

Polysilicon

n+

p bulk Si

n+D

1

S

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 20 of 32

Page 21: VLSI Design Lecture 2: Basic Fabrication Steps and ...

PMOS TransistorPMOS Transistor

Similar but doping and voltages reversed Similar, but doping and voltages reversed– Body tied to high voltage (VDD)– Gate low: transistor ON– Gate low: transistor ON– Gate high: transistor OFF

Bubble indicates inverted behavior– Bubble indicates inverted behaviorGateSource Drain

Polysilicon

SiO2

n bulk Si

p+ p+

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 21 of 32

Page 22: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Drain current characteristicsDrain current characteristics

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 22 of 32

Page 23: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Drain currentDrain current

Linear region (Vd < V - Vt): Linear region (Vds < Vgs Vt):– Id = k’ (W/L)[(Vgs - Vt)Vds - 0.5 Vds

2]

Saturation region (V ≥ V V ): Saturation region (Vds ≥ Vgs - Vt):– Id = 0.5k’ (W/L)(Vgs - Vt) 2

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 23 of 32

Page 24: VLSI Design Lecture 2: Basic Fabrication Steps and ...

180 nm transconductances180 nm transconductances

Typical values:Typical values: n-type:

k ’ 170 A/V2– kn’ = 170 A/V2

– Vtn = 0.5 V

p-type:– kp’ = 30 A/V2

– Vtp = -0.5 V

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 24 of 32

Page 25: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Current through a transistorCurrent through a transistor

Use 180 nm parameters Let W/L = 3/2 Measure atUse 180 nm parameters. Let W/L 3/2. Measure at boundary between linear and saturation regions.

V = 0 7V: Vgs = 0.7V:Id = 0.5k’(W/L)(Vgs-Vt)2 = 0.5(170 A/V2)(3/2)(0.7-0.5)2 = 5.1 AA

Vgs = 1.2V:I 62 AId = 62 A

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 25 of 32

Page 26: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Basic transistor parasiticsBasic transistor parasitics

Gate to substrate also gate to source/drain Gate to substrate, also gate to source/drain. Source/drain capacitance, resistance.

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 26 of 32

Page 27: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Basic transistor parasitics, cont’dBasic transistor parasitics, cont d

Gate capacitance C Determined by active area Gate capacitance Cg. Determined by active area. Source/drain overlap capacitances Cgs, Cgd.

Determined by source/gate and drain/gate overlapsDetermined by source/gate and drain/gate overlaps. Independent of transistor L.

C C W– Cgs = Col W

Gate/bulk overlap capacitance.

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 27 of 32

Page 28: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Latch-upLatch up

CMOS ICs have parastic silicon-controlled rectifiers CMOS ICs have parastic silicon controlled rectifiers (SCRs).

When powered up SCRs can turn on creating low When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chipdestroy chip.

Early CMOS problem. Can be solved with proper i it/l t t tcircuit/layout structures.

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 28 of 32

Page 29: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Parasitic SCR structure

There exist parasitic bipolar transistors (pnp and npn) in a CMOS structure.

Additionally, the well and substrate have resistances RW and RS, respectively.

Twin tub

n tub

A

YGND VDD

Rwell Vwell

n+

p substrate

p+ n+p+ n+ p+

n wellRsub

RwellVwell

RsubVsub

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 29 of 32

substrate tap well tapVsub

Page 30: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Parasitic SCRParasitic SCR

i i I V b h iModern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 30 of 32

circuit I-V behavior

Page 31: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Solution to latch-upSolution to latch up

Use tub ties to connect tub to power rail Use enough toUse tub ties to connect tub to power rail. Use enough to create low-voltage connection.

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 31 of 32

Page 32: VLSI Design Lecture 2: Basic Fabrication Steps and ...

Tub tie layoutTub tie layout

p+

metal (VDD)

p-tub

Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 32 of 32