ESE 570: Digital Integrated Circuits and VLSI …ese570/spring2019/handouts/...Gate Layout Algorithm...
Transcript of ESE 570: Digital Integrated Circuits and VLSI …ese570/spring2019/handouts/...Gate Layout Algorithm...
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ESE 570: Digital Integrated Circuits and VLSI Fundamentals
Lec 16: March 19, 2019 Euler Paths and Energy Basics &
Optimization
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Lecture Outline
! Pass Transistor Logic ! Logic Comparison ! Transmission Gates ! Euler Paths ! Energy Basics & Optimization
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Pass Transistor Logic
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Restore Output
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Voltage of Chain
! What is voltage at output?
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Vdd=1V Vthn=-Vthp=0.3V
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How compare
! Compare
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DC Analysis – chain of 3
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DC Analysis – chain of 6
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Conclude
! Can chain any number of pass transistors and only drop a single Vth
9
…
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Transient
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Transient: Zoomed Closeup
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Gate Cascade?
! What are voltages?
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Vdd=1V Vthn=-Vthp=0.3V
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Chain Together
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Cascaded Pass Gates
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Delay A=1, B=0, CDB=Cdiff=Cd?
! What’s the equivalent RC circuit?
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3Cd 2Cd+2Cg
2Cg
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Delay A=1, B=0, CDB=Cdiff=Cd?
! What’s the equivalent RC circuit? " What is the total delay?
" From A to Y
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3Cd 2Cd+2Cg
2Cg
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17
! What’s the equivalent RC circuit?
Delay A=1, B=1, CDB=Cdiff=Cd?
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2Cg
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Cascading Pass Gates
/b
b
/b
W=1 L=1
W=1 L=1
/c
c
/c
/d
d
/d
y
/y
W=1 L=1
W=1 L=1
W=1 L=1
W=1 L=1
A
one stage
W=1 L=1
W=1 L=1
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! Extract key path
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Chain without Inverters
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/a
a
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Logic Types
! CMOS Gates " Dual pull-down and pull-up networks, only one enabled at a time " Performance of gate is strong function of the fanin of gate
" Techniques to improve performance include sizing, input reordering, and buffering (staging)
! Ratioed Gates " Have active pull-down (-up) network connected to load device " Reduced gate complexity at expense of static power asymmetric transfer
function " Techniques to improve performance include sizing to improve noise margins and reduce
static power
! Pass Gates " Implement logic gate as switch network for reduced area and load
capacitance " Long cascades of switches result in quadratic increase in delay " Also suffer from reduced noise margins (VT drop)
" Use level-restoring buffers to improve noise margins
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Transmission Gates
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CMOS Transmission Gates
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CLK
CLK
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CMOS Transmission Gates
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CMOS Transmission Gates
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at t = 0-: Vin = 0, Vout = 0 at t = 0+: Vin = 0 -> VDD
Note
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CMOS Transmission Gates
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at t = 0-: Vin = 0, Vout = 0 at t = 0+: Vin = 0 -> VDD
Note
- VTp
≥ ≥
≤
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CMOS Transmission Gates
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at t = 0-: Vin = 0, Vout = 0 at t = 0+: Vin = 0 -> VDD
Note
- VTp
≥ ≥
≤
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CMOS Transmission Gates
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at t = 0-: Vin = 0, Vout = 0 at t = 0+: Vin = 0 -> VDD
Note
- VTp
≥ ≥
≤
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CMOS Transmission Gates
28 - VTp
≥ ≥
≤
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Transmission Gate, Req
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kp (- VDD - VTp)2
kp [2(- VDD - Vtp) (Vout – VDD) - (Vout – VDD)2]
kp [2(- VDD - Vtp) - (Vout – VDD)]
kp [2(- VDD - Vtp) (Vout – VDD) - (Vout – VDD)2]
kp [2(- VDD - Vtp) - (Vout – VDD)]
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Transmission Gate, Req
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Transmission Gate, Req
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Transmission Gate Layouts
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Transmission Gate Layouts
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Euler Paths
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NOR2 Layout
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NAND2 Layout
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Layout of Complex CMOS Gate
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DS DSGND
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Layout of Complex CMOS Gate
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d
d d
d
d
i.e. n, p Euler paths with identical sequences of inputs
diffusion breaks
Layout of Complex CMOS Gate
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Minimize Number of Diffusion Paths
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Minimize Number of Diffusion Paths
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Minimize Number of Diffusion Paths
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Minimize Number of Diffusion Paths
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Gate Layout Algorithm
! 1. Find all Euler paths that cover the graph ! 2. Find common n- and p- Euler paths ! 3. If no common n- and p- Euler paths are found in
step 2, partition the gate n- and p- graphs into the minimum number of sub-graphs that will result in separate common n- and p- Euler paths
44
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Energy and Power Basics
Review
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Total Power
! Ptot ≈ Pstatic + Pdyn + Psc
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Static
Leakage Power
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Operating Modes
! Steady-State: Vin=Vdd
" PMOS: subthreshold " NMOS: resistive
48
€
IDSp = −IS#WL
$
% &
'
( ) e
−VGS −VTnkT / q
$
% &
'
( )
1− eVDSkT / q$
% &
'
( )
$
% & &
'
( ) ) 1− λVDS( )
IDSn = µnCOXWL
!
"#
$
%& VGS −VT( )VDS −
VDS2
2(
)*
+
,-
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Static Power – Ratioed Logic
! Istatic ?
! Input low-Output high? " Ileak
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Static Power – Ratioed Logic
! Istatic ?
! Input low-Output high? " Ileak
! Input high-Output low? " Ipmos_on
" ~Vdd/Rp,on
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Total Static Power
! Pstatit ≈ p(Vout=low)V2/Rp,on
+p(Vout=high)VI’s(W/L)e-Vt/(nkT/q)
p(Vout=low) – probability the output is low p(Vout=high) – probability the output is high p(Vout=high)=1-p(Vout=low)
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Switching
Dynamic Power
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Switching Currents
! Iswitch(t) = Isc(t) + Idyn(t)
53
Isc
Idyn
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Isw
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Switching Energy
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! Do we know what this is?
! What is Q? Idyn
Q = Idyn (t)dt∫
E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫
€
Q = CV = I(t)dt∫
€
E = CVdd2
Capacitor charging energy
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Switching Power
! Every time output switches 0#1 pay: " E = CV2
! Pdyn = (# 0#1 trans) × CV2 / time
! # 0#1 trans = ½ # of transitions
! Pdyn = (# trans) × ½CV2 / time
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Switching
56
Short Circuit Power
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Short Circuit Power
! Between VTN and Vdd - VTP
" Both N and P devices conducting
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Short Circuit Power
! Between VTN and Vdd - VTP
" Both N and P devices conducting
! Roughly:
58
Isc
Vin
time
Vout
Isdp
time
time
time
Vthn
Vdd
Vdd
Vdd-Vthp
Isc
tsc tsc Penn ESE 570 Spring 2019 – Khanna
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Vin
time
Vout
Isdp
time
time
time
Vthn
Vdd
Vdd
Vdd-Vthp
Isc
tsc tsc
Peak Current
! Ipeak around Vdd/2 " If |VTN|=|VTP| and sized equal rise/fall
59
€
IDS ≈νsatCOXW VGS −VT −VDSAT
2%
& '
(
) *
€
I(t)dt∫ ≈ Ipeak × tsc ×12%
& ' (
) *
€
E =Vdd × Ipeak × tsc ×12#
$ % &
' (
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Short Circuit Energy
! Make it look like a capacitance, CSC
" Q=I×t " Q=CV
60
E =Vdd × I peak × tsc ×12"
#$%
&'
"
#$
%
&'
E =Vdd ×QSC
E =Vdd × (CSCVdd ) =CSCV2dd
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Short Circuit Energy
! Every time switch " Also dissipate short-circuit energy: E = CV2
" Different C = Csc
" Ccs “fake” capacitance (for accounting)
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Short Circuit Energy
! When transistors switch, both nMOS and pMOS networks may be nano-tarily ON at once
! Leads to a blip of “short circuit” current ! < 10% of dynamic power if rise/fall times are
comparable for input and output ! We will generally ignore this component in hand
analysis, but simulated measured results include it
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Switching Waveforms
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Switching Waveforms
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Switching Power
! Every time output switches 0#1 pay: " E = CV2
! Pdyn = (# 0#1 trans) × CV2 / time
! # 0#1 trans = ½ # of transitions
! Pdyn = (# trans) × ½CV2 / time
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Charging Power
! Pdyn = (# trans) × ½CV2 / time ! Often like to think about switching frequency ! Useful to consider per clock cycle
" Frequency f = 1/clock-period
! Pdyn = (#trans/clock) ½CV2 f
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Charging Power
! Pdyn = (# 0#1 trans) × CV2 / time ! Often like to think about switching frequency ! Useful to consider per clock cycle
" Frequency f = 1/clock-period
! Pdyn = (# 0#1 trans/clock) CV2 f
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Switching Power
! Pdyn = (#0#1 trans/clock) CV2 f ! Let a = activity factor
a = average #tran0#1/clock
! Pdyn = aCV2 f
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Activity Factor
! Let a = activity factor " a = average #tran0#1/clock
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a = p(outi = 0)p(outi+1 =1)
a =N02NN12N
=N0(2
N − N0 )22N
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Activity Factor
! Let a = activity factor " a = average #tran0#1/clock
Penn ESE 570 Spring 2019 - Khanna 70
a = p(outi = 0)p(outi+1 =1)
a = N0
2NN12N
=N0 (2
N − N0 )22N
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Reduce Dynamic Power?
! Pdyn = aCV2 f
! How do we reduce dynamic power?
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Reduce Activity Factor
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A B
C D
O1
O2
F
A B
C
D
O1
O2
F
Tree Chain
a = p(outi = 0)p(outi+1 =1)
a = N0
2NN12N
=N0 (2
N − N0 )22N
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Reduce Activity Factor
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A B
C D
O1
O2
F
A B
C
D
O1
O2
F
Tree Chain
a = p(outi = 0)p(outi+1 =1)
a = N0
2NN12N
=N0 (2
N − N0 )22N
3/16
3/16
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Reduce Activity Factor
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A B
C D
O1
O2
F
A B
C
D
O1
O2
F
Tree Chain
a = p(outi = 0)p(outi+1 =1)
a = N0
2NN12N
=N0 (2
N − N0 )22N
3/16
3/16
15/256
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Reduce Activity Factor
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A B
C D
O1
O2
F
A B
C
D
O1
O2
F
Tree Chain
3/16
7/64
15/256
a = p(outi = 0)p(outi+1 =1)
a = N0
2NN12N
=N0 (2
N − N0 )22N
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Reduce Activity Factor
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A B
C D
O1
O2
F
A B
C
D
O1
O2
F
Tree Chain
3/16
7/64
15/256
a = p(outi = 0)p(outi+1 =1)
a = N0
2NN12N
=N0 (2
N − N0 )22N
3/16
3/16
15/256
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Total Power
! Ptot = Pstatic + Psc + Pdyn
! Psw = Pdyn + Psc ≈ a(CloadV2f)
! Ptot ≈ a(CloadV2f) + VI’s(W/L)e-Vt/(nkT/q)
! Let a = activity factor a = average #tran0#1/clock
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Idea
! CMOS " Design for worst case input switching case and delay
! There are other logic disciplines " Ratioed logic " Can use pass transistors for logic
" Transmission gates " Will see in use in dynamic logic
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Midterm Exam
! Midterm – 3/21 " During class; starts at exactly 1:30pm, ends at exactly 2:50pm (80
minutes) " Location: College Hall 200 " Old exams posted on old course websites " Covers Lec 1- 14 + in-class worksheet " Closed book, no notes or cheat sheets " Calculators allowed and recommended, no smart phones
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Midterm Topics List
! Identify CMOS/non-CMOS
! Any logic function $# CMOS gate
! Noise Margins ! Circuit first order
switching rise/fall times " Output equivalent
resistance " Load capacitance
! Transistor " Regions of operation " Parasitic Capacitance
Model
! Layout and stick diagrams
! Sizing ! 1st order delay
" Worst case " Elmore delay
! Ratioed logic ! Pass logic 80 Penn ESE 570 Spring 2019 – Khanna