ESD Evaluation of the Emerging MuGFET Technology C. Russ et. al 2005 ESD/EOS Conference.
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Transcript of ESD Evaluation of the Emerging MuGFET Technology C. Russ et. al 2005 ESD/EOS Conference.
ESD Evaluation of the Emerging MuGFET Technology
C. Russ et. al 2005 ESD/EOS Conference
Slide 2
Oh No! Is ESD Going to be MuGGed by Yet Another Technology Development??
Dr. MuGFETGive me your ESD!
Slide 3
Purpose of this work
• Introduce the exciting new Multi-Gate Advanced Transistor Technology called the “MuGFET” and assess its sensitivity to high current ESD behavior
• Investigate suitable ESD protection methods for this new technology
Slide 4
Outline
Introduction: MultiGate FETs (MuGFETs)
ESD Characterization
– Fully depleted (FD) MuGFETs
– Partially depleted (PD) planar FETs
– Diodes
Failure analysis
Protection approaches
Conclusions
Slide 5
Introduction (1)
Classical FET in Bulk Si
SD
GL W
• Scaling expected to become difficult due to Short Channel Effects (32nm node and beyond)
SiO 2
Si
Gate
current current
Slide 6
Introduction (2)
Planar FET Device in SOI
SD
GL W
• Low junction capacitance speed!
• Good body control in fully depleted SOI– Requires costly wafers with ultra-thin Si-film
SiO 2
Si
Gate
current current
Slide 7
Introduction (3)MuGFET Device (or “Fin”-FET)
SD
GL
SiO 2
Si
Gate
• Channel enclosed by multiple (2, 3, 4) gates Best body control (fully depleted) Suppression of Short Channel Effect
• Best candidate for continued technology scaling
current
2 gates @ sides: double-gate
3 gates @ sides+top: tri-gate
current
W
Slide 8
Introduction (4)
S DG
finS D
G
fintop gate electrode
WFIN
Fu
lly
de
ple
ted
BOX
gate
side gate electrodes
HFIN
top gate electrode
WFIN
Fu
lly
de
ple
ted
BOX
gate
side gate electrodes
HFIN
Fu
lly
de
ple
ted
• Fin height: 60-88nm (present), 30-40nm (target)
• Fin width: 50nm (present), 20-30nm (target)
• Capability to carry ESD current?
Slide 9
Outline
Introduction: MultiGate FETs (MuGFETs)
ESD Characterization
– Fully depleted (FD) MuGFETs
– Partially depleted (PD) planar FETs
– Diodes
Failure analysis
Protection approaches
Conclusions
Slide 10
Test structures
SCGS
Lg
MD
R
Wgeo
LGATE
SOURCE
DRAINN+
GA
TE
N+
Planar SOIpartially depleted (PD)
Wgeo
SOURCE
GA
TE
Wfin=50nm
200nm
Lg
a S
pitchLGATE
DRAINN+
N+
MuGFETfully depleted (FD)
a D
Slide 11
Test structures
CAp+ n+
G
Gated diode
• NMOS and Gate diodes available as MuGFET (‘Fin’) and planar SOI types
• Fin width = 50nm, Fin heights = 88 and 60nm
• Nickel silicided (no silicide blocking)
SDn+ n+
G
NickelSilicide
NMOS
Buried oxide Buried oxide
Slide 12
MuGFET: Grounded Gate NMOS
• Unprecedented high ESD sensitivity failure instantaneous after breakdown!
• L pushes out breakdown, but no snapback visible
Slide 13
MuGFET: MOS-diode, Gate tied high
• Gate biasing allows moderate MOS current flow
• Damage occurs as soon as Vbd of GGNMOS-case is reached non-uniform current flow?
Slide 14
Planar PD SOI NFET: Grounded Gate
• More robust (~2mA/um), reproducible and scalable
• Very steep on-characteristics
• L pushes out BD, minor snapback occurs
Slide 15
• Excellent ESD performance (Fin-type and planar)!
• Fin-type diodes show less sensitivity to tsi
Gated Diodes: Fins + Planar (fwd. mode)
It2 [mA/um]
film thickness tsi
88nm 60nm
Fin-type
500 fins
Wsi=25um
16.8 15.2
Planar
W=50um11.6 9.6
Slide 16
0
0.01
0.02
0.03
0.04
0.05
4 5 6 7 8 9 10
FinFETp-typeFinFETn-typeplanarp-typeplanarn-type
curr
ent [
A]
voltage [V]
It2• Breakdown voltage
much higher than for any FET
• Fin-type diodes in BD do not show premature failure as seen in NFETs resistive ballasting
Gated Diodes: Fins + Planar (rev. mode)
Slide 17
Outline
Introduction: MultiGate FETs (MuGFETs)
ESD Characterization
– Fully depleted (FD) MuGFETs
– Partially depleted (PD) planar FETs
– Diodes
Failure analysis
Protection approaches
Conclusions
Slide 18
Failure Analysis: NFETs
S D
G
90nm
PlanarPD SOI
• Planar device: uniform damage along gate width– reasonable ESD performance
• MuGFET: localized damage of neighboring fins– extremely low ESD performance
D80nm
ESD
SDS
G G
metal
MuGFET
No
dam
age
Slide 19
Failure Analysis: Diodes (fwd. mode)
• MuGFET diode: uniform damage of fins– high ESD performance– intrinsic current capability of technology reached
C
metalmetal poly
500nm
A
ESD
Mu
GF
ET
AC
metalmetal poly
500nm
Pla
nar
• Planar diode: no failure in silicon (contact failure?)
Slide 20
Failure Analysis: Pulse Width vs. It2
It2 [mA]
Tpulse
100ns 500ns 2500ns
Planar NMOS W=50um
75-80 60-69 49-57
FinFET diode 500 fins, Wsi=25um
380 290 230
Planar diode W=50um
480 335 235
• ‘Wunsch-Bell’-unlike characteristics obtained• Planar MOS and FinFET diode:
– smaller sensitivity due to more heat sinking
Slide 21
Protection Approaches
0
0.5
1
1.5
0 1 2 3 4 5
FD MuGFET
PD planar
norm
aliz
ed
curr
ent [
mA
/um
]
voltage [V]
Lpoly=250nmplanar: W=50umFin: Wsi=500x50nm=25um
Vt1,FD
Vt1,PD
• Input protection: dual diode + power clamp approach• Output drivers: PD planar device as local clamp provides solution
integrated into process• Provides both performance and ESD protection
FD MuGFET driver
PD planarESD clamp
IOpad
Slide 22
ConclusionsNew issues for emerging Multigate technologies:– FinFET MOS: extremely ESD-susceptible
• Local burn-out of fins– Planar MOS: reasonable ESD hardness
• Uniform failure signature (even fully silicided!)• Available in same process• Lower trigger than FinFET local clamp
– Gate-biased MOS: • Possible as protection, BJT conduction must
strictly be avoided– Gated diodes (Fin-type and planar):
• Diodes needed in any protection scheme• FinFET diodes: high ESD currents possible!
Gate Dielectric Integrity along the Road Map of CMOS Scaling including Multi-Gate FET, TiN Metal Gate, and HfSiON High-k Gate Dielectric
T. Pompl et. al IRPS Conference
Infineon TechnologiesTexas Instruments
Slide 24
• Investigate:
Influences of multi-gate architecture and metal gate on gate dielectric reliability.
• Demonstrate:
Dielectric reliability trend along the road map towards a CMOS process using triple gate architecture, metal gate, and HfSiON gate dielectric.
Purpose
Slide 25
fully-depleted triple gate FET with poly-Si
gate and SiO2 (ISSG: 20 Å)
fully-depleted triple gate FET with TiN/poly-Si gate and SiO2
(ISSG: 17 Å)
fully-depleted triple gate FET with TiN/poly-Si gate and HfSiON
(ALD & post anneal in NH3, EOT: 10.5 Å,
20% Si, 7-8% N, bottom SiO2: 8 Å)
TEM Cross Sections of Vertical Silicon Fin
Slide 26
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
210-1-2
log(time (s))log(time (s))210-1-2
= 1.31
NFETtriple gatepoly, SiO
2
ln(-
ln(1
-F))
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
= 1.02
PFETtriple gatepoly, SiO
2
ln(-
ln(1
-F))
State of the art gate dielectric reliability can be achieved for CMOS processes using vertical multi-gate architectures.
The total length of tested top fin edge is 1.5 m per distribution.
High Volume TDDB checks for Weak Spots
Slide 27
10-1 100 101 102 103-5
-4
-3
-2
-1
0
1
2
Orientationon {100}substrate
0° 45° 90°
NFETtriple gatepoly, SiO
2
ln(-
ln(1
-F))
time (s)
No major influence on time to breakdown.Important also for SiO2 channel interface layer of high-k stacks.
Orientation of the silicon fin on {100} substrate:
SiO2 grown on silicon side walls with different crystal orientations.
Influence of Crystal Orientation
Slide 28
2.0 2.5 3.0 3.5 4.0 4.5100
101
102
103
104
105
EOT17Å
EOT20Å
EOT10.5Å
SiO2 & poly
SiO2 & TiN
HfSiON & TiNNFETtriple gate
t63%
(s)
gate voltage (V)
SiO2 & TiN: NFET meets standard reliability performance.HfSiON & TiN: NFET becomes more critical at stress level.
Expectations from thickness scaling of poly-Si/SiO2 towards
using 6.5 dec. in time per nm.
NFET: Time To Breakdown vs. Gate Voltage
17 Å
10.5 Å
Slide 29
-4.5 -4.0 -3.5 -3.0 -2.5 -2.0100
101
102
103
104
105
EOT10.5Å
EOT20Å
EOT17Å
SiO2 & poly
SiO2 & TiN
HfSiON & TiNPFETtriple gate
t63%
(s)
gate voltage (V)
SiO2 & TiN: PFET becomes more critical at stress level.HfSiON & TiN: PFET meets standard reliability performance.
PFET: Time To Breakdown vs. Gate Voltage
Expectations from thickness scaling of poly-Si/SiO2 towards
using 6.5 dec. in time per nm.
17 Å
10.5 Å
Slide 30
0 1 2 3
10-8
10-7
10-6
10-5
10-4
10-3
3
21
NFETtriple gate
gate
curr
ent (A
)
gate voltage (V)-3 -2 -1 0
10-8
10-7
10-6
10-5
10-4
10-3
321
1: SiO2 & poly, EOT=20Å
2: SiO2 & TiN, EOT=17Å
3: HfSiON & TiN, EOT=10.5Å
PFETtriple gate
gate
curr
ent (A
)
NFET: strong dependence of gate leakage on gate voltage needs to be considered for gate dielectric reliability.
1: SiO2 & poly-Si
2: SiO2 & TiN
PFET becomes equal to NFET
3: HfSiON & TiN
NFET gate leakage strongly increased compared to PFET.
Due to asymmetry of the high-k stack.
Gate Leakage Current vs. Gate Voltage in Inversion Biasing Mode
Slide 31
State of the art gate dielectric reliability can be achieved for CMOS processes using vertical multi-gate architectures.
GOX reliability trend along the road map of CMOS scaling will be dominated by metal gates and high-k dielectrics.
The use of metal gate increases gate leakage current density and reduces SiO2 reliability margin for PFET devices compared to poly-Si/SiO2.
NFET & HfSiON: the extrapolation of dielectric reliability to use conditions needs to consider the strong dependence of gate leakage on gate voltage.
PFET & HfSiON: the dielectric reliability meets the level of a standard poly-Si/SiO2 gate stack of same EOT.
Conclusions